SG11201503217TA - Apparatuses and methods for memory operations having variable latencies - Google Patents

Apparatuses and methods for memory operations having variable latencies

Info

Publication number
SG11201503217TA
SG11201503217TA SG11201503217TA SG11201503217TA SG11201503217TA SG 11201503217T A SG11201503217T A SG 11201503217TA SG 11201503217T A SG11201503217T A SG 11201503217TA SG 11201503217T A SG11201503217T A SG 11201503217TA SG 11201503217T A SG11201503217T A SG 11201503217TA
Authority
SG
Singapore
Prior art keywords
apparatuses
methods
memory operations
variable latencies
latencies
Prior art date
Application number
SG11201503217TA
Inventor
Graziano Mirichigni
Corrado Villa
Luca Porzio
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of SG11201503217TA publication Critical patent/SG11201503217TA/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
SG11201503217TA 2012-10-26 2013-10-25 Apparatuses and methods for memory operations having variable latencies SG11201503217TA (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201261719321P 2012-10-26 2012-10-26
US13/794,471 US9754648B2 (en) 2012-10-26 2013-03-11 Apparatuses and methods for memory operations having variable latencies
PCT/US2013/066949 WO2014066845A1 (en) 2012-10-26 2013-10-25 Apparatuses and methods for memory operations having variable latencies

Publications (1)

Publication Number Publication Date
SG11201503217TA true SG11201503217TA (en) 2015-05-28

Family

ID=50545362

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201503217TA SG11201503217TA (en) 2012-10-26 2013-10-25 Apparatuses and methods for memory operations having variable latencies

Country Status (7)

Country Link
US (3) US9754648B2 (en)
EP (1) EP2912558B1 (en)
JP (1) JP6006885B2 (en)
KR (1) KR101747570B1 (en)
CN (1) CN105264505B (en)
SG (1) SG11201503217TA (en)
WO (1) WO2014066845A1 (en)

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Publication number Publication date
JP6006885B2 (en) 2016-10-12
US20140122822A1 (en) 2014-05-01
EP2912558A4 (en) 2016-10-05
CN105264505B (en) 2019-04-05
CN105264505A (en) 2016-01-20
EP2912558B1 (en) 2020-12-16
US9754648B2 (en) 2017-09-05
EP2912558A1 (en) 2015-09-02
US20170309318A1 (en) 2017-10-26
US10885957B2 (en) 2021-01-05
KR101747570B1 (en) 2017-06-14
US20190080733A1 (en) 2019-03-14
WO2014066845A1 (en) 2014-05-01
KR20150104557A (en) 2015-09-15
US10163472B2 (en) 2018-12-25
JP2015536503A (en) 2015-12-21

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