CN109935252B - Memory device and operation method thereof - Google Patents
Memory device and operation method thereof Download PDFInfo
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- CN109935252B CN109935252B CN201711360150.3A CN201711360150A CN109935252B CN 109935252 B CN109935252 B CN 109935252B CN 201711360150 A CN201711360150 A CN 201711360150A CN 109935252 B CN109935252 B CN 109935252B
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Abstract
The embodiment of the invention discloses a memory device which comprises a memory array, a logic circuit, a sensing amplifier circuit and a read buffer. The logic circuit is used for responding to a reading instruction and an initial address and executing a reading operation. During a read operation, the logic circuit finds a target datum in the memory array according to the initial address. The sense amplifier circuit is used for reading out target data from the memory array during a read operation. The read buffer is used for buffering and outputting target data during read operation. When an interrupt event occurs during a read operation, the read buffer retains a cache content of the read buffer, and the logic circuit records a read status.
Description
Technical Field
The invention relates to a memory device and a reading operation method thereof.
Background
With the advent of the computer age, computer systems have been widely used in a variety of electronic products (e.g., personal computers, mobile phones, etc.). Generally, a computer system is composed of hardware and software. Memory is one of the important components of hardware.
The memory may be used to store data and read it when needed. In the conventional memory, during reading a piece of data, if the interruption is forced for some reason (for example, other instructions with higher priority than the reading instruction are received), the reading is invalid. The read portion of the data is discarded. In other words, if the memory is interrupted during the read operation, it takes extra time to restart the read operation from the beginning.
In view of the above problems, it is an important issue to provide a memory device and a read operation method thereof.
Disclosure of Invention
To achieve the above objective, an embodiment of the present invention discloses a memory device, which includes a memory array, a logic circuit, a sense amplifier circuit, and a read buffer. The logic circuit is used for responding to a reading instruction and an initial address and executing a reading operation. During a read operation, the logic circuit finds a target datum in the memory array according to the initial address. The sense amplifier circuit is used for reading out target data from the memory array during a read operation. The read buffer is used for buffering and outputting target data during read operation. When an interrupt event occurs during a read operation, the read buffer retains a cache content of the read buffer, and the logic circuit records a read status.
To achieve the above objective, an operating method of a memory device according to an embodiment of the present invention includes the following steps. A read command and an initial address are received. In response to the read command, a read operation is performed. The reading operation comprises finding out a target data according to the initial address; reading out the target data and caching the target data to a read buffer; and outputting the target data. When an interrupt event occurs during a read operation, a cache content of the read buffer is retained and a read status is recorded.
The memory device and the operation method thereof according to the embodiment of the invention can reduce the time required for continuously reading the target data after the reading operation of reading the target data is interrupted, thereby improving the overall efficiency of the memory device.
In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments is made with reference to the accompanying drawings, in which:
drawings
FIG. 1 is a block diagram of a memory device according to an embodiment of the invention.
FIG. 2 is a flow chart showing a read operation method of a memory device according to an embodiment of the invention.
FIG. 3 is a timing diagram of a memory device according to an embodiment of the invention.
[ notation ] to show
10: memory device
100: logic circuit
102: memory array
104: sense amplifier circuit
106: read buffer
90: controller
CSB, SCLK, SIO: signal line
S201 to S209: step (ii) of
C _ read: read instruction
A: initial address
L: delay time
D _ out1, D _ out 2: data output
E: interrupt event
C _ readcon: continue reading instruction
Detailed Description
Referring to fig. 1, fig. 1 is a block diagram of a memory device according to an embodiment of the invention. The memory device 10 is coupled to a controller 90 and controlled by the controller 90. In the present embodiment, the transmission Interface between the memory device 10 and the controller 90 is, for example, a Serial Peripheral Interface (SPI), which is not limited in the present invention. The memory device 10 is coupled to the controller 90, for example, by at least three signal lines CSB, SCLK, SIO.
The controller 90 selects or deselects the memory device 10 via the signal line CSB. When the controller 90 selects the memory device 10, the memory device 10 is in an operable state; conversely, when the controller 90 does not select the memory device 10, the memory device 10 is in an inoperable state. When the memory device 10 is selected by the controller 90, the controller 90 can transmit a clock signal to the memory device 10 through the signal line SCLK to control the operation timing of the memory device 10. The controller 90 transmits a write command, a read command, an erase command, and the like to the memory device 10 through the signal line SIO. When the memory device 10 receives an instruction from the controller 90, a corresponding operation may be performed depending on the type of the instruction. In addition, the controller 90 and the memory device 10 can also perform data transmission through the signal line SIO, for example, in a write operation, the controller 90 transmits data to be written to the memory device 10 through the signal line SIO; in a read operation, the memory device 10 transfers read data to the controller 90 through the signal line SIO.
The memory device 10 includes a logic circuit 100, a memory array 102, a sense amplifier circuit 104, and a read buffer 106.
The logic circuit 100 is used to receive instructions from the controller 90 and operate the memory array 102, the sense amplifier circuit 104, and the read buffer 106 according to the type of instruction.
The memory array 102 is coupled to the logic circuit 100. The memory array 102 may be non-volatile, such as a NOR gate flash (NOR gate flash) memory array, an NAD gate flash (NAND gate flash) memory array, or the like. The memory array 102 includes a plurality of memory cells (memory cells) arranged in a two-dimensional (2D) or three-dimensional (3D) manner.
The sense amplifier circuit 104 is coupled to the logic circuit 100 and the memory array 102. The sense amplifier circuitry 104 may be used to sense data stored within the memory array 102 and read data out of the memory array 102. After the data is read out by the sense amplifier circuit 104, the data is buffered in the read buffer 106.
The read buffer 106 is coupled to the logic circuit 100 and the sense amplifier circuit 104. The read buffer 106 buffers the data read by the sense amplifier circuit 104 and outputs the data to the controller 90.
Referring to fig. 2, fig. 2 is a flow chart illustrating an operation method of a memory device according to an embodiment of the invention. The operation method of the memory device 10 includes steps S201 to S209, which can be used to operate the memory device 10.
In step S201, a read command (read command) and an initial address are received. The read command and the initial address are issued by the controller 90 and transmitted to the memory device 10 through the signal line SIO.
In step S203, a read operation is performed in response to the read command. Specifically, step S203 may include steps S2031 to S2035.
In step S2031, a target data is found according to the initial address (start address). Generally, the initial address is a memory address (memory address) representing a location within the memory array 102 where the first bit of the data sequence storing the target data is located. When the logic circuit 100 receives the read command and the initial address from the controller 90, the initial address is buffered into an address register (not shown). Then, the logic circuit 100 finds the memory cell of the target data in the memory array 102 according to the initial address.
In step S2033, the target data is read out and buffered. Specifically, when the storage location of the target data is found, the logic circuit 100 instructs the sense amplifier circuit 104 to read out the target data. The target data read by the sense amplifier circuit 104 is buffered in the read buffer 106.
In step S2035, the target data is output. Specifically, after the target data is buffered in the read buffer 106, the read buffer 106 sequentially outputs the target data to the controller 90 through the signal line SIO.
For example, assume that the target data is a piece of data having a length of 32 bits (bit); when the sense amplifier circuit 104 reads out target data from the memory array 102, the number of bits read out per frequency cycle is 8 bits; the read buffer 106 is 32 bits in length; the signal line SIO may transmit 8 bits per clock cycle. In this example, the sense amplifier circuit 104 reads out 8 bits of the target data (starting from the start address) from the memory array 102 every clock cycle and buffers the 8 bits to the read buffer 106. The sense amplifier circuit 104 takes four clock cycles to read out all of the target data. After a portion of the target data (e.g., 8 bits) is buffered in the read buffer 106, the read buffer 106 outputs 8 bits of the target data to the controller 90 via the signal line SIO every clock cycle. The read buffer 106 takes four clock cycles to output the target data completely to the controller 90. In other words, step S2033 and step S2035 are repeated for a plurality of times until the target data is completely output to the controller 90 (i.e., the read operation is completed).
In step S205, it is determined whether an interrupt event occurs. The "interrupt event" refers to an event that causes the read operation (step S203) to be forcibly interrupted before completion. For example, before the read operation is completed, the memory device 10 receives an instruction from the controller 90 having a higher priority than the read instruction (e.g., a write instruction). The interrupt event occurs, for example, during execution of step S2033 or during execution of step S2035. When an interrupt event occurs, executing step S207; when no interrupt event occurs, the process is terminated (i.e., the read operation is not interrupted and is successfully completed).
In step S207, a buffer content of a read buffer is retained, and a read status is recorded. The "cache contents" refer to data (e.g., part or all of target data) cached in the read buffer 106. The read status may be recorded by the logic circuit 100, and may be used to record the execution status of the read operation when the interrupted event occurs. The read status includes, for example, a point in time when an interrupt event occurs, a number of bits that the target data has been read out (by the sense amplifier circuit 104) and buffered (to the read buffer 106), or a number of bits that the target data has been output from the read buffer 106 to the controller 90. However, the cache contents of the read buffer 106 are retained (i.e. the cache contents will not be cleared) regardless of the time point when the interrupt event occurs (e.g. during the execution of step S2033 or during the execution of step S2035).
In step S209, when a continue read command is received, the target data is read according to the read status and the buffer contents of the read buffer. The details of step S209 may include two embodiments, and the details will be described below respectively.
In the first embodiment of step S209, it is assumed that when the interrupt event occurs, part of the target data has been read out by the sense amplifier circuit 104 and buffered in the read buffer 106. After step S207 is executed, the content of the read buffer 106 (i.e., the portion of the target data that has been buffered and has not been output) is retained, and when the logic circuit 100 receives a read continuation command from the controller 90, the logic circuit 100 can instruct the sense amplifier circuit 104 to continue reading the rest of the target data from the memory array according to the read status. For example, assume that when an interrupt event occurs, the sense amplifier circuit 104 has read 16 bits of the target data (32 bits in total) and buffered in the read buffer 106. After step S207 is executed, the read buffer 106 retains a portion of the target data (e.g., 8 bits) that is buffered and not output, and the logic circuit 100 records the read status. In step S209, the logic circuit 100 instructs the sense amplifier circuit 104 to read out the remaining 16 bits of the target data according to the read status. When the rest of the target data is read, the reading can be started from the unread target data in the memory array, or the reading can be continued by selecting a start bit from the read target data.
In the second embodiment of step S209, it is assumed that all the target data has been read out by the sense amplifier circuit 104 and buffered in the read buffer 106 when the interrupt event occurs. The read buffer 106 has not yet begun transferring the target data to the controller 90, or the read buffer 106 may have output a portion of the target data to the controller 90. When the logic circuit 100 receives a continue read command from the controller 90, the logic circuit 100 may instruct the read buffer 106 to output the target data or the remaining portion of the target data to the controller 90 according to the read status. For example, assume that the read buffer 106 has output 16 bits of the target data (32 bits total) to the controller 90 when the interrupt event occurs. In step S207, the read buffer 106 retains a portion (16 bits) of the target data still buffered in the read buffer, and records the read status. In step S209, the logic circuit 100 instructs the read buffer 106 to transmit the remaining target data to the controller 90 according to the read status. When the rest of the target data is output, the data can be output from the target data which is not output, or the data can be continuously transmitted by selecting a start bit from the target data which is output.
The timing diagram of the second embodiment can be as shown in fig. 3. As shown in FIG. 3, after the memory device 10 receives the read command C _ read and the initial address A, it takes a delay time L to buffer a portion of the target data into the read buffer 106. Then, the data output D _ out1 is the read buffer 106 transferring the target data to the controller 90 (while the sense amplifier circuit 104 may still continue to read the target data that is not being read out). When the interrupt event E occurs, all of the target data has been read by the sense amplifier circuit 104, but a portion of the target data has not yet been output to the controller 90 by the read buffer 106. After the interrupt event E ends, the memory device 10 receives a continuous read command C _ readcon from the controller 90. Since it is not necessary to wait for the sense amplifier circuit 104 to read the target data out of the memory array 102, no delay (or very short delay) occurs in continuing the read. The read buffer 106 transmits the remaining target data to the controller 90 at the data output D _ out 2.
In summary, when an interrupt event occurs during a read operation, the memory device 10 can respond to the continue read command by keeping the buffer contents and recording the read status of the buffer register 106, and continue to read the target data according to the buffer contents and the read status. That is, the memory device 10 may continue to complete the read operation interrupted by the interrupt event in response to the continue read instruction without restarting a new read operation in order to read the same target data. According to the memory device and the operation method thereof disclosed by the embodiment of the invention, the time for continuously reading the target data after the reading operation for reading the target data is interrupted can be reduced, and the overall efficiency of the memory device is further improved.
In summary, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto. Various modifications and alterations can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention is defined by the protection scope of the preceding claims.
Claims (6)
1. A memory device, comprising:
a memory array;
a logic circuit, for responding to a read command and an initial address, executing a read operation, wherein the logic circuit finds a target data in the memory array according to the initial address during the read operation;
a sense amplifier circuit for reading the target data from the memory array during the read operation; and
a read buffer for buffering and outputting the target data during the read operation,
when an interrupt event occurs in the reading operation period, the reading buffer reserves the buffer content of the reading buffer, and the logic circuit records a reading state;
when receiving a continuous reading instruction, the logic circuit continuously reads the target data according to the reading state and the cache content;
when the interrupt event occurs and part of the target data is read out from the memory array by the sense amplifier circuit and cached to the read buffer, the logic circuit responds to the continuous read instruction and instructs the sense amplifier circuit to read out the rest part of the target data from the memory array according to the read state and the cache content.
2. The memory device of claim 1, wherein the logic circuit, in response to the continue read command, instructs the read buffer to output the target data according to the read status and the cache contents when the interrupt event occurs and all of the target data has been read by the sense amp circuit and cached in the read buffer.
3. The memory device of claim 1, wherein when the interrupt event occurs, all of the target data has been read out by the sense amp circuit and buffered in the read buffer, and a portion of the target data has been output, the logic circuit being responsive to the continue read command to instruct the read buffer to output the remaining portion of the target data based on the read status and the buffer contents.
4. A method of operation of a memory device, comprising:
receiving a reading instruction and an initial address; and
in response to the read command, performing a read operation, the read operation comprising:
finding out target data according to the initial address;
reading the target data and caching the target data to a read buffer; and
the target data is outputted, and the target data is outputted,
when an interrupt event occurs in the reading operation period, reserving a buffer content of the reading buffer and recording a reading state;
when receiving a continuous reading instruction, continuously reading the target data according to the reading state and the cache content;
when the interrupt event occurs and part of the target data is read out and cached to the read buffer, responding to the continuous read instruction, and reading out the rest part of the target data according to the read state and the cache content.
5. The operating method as claimed in claim 4, wherein when the interrupt event occurs and all of the target data has been read and buffered in the read buffer, the target data is output according to the read status and the buffer contents in response to the continue read command.
6. The operating method as claimed in claim 4, wherein when the interrupt event occurs, all of the target data has been read and buffered in the read buffer, and part of the target data has been output, the remaining part of the target data is output according to the read status and the buffer contents in response to the continue read command.
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