SG11201408606TA - Process for transferring a layer - Google Patents

Process for transferring a layer

Info

Publication number
SG11201408606TA
SG11201408606TA SG11201408606TA SG11201408606TA SG11201408606TA SG 11201408606T A SG11201408606T A SG 11201408606TA SG 11201408606T A SG11201408606T A SG 11201408606TA SG 11201408606T A SG11201408606T A SG 11201408606TA SG 11201408606T A SG11201408606T A SG 11201408606TA
Authority
SG
Singapore
Prior art keywords
international
donor substrate
rule
applicant
exposure time
Prior art date
Application number
SG11201408606TA
Inventor
Michel Bruel
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG11201408606TA publication Critical patent/SG11201408606TA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H10K50/11—OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers
    • H10K50/12—OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers comprising dopants

Abstract

(12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 3 January 2014 (03.01.2014) WIPOIPCT (10) International Publication Number WO 2014/001869 A1 (51) International Patent Classification: H01L 21/762 (2006.01) (21) International Application Number: (22) International Filing Date: (25) Filing Language: (26) Publication Language: PCT/IB2013/001252 14 June 2013 (14.06.2013) English English (30) Priority Data: 1201802 26 June 2012 (26.06.2012) FR (71) Applicant: SOITEC [FR/FR]; Chemin des Franques, Pare Teehnologique des Fontaines, F-38190 Bernin (FR). (72) Inventor: BRUEL, Michel; VEUREY VOROIZE (FR). Presvert n°9, F-38113 (81) Designated States (unless otherwise indicated, for every kind of national protection available)'. AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IS, JP, KE, KG, KN, KP, KR, KZ, LA, LC, LK, LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available)'. ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Declarations under Rule 4.17: — as to applicant's entitlement to apply for and be granted a patent (Rule 4.17(H)) — as to the applicant's entitlement to claim the priority of the earlier application (Rule 4.17(iii)) — of inventorship (Rule 4.17(iv)) Published: — with international search report (Art. 21(3)) (54) Title: PROCESS FOR TRANSFERRING A LAYER 5-M 1-N 20 6 6-v J* - ' > ' > i k E ' > ' 50 (57) Abstract: This transfer process comprises the following steps: (a) providing a donor substrate (2) and a support sub - strate (3); (b) forming a embrittlement region (4) in the donor substrate (2); (c) forming what is called a bonding layer (5) between the first part (1) of the donor substrate (2) and the support substrate (3); and (d) assembling the donor substrate (2) to the support substrate (3), and noteworthy is in that comprises it the following step: (e) exposing, in suc­ cession, portions (40) of the embrittlement region (4) to electromagnetic irradiations (6) for an exposure time at a given power density, the exposure time being chosen de­ pending on the thickness (E) of the bonding layer so that the support substrate (3) is thermally decoupled from the first part (1) of the donor substrate (2), the exposure time being chosen depending on the power density in order to activate kinetics that weaken the embrittlement region (4). 0\ 00 i-H o o Fig 1 o CJ O £
SG11201408606TA 2012-06-26 2013-06-14 Process for transferring a layer SG11201408606TA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1201802A FR2992464B1 (en) 2012-06-26 2012-06-26 METHOD FOR TRANSFERRING A LAYER
PCT/IB2013/001252 WO2014001869A1 (en) 2012-06-26 2013-06-14 Process for transferring a layer

Publications (1)

Publication Number Publication Date
SG11201408606TA true SG11201408606TA (en) 2015-01-29

Family

ID=48782549

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201408606TA SG11201408606TA (en) 2012-06-26 2013-06-14 Process for transferring a layer

Country Status (8)

Country Link
US (1) US9343351B2 (en)
EP (1) EP2865004B1 (en)
JP (1) JP6138931B2 (en)
KR (1) KR102007315B1 (en)
CN (1) CN104584203B (en)
FR (1) FR2992464B1 (en)
SG (1) SG11201408606TA (en)
WO (1) WO2014001869A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3007892B1 (en) * 2013-06-27 2015-07-31 Commissariat Energie Atomique METHOD FOR TRANSFERRING A THIN LAYER WITH THERMAL ENERGY SUPPLY TO A FRAGILIZED AREA VIA AN INDUCTIVE LAYER
US9966466B2 (en) * 2016-08-08 2018-05-08 Globalfoundries Inc. Semiconductor-on-insulator wafer, semiconductor structure including a transistor, and methods for the formation and operation thereof
CN108365083B (en) * 2018-02-07 2022-03-08 济南晶正电子科技有限公司 Method for manufacturing composite piezoelectric substrate for surface acoustic wave device

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1758169A3 (en) * 1996-08-27 2007-05-23 Seiko Epson Corporation Exfoliating method, transferring method of thin film device, and thin film device, thin film integrated circuit device, and liquid crystal display device produced by the same
US6291314B1 (en) * 1998-06-23 2001-09-18 Silicon Genesis Corporation Controlled cleavage process and device for patterned films using a release layer
TW452866B (en) * 2000-02-25 2001-09-01 Lee Tien Hsi Manufacturing method of thin film on a substrate
FR2817394B1 (en) * 2000-11-27 2003-10-31 Soitec Silicon On Insulator METHOD FOR MANUFACTURING A SUBSTRATE, IN PARTICULAR FOR OPTICS, ELECTRONICS OR OPTOELECTRONICS AND SUBSTRATE OBTAINED THEREBY
FR2855909B1 (en) * 2003-06-06 2005-08-26 Soitec Silicon On Insulator PROCESS FOR THE CONCURRENT PRODUCTION OF AT LEAST ONE PAIR OF STRUCTURES COMPRISING AT LEAST ONE USEFUL LAYER REPORTED ON A SUBSTRATE
US7052978B2 (en) * 2003-08-28 2006-05-30 Intel Corporation Arrangements incorporating laser-induced cleaving
FR2860249B1 (en) * 2003-09-30 2005-12-09 Michel Bruel METHOD FOR MANUFACTURING PLATE-LIKE STRUCTURE, ESPECIALLY SILICON, PROCESS APPLICATION, AND PLATE-LIKE STRUCTURE, PARTICULARLY SILICON
US20060240275A1 (en) * 2005-04-25 2006-10-26 Gadkaree Kishor P Flexible display substrates
DE102006007293B4 (en) * 2006-01-31 2023-04-06 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Method for producing a quasi-substrate wafer and a semiconductor body produced using such a quasi-substrate wafer
JP5284576B2 (en) * 2006-11-10 2013-09-11 信越化学工業株式会社 Manufacturing method of semiconductor substrate
JP2008153411A (en) * 2006-12-18 2008-07-03 Shin Etsu Chem Co Ltd Manufacturing method of soi substrate
EP1986229A1 (en) * 2007-04-27 2008-10-29 S.O.I.T.E.C. Silicon on Insulator Technologies Method for manufacturing compound material wafer and corresponding compound material wafer
US20090179160A1 (en) * 2008-01-16 2009-07-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor substrate manufacturing apparatus
KR20100008123A (en) * 2008-07-15 2010-01-25 고려대학교 산학협력단 Vertical light emitting devices with the support composed of double heat-sinking layer
JP5496608B2 (en) * 2008-11-12 2014-05-21 信越化学工業株式会社 Method for manufacturing SOI substrate
JP5643509B2 (en) * 2009-12-28 2014-12-17 信越化学工業株式会社 SOS substrate manufacturing method with reduced stress
CN101866874B (en) * 2010-06-01 2013-05-22 中国科学院上海微系统与信息技术研究所 Method for preparing silicon germanium on insulator (SGOI) by layer transfer technology

Also Published As

Publication number Publication date
EP2865004B1 (en) 2020-07-29
JP2015525964A (en) 2015-09-07
EP2865004A1 (en) 2015-04-29
WO2014001869A1 (en) 2014-01-03
KR20150023514A (en) 2015-03-05
CN104584203B (en) 2018-03-20
CN104584203A (en) 2015-04-29
US20150187638A1 (en) 2015-07-02
FR2992464A1 (en) 2013-12-27
JP6138931B2 (en) 2017-05-31
KR102007315B1 (en) 2019-08-06
US9343351B2 (en) 2016-05-17
FR2992464B1 (en) 2015-04-03

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