SG111048A1 - Structures and methods to minimize plasma charging damage in silicon on insulator devices - Google Patents

Structures and methods to minimize plasma charging damage in silicon on insulator devices

Info

Publication number
SG111048A1
SG111048A1 SG200201205A SG200201205A SG111048A1 SG 111048 A1 SG111048 A1 SG 111048A1 SG 200201205 A SG200201205 A SG 200201205A SG 200201205 A SG200201205 A SG 200201205A SG 111048 A1 SG111048 A1 SG 111048A1
Authority
SG
Singapore
Prior art keywords
silicon
structures
methods
charging damage
plasma charging
Prior art date
Application number
SG200201205A
Other languages
English (en)
Inventor
Khare Mukesh
D Agnello Paul
I Chou Anthony
Blackwell Hook Terence
C Mocuta Anda
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of SG111048A1 publication Critical patent/SG111048A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)
SG200201205A 2001-03-30 2002-02-28 Structures and methods to minimize plasma charging damage in silicon on insulator devices SG111048A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/822,453 US20020142526A1 (en) 2001-03-30 2001-03-30 Structures and methods to minimize plasma charging damage in silicon on insulator devices

Publications (1)

Publication Number Publication Date
SG111048A1 true SG111048A1 (en) 2005-05-30

Family

ID=25236073

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200201205A SG111048A1 (en) 2001-03-30 2002-02-28 Structures and methods to minimize plasma charging damage in silicon on insulator devices

Country Status (4)

Country Link
US (1) US20020142526A1 (ja)
JP (1) JP3897339B2 (ja)
SG (1) SG111048A1 (ja)
TW (1) TW544851B (ja)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10324434B4 (de) * 2003-05-28 2005-08-25 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Einstellen der Ätzselektivität durch Anpassen von Aspektverhältnissen bei einem Mehrebenen-Ätzprozess
US7470959B2 (en) * 2003-11-04 2008-12-30 International Business Machines Corporation Integrated circuit structures for preventing charging damage
US7067886B2 (en) * 2003-11-04 2006-06-27 International Business Machines Corporation Method of assessing potential for charging damage in SOI designs and structures for eliminating potential for damage
US20050242439A1 (en) * 2004-04-28 2005-11-03 International Business Machines Corporation Method and structure for connecting ground/power networks to prevent charge damage in silicon on insulator
US7445966B2 (en) * 2005-06-24 2008-11-04 International Business Machines Corporation Method and structure for charge dissipation during fabrication of integrated circuits and isolation thereof
KR20120017258A (ko) * 2010-08-18 2012-02-28 삼성모바일디스플레이주식회사 박막 대전 센서
JP5996893B2 (ja) * 2012-03-13 2016-09-21 ラピスセミコンダクタ株式会社 半導体装置の製造方法
US9996654B2 (en) * 2014-12-22 2018-06-12 Wallace W Lin Transistor plasma charging evaluator
US9852248B2 (en) * 2014-12-22 2017-12-26 Wallace W Lin Transistor plasma charging eliminator

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5234535A (en) * 1992-12-10 1993-08-10 International Business Machines Corporation Method of producing a thin silicon-on-insulator layer
JPH1154759A (ja) * 1997-08-05 1999-02-26 Toshiba Corp 半導体装置およびその製造方法
US6133610A (en) * 1998-01-20 2000-10-17 International Business Machines Corporation Silicon-on-insulator chip having an isolation barrier for reliability and process of manufacture
WO2001026160A1 (fr) * 1999-10-01 2001-04-12 France Telecom Dispositif semi-conducteur combinant les avantages des architectures massives et soi, et procede de fabrication
US6303414B1 (en) * 2000-07-12 2001-10-16 Chartered Semiconductor Manufacturing Ltd. Method of forming PID protection diode for SOI wafer
US6357861B1 (en) * 1998-06-22 2002-03-19 Sharp Kabushiki Kaisha Image forming device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5234535A (en) * 1992-12-10 1993-08-10 International Business Machines Corporation Method of producing a thin silicon-on-insulator layer
JPH1154759A (ja) * 1997-08-05 1999-02-26 Toshiba Corp 半導体装置およびその製造方法
US6133610A (en) * 1998-01-20 2000-10-17 International Business Machines Corporation Silicon-on-insulator chip having an isolation barrier for reliability and process of manufacture
US6357861B1 (en) * 1998-06-22 2002-03-19 Sharp Kabushiki Kaisha Image forming device
WO2001026160A1 (fr) * 1999-10-01 2001-04-12 France Telecom Dispositif semi-conducteur combinant les avantages des architectures massives et soi, et procede de fabrication
US6303414B1 (en) * 2000-07-12 2001-10-16 Chartered Semiconductor Manufacturing Ltd. Method of forming PID protection diode for SOI wafer

Also Published As

Publication number Publication date
TW544851B (en) 2003-08-01
JP3897339B2 (ja) 2007-03-22
JP2002324903A (ja) 2002-11-08
US20020142526A1 (en) 2002-10-03

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