SG102552A1 - Device contact structure and method for fabricating same - Google Patents
Device contact structure and method for fabricating sameInfo
- Publication number
- SG102552A1 SG102552A1 SG9905103A SG1999005103A SG102552A1 SG 102552 A1 SG102552 A1 SG 102552A1 SG 9905103 A SG9905103 A SG 9905103A SG 1999005103 A SG1999005103 A SG 1999005103A SG 102552 A1 SG102552 A1 SG 102552A1
- Authority
- SG
- Singapore
- Prior art keywords
- contact structure
- device contact
- fabricating same
- fabricating
- same
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/175,304 US6090673A (en) | 1998-10-20 | 1998-10-20 | Device contact structure and method for fabricating same |
Publications (1)
Publication Number | Publication Date |
---|---|
SG102552A1 true SG102552A1 (en) | 2004-03-26 |
Family
ID=22639770
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG9905103A SG102552A1 (en) | 1998-10-20 | 1999-10-13 | Device contact structure and method for fabricating same |
Country Status (4)
Country | Link |
---|---|
US (1) | US6090673A (ko) |
KR (1) | KR100311842B1 (ko) |
MY (1) | MY121099A (ko) |
SG (1) | SG102552A1 (ko) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6380063B1 (en) * | 2000-03-01 | 2002-04-30 | International Business Machines Corporation | Raised wall isolation device with spacer isolated contacts and the method of so forming |
KR100573276B1 (ko) * | 2003-12-31 | 2006-04-24 | 동부아남반도체 주식회사 | 에스램 소자 및 그 제조방법 |
US20070218685A1 (en) * | 2006-03-17 | 2007-09-20 | Swaminathan Sivakumar | Method of forming trench contacts for MOS transistors |
US7737715B2 (en) * | 2006-07-31 | 2010-06-15 | Marvell Israel (M.I.S.L) Ltd. | Compensation for voltage drop in automatic test equipment |
CN100481354C (zh) * | 2006-08-30 | 2009-04-22 | 中国科学院微电子研究所 | 一种制备低栅扩展电容绝缘体上硅体接触器件的方法 |
US20100308380A1 (en) * | 2009-06-05 | 2010-12-09 | International Business Machines Corporation | Dual damascene processing for gate conductor and active area to first metal level interconnect structures |
CN104752334B (zh) * | 2013-12-31 | 2017-12-01 | 中芯国际集成电路制造(上海)有限公司 | 接触插塞的形成方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5621232A (en) * | 1993-10-05 | 1997-04-15 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device including a local interconnection between an interconnection layer and an adjoining impurity region |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5211199B1 (ko) * | 1970-05-27 | 1977-03-29 | ||
US4034243A (en) * | 1975-12-19 | 1977-07-05 | International Business Machines Corporation | Logic array structure for depletion mode-FET load circuit technologies |
JPS55132055A (en) * | 1979-03-30 | 1980-10-14 | Nec Corp | Mos integrated circuit |
US4305200A (en) * | 1979-11-06 | 1981-12-15 | Hewlett-Packard Company | Method of forming self-registering source, drain, and gate contacts for FET transistor structures |
US5121174A (en) * | 1987-10-23 | 1992-06-09 | Vitesse Semiconductor Corporation | Gate-to-ohmic metal contact scheme for III-V devices |
US5166771A (en) * | 1990-01-12 | 1992-11-24 | Paradigm Technology, Inc. | Self-aligning contact and interconnect structure |
US5206532A (en) * | 1990-10-03 | 1993-04-27 | Micron Technology, Inc. | Buried contact between polysilicon gate and diffusion area |
EP0482556A1 (en) * | 1990-10-22 | 1992-04-29 | Nec Corporation | Polysilicon resistance element and semiconductor device using the same |
GB9219268D0 (en) * | 1992-09-11 | 1992-10-28 | Inmos Ltd | Semiconductor device incorporating a contact and manufacture thereof |
JPH06140519A (ja) * | 1992-10-22 | 1994-05-20 | Toshiba Corp | 半導体装置及びその製造方法 |
TW247368B (en) * | 1993-09-29 | 1995-05-11 | Seiko Epuson Co | Current regulating semiconductor integrate circuit device and fabrication method of the same |
US5541427A (en) * | 1993-12-03 | 1996-07-30 | International Business Machines Corporation | SRAM cell with capacitor |
KR0135147B1 (ko) * | 1994-07-21 | 1998-04-22 | 문정환 | 트랜지스터 제조방법 |
US5631484A (en) * | 1995-12-26 | 1997-05-20 | Motorola, Inc. | Method of manufacturing a semiconductor device and termination structure |
US5811350A (en) * | 1996-08-22 | 1998-09-22 | Micron Technology, Inc. | Method of forming contact openings and an electronic component formed from the same and other methods |
TW346652B (en) * | 1996-11-09 | 1998-12-01 | Winbond Electronics Corp | Semiconductor production process |
US5851890A (en) * | 1997-08-28 | 1998-12-22 | Lsi Logic Corporation | Process for forming integrated circuit structure with metal silicide contacts using notched sidewall spacer on gate electrode |
US5953614A (en) * | 1997-10-09 | 1999-09-14 | Lsi Logic Corporation | Process for forming self-aligned metal silicide contacts for MOS structure using single silicide-forming step |
US5895269A (en) * | 1997-12-18 | 1999-04-20 | Advanced Micro Devices, Inc. | Methods for preventing deleterious punch-through during local interconnect formation |
-
1998
- 1998-10-20 US US09/175,304 patent/US6090673A/en not_active Expired - Fee Related
-
1999
- 1999-09-09 KR KR1019990038248A patent/KR100311842B1/ko not_active IP Right Cessation
- 1999-09-29 MY MYPI99004205A patent/MY121099A/en unknown
- 1999-10-13 SG SG9905103A patent/SG102552A1/en unknown
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5621232A (en) * | 1993-10-05 | 1997-04-15 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device including a local interconnection between an interconnection layer and an adjoining impurity region |
Also Published As
Publication number | Publication date |
---|---|
KR20000028642A (ko) | 2000-05-25 |
KR100311842B1 (ko) | 2001-10-18 |
US6090673A (en) | 2000-07-18 |
MY121099A (en) | 2005-12-30 |
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