SG10201805814UA - Image processing apparatus and method of controlling the same - Google Patents

Image processing apparatus and method of controlling the same

Info

Publication number
SG10201805814UA
SG10201805814UA SG10201805814UA SG10201805814UA SG10201805814UA SG 10201805814U A SG10201805814U A SG 10201805814UA SG 10201805814U A SG10201805814U A SG 10201805814UA SG 10201805814U A SG10201805814U A SG 10201805814UA SG 10201805814U A SG10201805814U A SG 10201805814UA
Authority
SG
Singapore
Prior art keywords
processing apparatus
image processing
zone
controlling
pixels
Prior art date
Application number
SG10201805814UA
Other languages
English (en)
Inventor
Kim Seung-Hoon
Baek Kwang-sun
Lee Jung-Won
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of SG10201805814UA publication Critical patent/SG10201805814UA/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • G09G5/397—Arrangements specially adapted for transferring the contents of two or more bit-mapped memories to the screen simultaneously, e.g. for mixing or overlay
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/222—Studio circuitry; Studio devices; Studio equipment
    • H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
    • H04N5/265—Mixing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/79—Processing of colour television signals in connection with recording
    • H04N9/87—Regeneration of colour television signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/10—Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/18—Use of a frame buffer in a display terminal, inclusive of the display panel

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Computer Graphics (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Processing (AREA)
  • Ultra Sonic Daignosis Equipment (AREA)
SG10201805814UA 2017-07-05 2018-07-05 Image processing apparatus and method of controlling the same SG10201805814UA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020170085560A KR102442625B1 (ko) 2017-07-05 2017-07-05 영상 처리 장치 및 상기 영상 처리 장치의 제어 방법

Publications (1)

Publication Number Publication Date
SG10201805814UA true SG10201805814UA (en) 2019-02-27

Family

ID=64666434

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10201805814UA SG10201805814UA (en) 2017-07-05 2018-07-05 Image processing apparatus and method of controlling the same

Country Status (5)

Country Link
US (1) US10896661B2 (zh)
KR (1) KR102442625B1 (zh)
CN (1) CN109214977B (zh)
DE (1) DE102018116270A1 (zh)
SG (1) SG10201805814UA (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7427381B2 (ja) * 2019-07-22 2024-02-05 キヤノン株式会社 情報処理装置、システム、情報処理方法及びプログラム
CN115497432A (zh) * 2022-09-23 2022-12-20 珠海格力电器股份有限公司 数据处理方法、装置、电子设备、显示设备及存储介质

Family Cites Families (19)

* Cited by examiner, † Cited by third party
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US4528636A (en) * 1981-10-19 1985-07-09 Intermark Industries, Inc. Display memory with write inhibit signal for transparent foreground pixel codes
US5959637A (en) 1995-06-23 1999-09-28 Cirrus Logic, Inc. Method and apparatus for executing a raster operation in a graphics controller circuit
US6084600A (en) 1996-03-15 2000-07-04 Micron Technology, Inc. Method and apparatus for high-speed block transfer of compressed and word-aligned bitmaps
US6573905B1 (en) 1999-11-09 2003-06-03 Broadcom Corporation Video and graphics system with parallel processing of graphics windows
JP2001195230A (ja) * 2000-01-14 2001-07-19 Mitsubishi Electric Corp 描画処理システム、及び描画演算を行う半導体集積回路
JP3889392B2 (ja) 2003-11-18 2007-03-07 株式会社スクウェア・エニックス 画像描画装置及び方法、プログラム並びに記録媒体
DE602004010777T2 (de) 2004-02-18 2008-12-04 Harman Becker Automotive Systems Gmbh Alphamischung auf Basis einer Nachschlagtabelle
JP4219887B2 (ja) * 2004-12-28 2009-02-04 富士通マイクロエレクトロニクス株式会社 画像処理装置及び画像処理方法
KR100706442B1 (ko) 2005-03-08 2007-04-10 주식회사 팬택앤큐리텔 투명색 처리속도를 향상시키기 위한 파일처리 시스템 및 투명색 처리속도를 향상시키기 위한 화면처리 시스템
KR101169994B1 (ko) * 2005-04-07 2012-08-01 삼성전자주식회사 알파 평면을 이용한 영상 데이터 처리 장치 및 방법
US7737985B2 (en) * 2006-11-09 2010-06-15 Qualcomm Incorporated Pixel cache for 3D graphics circuitry
US7973803B1 (en) * 2007-05-17 2011-07-05 Adobe Systems Incorporated Simultaneous occluding transparency graphics processing
CN102215428B (zh) 2011-06-23 2012-12-26 深圳市茁壮网络股份有限公司 一种图片的处理方法及机顶盒
JP5851170B2 (ja) * 2011-09-22 2016-02-03 株式会社ソニー・コンピュータエンタテインメント 画像処理装置および画像処理方法
JP6338357B2 (ja) 2013-11-18 2018-06-06 キヤノン株式会社 画像処理装置、画像処理方法、及びプログラム
KR102164543B1 (ko) 2014-10-16 2020-10-12 삼성전자 주식회사 디스플레이 장치 및 디스플레이 방법
GR20140100528A (el) 2014-10-20 2016-06-01 Arm Limited Ενας βασισμενος σε πλακιδια επεξεργαστης γραφικων και μια μεθοδος επεξεργασιας γραφικων σε ενα βασισμενο σε πλακιδια επεξεργαστη
US20170004808A1 (en) * 2015-07-02 2017-01-05 Nvidia Corporation Method and system for capturing a frame buffer of a virtual machine in a gpu pass-through environment
WO2017107183A1 (en) 2015-12-25 2017-06-29 Intel Corporation Alpha blending and display update bandwidth saving during render and display operations

Also Published As

Publication number Publication date
US10896661B2 (en) 2021-01-19
CN109214977A (zh) 2019-01-15
KR20190005035A (ko) 2019-01-15
CN109214977B (zh) 2023-11-14
US20190012990A1 (en) 2019-01-10
KR102442625B1 (ko) 2022-09-13
DE102018116270A1 (de) 2019-01-10

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