SG10201408265SA - Integrated circuit packaging system with conductive ink and method of manufacture thereof - Google Patents

Integrated circuit packaging system with conductive ink and method of manufacture thereof

Info

Publication number
SG10201408265SA
SG10201408265SA SG10201408265SA SG10201408265SA SG10201408265SA SG 10201408265S A SG10201408265S A SG 10201408265SA SG 10201408265S A SG10201408265S A SG 10201408265SA SG 10201408265S A SG10201408265S A SG 10201408265SA SG 10201408265S A SG10201408265S A SG 10201408265SA
Authority
SG
Singapore
Prior art keywords
manufacture
integrated circuit
conductive ink
packaging system
circuit packaging
Prior art date
Application number
SG10201408265SA
Inventor
Ramirez Camacho Zigmund
Liao Chung Foh Bartholomew
Marie L Alvarez Sheila
Dao Nguyen Phu Cuong Kelvin
Original Assignee
Stats Chippac Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stats Chippac Ltd filed Critical Stats Chippac Ltd
Publication of SG10201408265SA publication Critical patent/SG10201408265SA/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867—Applying pastes or inks, e.g. screen printing
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4827—Materials
    • H01L23/4828—Conductive organic material or pastes, e.g. conductive adhesives, inks
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Materials Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Manufacturing Of Printed Wiring (AREA)
SG10201408265SA 2013-12-20 2014-12-11 Integrated circuit packaging system with conductive ink and method of manufacture thereof SG10201408265SA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/136,274 US20150179602A1 (en) 2013-12-20 2013-12-20 Integrated circuit packaging system with conductive ink and method of manufacture thereof

Publications (1)

Publication Number Publication Date
SG10201408265SA true SG10201408265SA (en) 2015-07-30

Family

ID=53400896

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10201408265SA SG10201408265SA (en) 2013-12-20 2014-12-11 Integrated circuit packaging system with conductive ink and method of manufacture thereof

Country Status (4)

Country Link
US (1) US20150179602A1 (en)
CN (1) CN104733333A (en)
SG (1) SG10201408265SA (en)
TW (1) TW201532230A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10541218B2 (en) 2016-11-29 2020-01-21 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution layer structure and fabrication method therefor
TWI677949B (en) 2018-11-21 2019-11-21 華邦電子股份有限公司 Semiconductor device
CN112582276A (en) * 2019-09-28 2021-03-30 台湾积体电路制造股份有限公司 Semiconductor structure and manufacturing method thereof

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007052396A1 (en) * 2005-10-31 2007-05-10 Sharp Kabushiki Kaisha Multilayer wiring board and method for manufacturing multilayer wiring board
US7674701B2 (en) * 2006-02-08 2010-03-09 Amkor Technology, Inc. Methods of forming metal layers using multi-layer lift-off patterns
US20090294958A1 (en) * 2008-05-30 2009-12-03 Broadcom Corporation Wafer level redistribution using circuit printing technology
US7952203B2 (en) * 2008-08-29 2011-05-31 Intel Corporation Methods of forming C4 round dimple metal stud bumps for fine pitch packaging applications and structures formed thereby
FR2946795B1 (en) * 2009-06-12 2011-07-22 3D Plus METHOD FOR POSITIONING CHIPS WHEN MANUFACTURING A RECONSTITUTED PLATE
US8283835B2 (en) * 2010-04-30 2012-10-09 Epcos Ag Guided bulk acoustic wave device having reduced height and method for manufacturing
JP2012114148A (en) * 2010-11-22 2012-06-14 Fujitsu Semiconductor Ltd Method of manufacturing semiconductor device
US9082870B2 (en) * 2013-03-13 2015-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of packaging semiconductor devices

Also Published As

Publication number Publication date
US20150179602A1 (en) 2015-06-25
CN104733333A (en) 2015-06-24
TW201532230A (en) 2015-08-16

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