SG10201408268YA - Integrated circuit packaging system with vialess substrate and method of manufacture thereof - Google Patents

Integrated circuit packaging system with vialess substrate and method of manufacture thereof

Info

Publication number
SG10201408268YA
SG10201408268YA SG10201408268YA SG10201408268YA SG10201408268YA SG 10201408268Y A SG10201408268Y A SG 10201408268YA SG 10201408268Y A SG10201408268Y A SG 10201408268YA SG 10201408268Y A SG10201408268Y A SG 10201408268YA SG 10201408268Y A SG10201408268Y A SG 10201408268YA
Authority
SG
Singapore
Prior art keywords
vialess
manufacture
substrate
integrated circuit
packaging system
Prior art date
Application number
SG10201408268YA
Inventor
Soo Kim Sung
Tai Do Byung
Trasporto Arnel
Original Assignee
Stats Chippac Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stats Chippac Ltd filed Critical Stats Chippac Ltd
Publication of SG10201408268YA publication Critical patent/SG10201408268YA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
SG10201408268YA 2013-12-20 2014-12-11 Integrated circuit packaging system with vialess substrate and method of manufacture thereof SG10201408268YA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/136,513 US20150179555A1 (en) 2013-12-20 2013-12-20 Integrated circuit packaging system with vialess substrate and method of manufacture thereof

Publications (1)

Publication Number Publication Date
SG10201408268YA true SG10201408268YA (en) 2015-07-30

Family

ID=53400868

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10201408268YA SG10201408268YA (en) 2013-12-20 2014-12-11 Integrated circuit packaging system with vialess substrate and method of manufacture thereof

Country Status (5)

Country Link
US (1) US20150179555A1 (en)
KR (1) KR20150073864A (en)
CN (1) CN104733334A (en)
SG (1) SG10201408268YA (en)
TW (1) TW201543583A (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9406531B1 (en) 2014-03-28 2016-08-02 STATS ChipPAC Pte. Ltd. Integrated circuit packaging system with photoimagable dielectric-defined trace and method of manufacture thereof
US9718678B2 (en) * 2014-09-25 2017-08-01 Infineon Technologies Ag Package arrangement, a package, and a method of manufacturing a package arrangement
US9809446B1 (en) * 2016-05-09 2017-11-07 Amkor Technology, Inc. Semiconductor package and manufacturing method thereof
US11393788B2 (en) * 2016-09-22 2022-07-19 Intel Corporation Integrated circuit package with glass spacer
CN109065459A (en) * 2018-07-27 2018-12-21 大连德豪光电科技有限公司 The production method of pad
CN113113319B (en) * 2021-03-23 2023-02-10 江西新菲新材料有限公司 Lead frame and manufacturing method thereof

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7157380B2 (en) * 2003-12-24 2007-01-02 Intel Corporation Damascene process for fabricating interconnect layers in an integrated circuit
JP5346578B2 (en) * 2005-03-31 2013-11-20 スタッツ・チップパック・リミテッド Semiconductor assembly and manufacturing method thereof
US7446712B2 (en) * 2005-12-21 2008-11-04 The Regents Of The University Of California Composite right/left-handed transmission line based compact resonant antenna for RF module integration
KR100714310B1 (en) * 2006-02-23 2007-05-02 삼성전자주식회사 Semiconductor packages including transformer or antenna
JP2008005471A (en) * 2006-05-23 2008-01-10 Matsushita Electric Ind Co Ltd Piezoelectric oscillator and its manufacturing method
US8017436B1 (en) * 2007-12-10 2011-09-13 Amkor Technology, Inc. Thin substrate fabrication method and structure
US9847268B2 (en) * 2008-11-21 2017-12-19 Advanpack Solutions Pte. Ltd. Semiconductor package and manufacturing method thereof
JP5568250B2 (en) * 2009-05-18 2014-08-06 公立大学法人大阪府立大学 How to fill copper
CN102130088B (en) * 2010-01-20 2013-01-16 矽品精密工业股份有限公司 Semiconductor packaging structure and making method thereof
TWI497668B (en) * 2011-07-27 2015-08-21 矽品精密工業股份有限公司 Semiconductor package and method of forming same
US8916422B2 (en) * 2013-03-15 2014-12-23 United Test And Assembly Center Ltd. Semiconductor packages and methods of packaging semiconductor devices

Also Published As

Publication number Publication date
CN104733334A (en) 2015-06-24
US20150179555A1 (en) 2015-06-25
KR20150073864A (en) 2015-07-01
TW201543583A (en) 2015-11-16

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