SE9901606L - Method and apparatus for reducing buffer delay - Google Patents

Method and apparatus for reducing buffer delay

Info

Publication number
SE9901606L
SE9901606L SE9901606A SE9901606A SE9901606L SE 9901606 L SE9901606 L SE 9901606L SE 9901606 A SE9901606 A SE 9901606A SE 9901606 A SE9901606 A SE 9901606A SE 9901606 L SE9901606 L SE 9901606L
Authority
SE
Sweden
Prior art keywords
frame buffer
read
pointer
write
pointers
Prior art date
Application number
SE9901606A
Other languages
Swedish (sv)
Other versions
SE9901606D0 (en
SE516746C2 (en
Inventor
Joachim Roos
Original Assignee
Net Insight Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Net Insight Ab filed Critical Net Insight Ab
Priority to SE9901606A priority Critical patent/SE516746C2/en
Publication of SE9901606D0 publication Critical patent/SE9901606D0/en
Priority to PCT/SE2000/000848 priority patent/WO2000067518A1/en
Priority to AU44473/00A priority patent/AU4447300A/en
Publication of SE9901606L publication Critical patent/SE9901606L/en
Publication of SE516746C2 publication Critical patent/SE516746C2/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13103—Memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13292—Time division multiplexing, TDM
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/1336—Synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13361—Synchronous systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13393—Time slot switching, T-stage, time slot interchanging, TSI

Abstract

The present invention relates to methods and an apparatus for switching data. According to the invention, storage means providing three or more frame buffers are used for temporarily storing frames of slots received via an input port of said apparatus. Read and write pointers are provided to designate which of said frame buffers that are used to be read/write accessed at each point in time. Control means are provided for controlling the operation of said pointer means, said control means being arranged to position said pointers so that the frame buffer currently designated by said write pointer is not the same as the one currently designated by said read pointer. Configuring means are provided for enabling, for slots that are to be transmitted from said output port and that are not to be time switched by said switch, reading of data for said slot from the frame buffer that is located one frame buffer ahead, in said round-robin fashion, of the frame buffer designated by said read pointer.
SE9901606A 1999-05-04 1999-05-04 Method and apparatus for reducing buffer delay SE516746C2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
SE9901606A SE516746C2 (en) 1999-05-04 1999-05-04 Method and apparatus for reducing buffer delay
PCT/SE2000/000848 WO2000067518A1 (en) 1999-05-04 2000-05-03 Method and apparatus for reducing buffer delay
AU44473/00A AU4447300A (en) 1999-05-04 2000-05-03 Method and apparatus for reducing buffer delay

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9901606A SE516746C2 (en) 1999-05-04 1999-05-04 Method and apparatus for reducing buffer delay

Publications (3)

Publication Number Publication Date
SE9901606D0 SE9901606D0 (en) 1999-05-04
SE9901606L true SE9901606L (en) 2000-11-05
SE516746C2 SE516746C2 (en) 2002-02-26

Family

ID=20415457

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9901606A SE516746C2 (en) 1999-05-04 1999-05-04 Method and apparatus for reducing buffer delay

Country Status (3)

Country Link
AU (1) AU4447300A (en)
SE (1) SE516746C2 (en)
WO (1) WO2000067518A1 (en)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4005272A (en) * 1974-08-14 1977-01-25 Arthur A. Collins, Inc. Time folded TST (time space time) switch
US4791629A (en) * 1986-06-02 1988-12-13 Ibm Corporation Communications switching system
US4809261A (en) * 1987-07-10 1989-02-28 Solid State Systems, Inc. Space and time switch for 22 PCM highways
US5128929A (en) * 1988-11-15 1992-07-07 Nec Corporation Time division switching system capable of broad band communications service
US5862136A (en) * 1995-07-07 1999-01-19 Northern Telecom Limited Telecommunications apparatus and method
US6141346A (en) * 1995-07-19 2000-10-31 Fujitsu Network Communications, Inc. Point-to-multipoint transmission using subqueues

Also Published As

Publication number Publication date
AU4447300A (en) 2000-11-17
SE9901606D0 (en) 1999-05-04
WO2000067518A1 (en) 2000-11-09
SE516746C2 (en) 2002-02-26

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