SE9803694L - Köhantering - Google Patents

Köhantering

Info

Publication number
SE9803694L
SE9803694L SE9803694A SE9803694A SE9803694L SE 9803694 L SE9803694 L SE 9803694L SE 9803694 A SE9803694 A SE 9803694A SE 9803694 A SE9803694 A SE 9803694A SE 9803694 L SE9803694 L SE 9803694L
Authority
SE
Sweden
Prior art keywords
memory
queue
buffer
cells
buffer memory
Prior art date
Application number
SE9803694A
Other languages
English (en)
Other versions
SE521609C2 (sv
SE9803694D0 (sv
Inventor
Per Andersson
Jonas Alowersson
Patrik Sundstroem
Bertil Roslund
Original Assignee
Switchcore Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Switchcore Ab filed Critical Switchcore Ab
Priority to SE9803694A priority Critical patent/SE521609C2/sv
Publication of SE9803694D0 publication Critical patent/SE9803694D0/sv
Priority to US09/428,285 priority patent/US6754742B1/en
Publication of SE9803694L publication Critical patent/SE9803694L/sv
Publication of SE521609C2 publication Critical patent/SE521609C2/sv

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/103—Packet switching elements characterised by the switching fabric construction using a shared central buffer; using a shared memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/104—Asynchronous transfer mode [ATM] switching fabrics
    • H04L49/105—ATM switching elements
    • H04L49/108—ATM switching elements using shared central buffer
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5681—Buffer or queue management

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
SE9803694A 1998-10-28 1998-10-28 Buffertminne, buffertkontrollenhet och en metod för att hantera köer i en ATM-växel SE521609C2 (sv)

Priority Applications (2)

Application Number Priority Date Filing Date Title
SE9803694A SE521609C2 (sv) 1998-10-28 1998-10-28 Buffertminne, buffertkontrollenhet och en metod för att hantera köer i en ATM-växel
US09/428,285 US6754742B1 (en) 1998-10-28 1999-10-27 Queue management system having one read and one write per cycle by using free queues

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9803694A SE521609C2 (sv) 1998-10-28 1998-10-28 Buffertminne, buffertkontrollenhet och en metod för att hantera köer i en ATM-växel

Publications (3)

Publication Number Publication Date
SE9803694D0 SE9803694D0 (sv) 1998-10-28
SE9803694L true SE9803694L (sv) 2000-04-29
SE521609C2 SE521609C2 (sv) 2003-11-18

Family

ID=20413114

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9803694A SE521609C2 (sv) 1998-10-28 1998-10-28 Buffertminne, buffertkontrollenhet och en metod för att hantera köer i en ATM-växel

Country Status (2)

Country Link
US (1) US6754742B1 (sv)
SE (1) SE521609C2 (sv)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10015683B4 (de) * 2000-03-29 2006-07-13 Infineon Technologies Ag Datenübertragungsspeicher
US7889750B1 (en) * 2004-04-28 2011-02-15 Extreme Networks, Inc. Method of extending default fixed number of processing cycles in pipelined packet processor architecture
US7555579B2 (en) * 2004-05-21 2009-06-30 Nortel Networks Limited Implementing FIFOs in shared memory using linked lists and interleaved linked lists
JP2006115315A (ja) * 2004-10-15 2006-04-27 Fujitsu Ltd データ転送方法及びデータ転送装置
WO2012169032A1 (ja) * 2011-06-09 2012-12-13 富士通株式会社 バッファ装置，バッファ制御装置，及びバッファ制御方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02117243A (ja) 1988-10-27 1990-05-01 Toshiba Corp パケット通信装置
EP0471051B1 (de) 1990-03-02 1994-10-19 Ascom Tech Ag Steuereinheit für den zentralspeicher eines atm-knotens
JPH05336153A (ja) * 1992-05-29 1993-12-17 Matsushita Electric Ind Co Ltd セル転送キュー構成方式およびセル転送キュー回路
US5390184A (en) * 1993-09-30 1995-02-14 Northern Telecom Limited Flexible scheduling mechanism for ATM switches
JP2922119B2 (ja) * 1994-09-01 1999-07-19 沖電気工業株式会社 帯域規制装置及びパケット通信装置
US5828903A (en) 1994-09-30 1998-10-27 Intel Corporation System for performing DMA transfer with a pipeline control switching such that the first storage area contains location of a buffer for subsequent transfer
US5790770A (en) * 1995-07-19 1998-08-04 Fujitsu Network Communications, Inc. Method and apparatus for reducing information loss in a communications network
JP3156752B2 (ja) * 1996-02-09 2001-04-16 日本電気株式会社 Ａｔｍスイッチ装置及びその制御方法
US6128303A (en) * 1996-05-09 2000-10-03 Maker Communications, Inc. Asynchronous transfer mode cell processing system with scoreboard scheduling
GB9618131D0 (en) 1996-08-30 1996-10-09 Sgs Thomson Microelectronics Improvements in or relating to an ATM switch
US6137807A (en) * 1997-12-05 2000-10-24 Whittaker Corporation Dual bank queue memory and queue control system

Also Published As

Publication number Publication date
SE521609C2 (sv) 2003-11-18
SE9803694D0 (sv) 1998-10-28
US6754742B1 (en) 2004-06-22

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Legal Events

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NUG Patent has lapsed