SE9700551L - Locked loop - Google Patents

Locked loop

Info

Publication number
SE9700551L
SE9700551L SE9700551A SE9700551A SE9700551L SE 9700551 L SE9700551 L SE 9700551L SE 9700551 A SE9700551 A SE 9700551A SE 9700551 A SE9700551 A SE 9700551A SE 9700551 L SE9700551 L SE 9700551L
Authority
SE
Sweden
Prior art keywords
signal
control signal
digital
output signal
error
Prior art date
Application number
SE9700551A
Other languages
Swedish (sv)
Other versions
SE9700551D0 (en
Inventor
Mats Wilhelmsson
Clarence Joern Niklas Fransson
Karl Anders Bjenne
Peter Lundh
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from SE9503702A external-priority patent/SE517602C2/en
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Priority to SE9700551A priority Critical patent/SE9700551L/en
Publication of SE9700551D0 publication Critical patent/SE9700551D0/en
Publication of SE9700551L publication Critical patent/SE9700551L/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

The circuit includes an output signal source (9) which provides an output signal in response to a control signal. The output signal has a frequency that is dependent on the control signal. A phase detector (2D) provides an error signal which represents the difference in phase between an input reference signal and the output signal. A first feedback path supplies the output signal to the phase detector. The PLL arrangement also includes a digital filter (6D) responsive to the error signal for providing a digital control signal which is converter into the control signal by a digital-to-analog converter (3). - The Pll further includes a differentiator (5D) which responds to the error signal by providing a differentiated signal representative of a discrete-time approximation of the time-derivative of the error signal. The digital filter is responsive to both the error signal and the differentiated signal to provide the digital control signal.
SE9700551A 1995-10-20 1997-02-17 Locked loop SE9700551L (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
SE9700551A SE9700551L (en) 1995-10-20 1997-02-17 Locked loop

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9503702A SE517602C2 (en) 1995-10-20 1995-10-20 Locked loop
SE9700551A SE9700551L (en) 1995-10-20 1997-02-17 Locked loop

Publications (2)

Publication Number Publication Date
SE9700551D0 SE9700551D0 (en) 1997-02-17
SE9700551L true SE9700551L (en) 1997-04-21

Family

ID=26662404

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9700551A SE9700551L (en) 1995-10-20 1997-02-17 Locked loop

Country Status (1)

Country Link
SE (1) SE9700551L (en)

Also Published As

Publication number Publication date
SE9700551D0 (en) 1997-02-17

Similar Documents

Publication Publication Date Title
TW341735B (en) Phase-locked loop
MY109097A (en) An adaptive phase locked loop
WO2002005429A3 (en) Digital phase detector circuit and method therefor
EP0218406A3 (en) Sampling clock generation circuit
CA2152180A1 (en) Phase locked loop synchronization circuit and method
WO2001001577A8 (en) Adjustable bandwidth phase locked loop with fast settling time
IE792526L (en) Digital phase control circuit
KR101015724B1 (en) Audio amplifier
MY114544A (en) Filter circuit
MX9804172A (en) Highly stable frequency synthesizer loop with feedforward.
CA2061475A1 (en) Phase-Lock-Loop System with Variable Bandwidth and Charge Pump Parameters
EP0376847A3 (en) Pll synthesizer
EP0378190A3 (en) Digital phase locked loop
EP0400473A3 (en) Digital signal processing apparatus
SE9700551D0 (en) Locked loop
WO2001093418A3 (en) Linear dead-band-free digital phase detection
MY113714A (en) Synchronized scanning circuit
WO2002009290A3 (en) Analog phase locked loop holdover
EP0540158A3 (en)
ATE175825T1 (en) PHASE CONTROL LOOP WITH ADDITIONAL FREQUENCY DISCRIMINATOR
JPS57143936A (en) Frequency synthesizer
SU1171969A2 (en) Frequency-phase discriminator
JPS57103412A (en) Phase modulation system due to pll
EP0346623A3 (en) A circuit for high-efficiency tuning video frequencies
DE3783786D1 (en) CIRCUIT FOR DIGITAL COMPENSATION OF A DETERMINED NOISE SIGNAL.

Legal Events

Date Code Title Description
NAV Patent application has lapsed