SE9700551D0 - Locked loop - Google Patents
Locked loopInfo
- Publication number
- SE9700551D0 SE9700551D0 SE9700551A SE9700551A SE9700551D0 SE 9700551 D0 SE9700551 D0 SE 9700551D0 SE 9700551 A SE9700551 A SE 9700551A SE 9700551 A SE9700551 A SE 9700551A SE 9700551 D0 SE9700551 D0 SE 9700551D0
- Authority
- SE
- Sweden
- Prior art keywords
- signal
- control signal
- digital
- output signal
- error
- Prior art date
Links
- 230000001419 dependent effect Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The circuit includes an output signal source (9) which provides an output signal in response to a control signal. The output signal has a frequency that is dependent on the control signal. A phase detector (2D) provides an error signal which represents the difference in phase between an input reference signal and the output signal. A first feedback path supplies the output signal to the phase detector. The PLL arrangement also includes a digital filter (6D) responsive to the error signal for providing a digital control signal which is converter into the control signal by a digital-to-analog converter (3). - The Pll further includes a differentiator (5D) which responds to the error signal by providing a differentiated signal representative of a discrete-time approximation of the time-derivative of the error signal. The digital filter is responsive to both the error signal and the differentiated signal to provide the digital control signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE9700551A SE9700551L (en) | 1995-10-20 | 1997-02-17 | Locked loop |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE9503702A SE517602C2 (en) | 1995-10-20 | 1995-10-20 | Locked loop |
SE9700551A SE9700551L (en) | 1995-10-20 | 1997-02-17 | Locked loop |
Publications (2)
Publication Number | Publication Date |
---|---|
SE9700551D0 true SE9700551D0 (en) | 1997-02-17 |
SE9700551L SE9700551L (en) | 1997-04-21 |
Family
ID=26662404
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SE9700551A SE9700551L (en) | 1995-10-20 | 1997-02-17 | Locked loop |
Country Status (1)
Country | Link |
---|---|
SE (1) | SE9700551L (en) |
-
1997
- 1997-02-17 SE SE9700551A patent/SE9700551L/en not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
SE9700551L (en) | 1997-04-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
NAV | Patent application has lapsed |