SE9502780L - Metod och anordning för distribution och synkronisering av klocksignaler i ett digitalt system - Google Patents

Metod och anordning för distribution och synkronisering av klocksignaler i ett digitalt system

Info

Publication number
SE9502780L
SE9502780L SE9502780A SE9502780A SE9502780L SE 9502780 L SE9502780 L SE 9502780L SE 9502780 A SE9502780 A SE 9502780A SE 9502780 A SE9502780 A SE 9502780A SE 9502780 L SE9502780 L SE 9502780L
Authority
SE
Sweden
Prior art keywords
pct
system parts
signal
internal clock
reference signal
Prior art date
Application number
SE9502780A
Other languages
Unknown language ( )
English (en)
Other versions
SE505022C2 (sv
SE9502780D0 (sv
Inventor
Ingemar Soederquist
Original Assignee
Saab Dynamics Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Saab Dynamics Ab filed Critical Saab Dynamics Ab
Priority to SE9502780A priority Critical patent/SE505022C2/sv
Publication of SE9502780D0 publication Critical patent/SE9502780D0/sv
Priority to US09/011,026 priority patent/US5982238A/en
Priority to PCT/SE1996/001010 priority patent/WO1997006478A1/en
Priority to JP50838297A priority patent/JP3928666B2/ja
Priority to EP96927232A priority patent/EP0843846B1/en
Priority to DE69627347T priority patent/DE69627347T2/de
Publication of SE9502780L publication Critical patent/SE9502780L/sv
Publication of SE505022C2 publication Critical patent/SE505022C2/sv

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
SE9502780A 1995-08-08 1995-08-08 Metod och anordning för distribution och synkronisering av klocksignaler i ett digitalt system SE505022C2 (sv)

Priority Applications (6)

Application Number Priority Date Filing Date Title
SE9502780A SE505022C2 (sv) 1995-08-08 1995-08-08 Metod och anordning för distribution och synkronisering av klocksignaler i ett digitalt system
US09/011,026 US5982238A (en) 1995-08-08 1996-08-08 Clock signal distribution and synchronization in a digital system
PCT/SE1996/001010 WO1997006478A1 (en) 1995-08-08 1996-08-08 Clock signal distribution and synchronisation in a digital system
JP50838297A JP3928666B2 (ja) 1995-08-08 1996-08-08 デジタルシステムにおけるクロック信号分配および同期化
EP96927232A EP0843846B1 (en) 1995-08-08 1996-08-08 Clock signal distribution and synchronisation in a digital system
DE69627347T DE69627347T2 (de) 1995-08-08 1996-08-08 Verteilung und synchronisation eines taktsignales in einem digitalsystem

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9502780A SE505022C2 (sv) 1995-08-08 1995-08-08 Metod och anordning för distribution och synkronisering av klocksignaler i ett digitalt system

Publications (3)

Publication Number Publication Date
SE9502780D0 SE9502780D0 (sv) 1995-08-08
SE9502780L true SE9502780L (sv) 1997-02-09
SE505022C2 SE505022C2 (sv) 1997-06-16

Family

ID=20399137

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9502780A SE505022C2 (sv) 1995-08-08 1995-08-08 Metod och anordning för distribution och synkronisering av klocksignaler i ett digitalt system

Country Status (6)

Country Link
US (1) US5982238A (sv)
EP (1) EP0843846B1 (sv)
JP (1) JP3928666B2 (sv)
DE (1) DE69627347T2 (sv)
SE (1) SE505022C2 (sv)
WO (1) WO1997006478A1 (sv)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7017002B2 (en) 2000-01-05 2006-03-21 Rambus, Inc. System featuring a master device, a buffer device and a plurality of integrated circuit memory devices
US20050010737A1 (en) * 2000-01-05 2005-01-13 Fred Ware Configurable width buffered module having splitter elements
US7404032B2 (en) 2000-01-05 2008-07-22 Rambus Inc. Configurable width buffered module having switch elements
US6502161B1 (en) 2000-01-05 2002-12-31 Rambus Inc. Memory system including a point-to-point linked memory subsystem
US7356639B2 (en) * 2000-01-05 2008-04-08 Rambus Inc. Configurable width buffered module having a bypass circuit
US7266634B2 (en) 2000-01-05 2007-09-04 Rambus Inc. Configurable width buffered module having flyby elements
US7363422B2 (en) * 2000-01-05 2008-04-22 Rambus Inc. Configurable width buffered module
US6748549B1 (en) * 2000-06-26 2004-06-08 Intel Corporation Clocking an I/O buffer, having a selectable phase difference from the system clock, to and from a remote I/O buffer clocked in phase with the system clock
US6813721B1 (en) 2000-09-20 2004-11-02 Stratus Computer Systems, S.A.R.L. Methods and apparatus for generating high-frequency clocks deterministically from a low-frequency system reference clock
KR100424118B1 (ko) 2001-05-03 2004-03-24 주식회사 하이닉스반도체 클럭 신호의 주파수 정보를 이용하여 셀 동작을 제어하는동기식 반도체 메모리 장치
US7110400B2 (en) 2002-04-10 2006-09-19 Integrated Device Technology, Inc. Random access memory architecture and serial interface with continuous packet handling capability
US7224759B2 (en) * 2002-07-11 2007-05-29 Honeywell International Inc. Methods and apparatus for delay free phase shifting in correcting PLL phase offset
CN100421048C (zh) * 2003-12-19 2008-09-24 Nxp股份有限公司 集成电路的时钟分配
US7464225B2 (en) 2005-09-26 2008-12-09 Rambus Inc. Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology
US7562271B2 (en) 2005-09-26 2009-07-14 Rambus Inc. Memory system topologies including a buffer device and an integrated circuit memory device
US11328764B2 (en) 2005-09-26 2022-05-10 Rambus Inc. Memory system topologies including a memory die stack
US7876261B1 (en) * 2008-10-28 2011-01-25 Lockheed Martin Corporation Reflected wave clock synchronization
US9395747B1 (en) * 2015-01-08 2016-07-19 Apple Inc. Method for calibrating a clock signal generator in a reduced power state

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63238714A (ja) * 1986-11-26 1988-10-04 Hitachi Ltd クロック供給システム
JPH02105910A (ja) * 1988-10-14 1990-04-18 Hitachi Ltd 論理集積回路
US5008636A (en) * 1988-10-28 1991-04-16 Apollo Computer, Inc. Apparatus for low skew system clock distribution and generation of 2X frequency clocks
US4868522A (en) * 1988-12-13 1989-09-19 Gazelle Microcircuits, Inc. Clock signal distribution device
US5204555A (en) * 1990-04-05 1993-04-20 Gazelle Microcircuits, Inc. Logic array having high frequency internal clocking
US5481573A (en) * 1992-06-26 1996-01-02 International Business Machines Corporation Synchronous clock distribution system
EP0596657A3 (en) * 1992-11-05 1994-12-07 American Telephone & Telegraph Normalization of propagation delay.
JP3247190B2 (ja) * 1993-04-13 2002-01-15 三菱電機株式会社 位相同期回路および集積回路装置
JP3169794B2 (ja) * 1995-05-26 2001-05-28 日本電気株式会社 遅延クロック生成回路
US5565816A (en) * 1995-08-18 1996-10-15 International Business Machines Corporation Clock distribution network

Also Published As

Publication number Publication date
DE69627347D1 (de) 2003-05-15
SE505022C2 (sv) 1997-06-16
JP3928666B2 (ja) 2007-06-13
US5982238A (en) 1999-11-09
SE9502780D0 (sv) 1995-08-08
WO1997006478A1 (en) 1997-02-20
DE69627347T2 (de) 2003-11-27
JPH11510629A (ja) 1999-09-14
EP0843846A1 (en) 1998-05-27
EP0843846B1 (en) 2003-04-09

Similar Documents

Publication Publication Date Title
SE9502780L (sv) Metod och anordning för distribution och synkronisering av klocksignaler i ett digitalt system
SE9603368D0 (sv) Metod och anordning för synkronisering av tidsstämpling
SE9400116D0 (sv) Förfarande och arrangemang för synkronisering vid OFDM- modulering
SE9502483L (sv) Krets och metod för PLL-synkronisering
JP2000148286A (ja) 時刻値分配システム
SE9503284L (sv) Förfarande och anordning för åstadkommande av en synkron kommunikatonsmiljö
FI933776A0 (fi) System foer radiosaendning och -mottagning av digital data, mottagare och saendare som anvaends i detta system
SE9801706D0 (sv) Förfarande och anordning för synkronisering i ett kretskopplat nät
SE9703294D0 (sv) Anordning och förfarande vid radiokommunikation
FI923166A0 (fi) Sdh dataoeverfoeringssystem.
AU546311B2 (en) Sequential data block address processing circuit
SE9604444L (sv) Metod och system för tidsinpassning av en ram i ett kommunikationssystem
TW337563B (en) Optimizing performance in a packet slot priority packet transport system
SE9703944L (sv) Anordning och förfarande avseende radiokommunikation
FR2434521A1 (fr) Circuit generateur de signaux a haute frequence se recouvrant sans interference, pour systeme gradateur de lampes
SE9301327L (sv) Referenssignal sammansatt av klocksignal och synkroniseringssignal, anordning och förfarande för synkronisering m.h.a. referenssignal
JPH1013375A (ja) クロック供給方式
SE9402708D0 (sv) Dämpning av pekarjitter i en desynkronisator
EP0610052A3 (en) Method and device for clock control.
SE9504297L (sv) Förfarande för reducering av transienter i ett redundant klocksignalgenererande system
FR2737633B1 (fr) Generateur de signaux d'horloge pour la synchronisation d'un systeme de traitement de paquets de donnees numeriques
JPS5773545A (en) Phase synchronizing system
AU2002229600A1 (en) An arrangement and method for transmitting data over a tdm bus
KR970004925A (ko) 디지탈 교환기의 동기 클럭 제어회로
KR930015910A (ko) 전전자 교환기의 동기 클럭 분배 장치

Legal Events

Date Code Title Description
NUG Patent has lapsed