SE522038C2 - NPN bipolar transistors for radio frequency use - Google Patents

Abstract

A semiconductor component, in particular an NPN bipolar transistor, comprises an active surface region surrounded by thick field oxide and which is partly covered by an electrically isolating surface layer different from the field oxide. A base region within the active region is defined by a lithographically defined opening in the isolating layer. Also claimed are: (i) a process for manufacturing a transistor as above; (ii) a capacitor at the surface of a substrate comprising a dielectric layer over a highly doped buried region; (iii) a process of manufacturing the capacitor above; (iv) a process for producing a free area at a surface of a substrate which is limited by a nitride layer; (v) a side-string structure having conductive silicon contact a border of an active area; and (vi) an integrated circuit, bipolar device and process.

Description

522 038 2 are separated, separated by an oxide layer dryer area 109 ', insulation trenches 110 are defined by lithographic means, after which the silica material 107 and the substrate material 101 are etched away by means of anisotropic dry etching, until the trenches 110 have the desired depth, about 5 - 10 μm, and stretch The walls of the trenches 110 are thermally oxidized to form a thin electrically insulating layer, after which they are filled with an insulating or semi-insulating material 111, for example silicon oxide or polycrystalline silicon (also called polycrystalline silicon). Si or polysilicon). The filling material is then etched away by means of dry etching, until a flat surface is obtained. Then the surface of the disc is oxidized and in particular the silicon material is oxidized the openings of the trench shafts in the event that the trench has been filled with polysilicon, in order to obtain an insulating layer on the surface of the opening. If the trenches 110 are initially filled with oxide alone, no such additional oxidation step is required.

The result is shown in Fig. 3. It can be observed that the extent of the base area 108 in Fig. 3 is defined by means of LOCOS technology as above. The weakness of this method will be discussed later, among other things in connection with the description of a modified method for producing an ice transistor.

After the formation of the trenches 110, a collector plug 112 is defined, see Fig. 4, ie a low-resistance connection between the surface of the component plate and the bottom diffusion 102, within the collector area 109, in a lithographic way. Then a dopant, usually phosphorus, is applied by ion implantation in the lithographically defined openings. The description of the further manufacturing process will be related to the manufacture of the above-mentioned NPN transistor of the double-poly-Si type with self-registered base-emitter junction, since the component type is usually combined with electrical insulation provided by trenches.

Following the above-described definition of active areas 108, 109 and the formation of a zs collector plug 112, a thin layer 113 of polysilicon with a thickness of a few hundred nm is deposited, see still Fig. 4. The polysilicon layer 113 is then doped to type P + by means of ion plating. boron, after which a thin oxide layer 114 is deposited on top of the polysilicon layer by means of CVD ("Chemical Vapor Deposition"). This table-doped polysilicon layer of type P + will, after completion of production, form a so-called extrinsic base or base-connection. The oxide layer 114 produced by CVD and the underlying polysilicon layer 113 are patterned on a lithographic path to define an emitter opening 115 located within the base region 108. Thereafter, those portions of these two layers which are not covered by the lithographic mask are removed. using dry etching (plasma etching). After patterning of the emitter orifice 115, a thin thermal oxide 116 is grown to protect the surface of the emitter orifice, as a so-called intrinsic base 117 is created by ion implantation of boron. The intrinsic base 117 is thus located just inside and below the emitter opening 115.

To separate the emitter to be produced from the extrinsic base, spacers or edge strands 118 are formed along the edge of the emitter port 115, see Fig. 5.

This is done by first depositing an oxide layer by means of CVD compound over the board, after which an anisotropic dry etching method is used to etch away this oxide layer on the flat surface portions of the board. This results in an edge strand or spacer 118 of CVD oxide along the ledges or steps created by the pattern for making the ernitter opening 115.

After formation of such spacers 118, an additional thin polysilicon layer 119 with a thickness of a few hundred nm is deposited on the surface of the disc. This layer is implanted with arsenic to become type N + and after heat treatment will form the emitter electrode 120 of the transistor. After patterning and etching the layer 119 for manufacturing the emitter electrode 120, the structure acquires the appearance shown in fi g. 5. Usually, areas of this upper polysilicon layer 119, thus forming the emitter electrode, are also left over the collector wire 109, see Fig. 3, m and the collector plug 112, where it serves as a collector contact 121.

The circuit is then passivated with a layer 122 of, for example, silica, see fi g. 6, in which contact holes 123, 124, 125 to the base, emitter and collector of the transistor are defined by lithographic means. After etching the contact holes, the circuit is coated with a metal layer 126 by means of sputtering ("sputtering") of, for example, aluminum, which penetrates into the contact holes 123, 1s 124, 125 and is to constitute electrical contact with the outside world. The conductor layer 126 is then defined by means of lithography and etching for the production of external contacts 127, 128, 129 and the end result is shown in Fig. 6, also compare Fig. 1. Fig. 1 gives a better picture of the final component, although there also the thicknesses of the layers are in some cases excessive.

As can be seen from the above description, the base region 108 is defined by means of zo LOCOS technology, see Fig. 3. In this case, a two-layer structure consisting of silica, which lies directly on top of monocrystalline silicon, and silicon nitride is used as a local oxidation mask in thermal culture. of the so-called field oxide 107. In field oxidation, a certain lateral diffusion of oxygen will take place along the boundary layer between monocrystalline silicon and silicon oxide, whereby some oxide growth also takes place below the nitride edge, see 130 in fi g. 3. This oxide 130 is usually popularly referred to as "birds-beak". As a result, the extent of the base area will only to a certain extent be determined by the lithographically defined nitride oxide mask structure. It can be said that the accuracy of the area of the area is de-nied by the size of the remaining "birds-beak" after completion of production. To compensate for the lack of accuracy and process variations in the production of these "birds-beak", the base board 108 is made unnecessarily large. This results in such an unnecessarily large capacitance between base and collector.

Furthermore, in the production of the field oxide 107 in the N-region 104, an accumulation 131 of dopants (so-called "dopant pile up") will take place in the boundary layer between the field oxide 107 and the surface of the monocrystalline silicon substrate 101, see Fig. 3. When then the polysilicon layer 113 of type P +, which forms extrinsic base, is brought into contact with the base region 108 outside the edge strands 118, this results in an increased capacitance between base and collector in the final NPN transistor, see Figs. 3 and 4.

DISCLOSURE OF THE INVENTION It is an object of the present invention to provide such a solution to the above problems, that a substrate capacitor, i.e. a passive capacitor component at the surface of the substrate, is formed simultaneously with the production of a bipolar NPN transistor.

To provide an NPN transistor, a laminated layer of silicon oxide and silicon nitride located on top of the active region (collector region) of the NPN transistor is introduced. The laminate is patterned in a lithographic way, so that the base area of the transistor is defined by an opening in the laminated layer. At the same time, a lateral PNP transistor can be provided with lithographically defined apertures for producing emitter and collector demia transistors.

This also makes it possible to form a substrate capacitor, which uses the silicon nitride layer as a dielectric, without any additional mesh step at the same time as the capacitance between base and collector of the bipolar NPN transistor is reduced. w A semiconductor component, which may be an NPN-type bipolar transistor, has an active region at the surface of the component, which is surrounded, seen along the surface of the component, in a conventional manner by thick field oxidone wires. The active area is partially covered by an electrically insulating surface layer, preferably comprising a nitride layer. A base area in the active area is determined by a well-defined, lithographically produced opening in the electrically insulating surface layer. In the case that the semiconductor component, which in this case may be a bipolar transistor of the PNP type, instead has emitter and collector regions, which are surrounded at the surface of the component, seen along the surface of the component, by such thick field oxide regions, an emitter region and or a collector area in a corresponding manner be determined resp. determined by a lithographically defined opening in an electrically insulating surface layer. By the lithographic definition, in these two cases the electrically insulating surface layer will extend over and past the surrounding field oxidone regions, so that a strip of the electrically insulating surface layer is found between the base area resp. between the emitter or collector area and the phlox oxidor areas closest to this area.

The electrically insulating surface layer advantageously comprises a larnate of silicon nitride zs at the top and silicon oxide below. The silicon nitride layer is advantageously used as an efficient dielectric in a capacitor produced at the same time.

DESCRIPTION OF THE DRAWINGS The invention will now be described by means of non-limiting exemplary embodiments in connection with the accompanying drawings, in which Figs. 2 is a cross-sectional view of the starting material for producing it in fi g. 1 is shown transistently after the formation of a bottom diffusion and an epitaxial surface layer, - Fig. 3 is a cross section similar to fi g. 2 but after the fi nition of the active area and after isolation by means of trenches, - Fig. 4 is a cross section similar to fi g. 2 but after the fi nition of emitter opening and extrinsic base, - Fig. 5 is a cross section similar to fi g. Fig. 6 is a cross-section similar to Fig. 2 but according to the definition of the first metal layer, - Fig. 7 is a cross-section of a silicon wafer and layers arranged thereon intended for production of primarily an NPN transistor with good high frequency properties but also for the production of a capacitor and a lateral PNP transistor, where the cross section is shown the disc before the formation of the bottom diffusions, Fig. 8 is a cross section similar to Fig. 7, which shows Fig. 9 is a cross-section similar to Fig. 8 but after the formation of bottom diffusions, Fig. 10 is a cross-section similar to Fig. 9, showing the condition of the disc when performing additional P-doping. Fig. 11 is a cross-section similar to Fig. 10 after deposition of epitaxial silicon on the surface of the disk, Fig. 12 is a cross-section similar to Fig. 11, showing the state of the disk upon selective formation of the N-one regions, a cross section Fig. 12 after selective oxidation of N-regions and ice formation of self-aligned P-shape regions, - Fig. 14 is a cross-section similar to Fig. 13 after definition of the component regions, where different component regions are indicated, - Figs. Fig. 14 after field oxidation, showing areas for an NPN transistor and a capacitor resp. a region for a lateral PN P transistor, zo - Fig. 16 is a cross section similar to fi g. Fig. 17a is a cross-section similar to Fig. 16 but after removal of the hard mesh and barrier layer and oxidation of walls in the trenchs, Fig. 18 is a cross-section similar to Fig. 17 after filling of trenches with a polysilicon layer, Fig. 19 is a cross-section similar to Fig. 18 after oxidation of polysilicon in the openings of the trenches, zs - Figs. 20a and 20b are cross-sections similar to fi g. 19, which shows the state of the disk in the formation of a collector at areas of an N PN transistor and a capacitor resp. a region for a lateral PNP transistor, Figs. 21a and 21b are cross-sections similar to Figs. Fig. 20b after deposition of a silicon nitride layer and definition of emitter-base zone, ao - Fig. 22 is a cross section similar to Fig. 21a after definition of a base region and deposition of amorphous silicon, Figs. 23a and 23b are cross-sections similar to Fig. 22 according to the definition of an enitter array region, upper capacitor plate and substrate connections and showing regions of an NPN transistor and a capacitor resp. a region for a lateral PN P transistor, as - Fig. 24 is a cross-section similar to Fig. 23a, showing the state of the disk at basal implantation, - Fig. 25a is a cross-section similar to Fig. 24, showing the state of the disk in the formation of spacers. for insulation between base connection and emitter connection, Fig. 25b is a cross-section showing a part of the cross-section in Fig. 24 after formation of spacers of an alternative design, Fig. 25c is an electron microscope image taken of an emitter structure according to fi g. Fig. 25d is a view taken by means of an electron microscope of an emitter structure according to Fig. 25b, s - Fig. 26a is a cross section similar to fig. Fig. 26b, which shows the state of the disk in the formation of an emitter, where a polysilicon layer is shown before and after etching, and which shows areas of an N PN transistor and a capacitor, Fig. 26b is a cross-section showing a part of the structure , which is partly shown by fi g. 26a, and showing the formation of low and high resistive resistors, Fig. 26c is a cross section similar to fi g. Fig. 27a and 27b are cross-sectional views similar to fig. 26a resp. Fig. 28a and 28b are cross-sections similar to Figs. 27a and 28b after etching of oxide layers applied on top of a polysilicon layer doped with P +. Fig. 27b after driving in of ernitter and base regions and etching for the production of additional spacers, - Fig. 29 is a diagram showing a dopant profile of a manufactured NPN transistor, which is occupied by means of SIMS, - Fig. 30 is a top view of a protective mask layer applied over resistance when etching the spacers shown in Figs. 28a and 28b, zo - Fig. 31 is a part of the cross-sectional view in fi g. 27a, which shows only the manufactured transistor, - Figs. 32a and 32b are cross-sections similar to fi g. 28a resp. 28b after deposition of titanium and silicidation and chemical removal of titanium and titanium nitride, - Fig. 33 is a cross section similar to Fig. 32a after etching of deep contact holes for electrical connection of substrates, zs - Figs. 34a and 34b are cross sections Fig. 35 is a cross-sectional view of the final fabricated electronic circuit element comprising two kinds of transistors, two kinds of capacitors and a resistor element, the circuit, in which deep, tungsten-filled substrate contacts, a polysilicon resistor and a transducer-insulated NPN transistor are visible, Fig. 37 is a top view schematically showing how the various components are designed.

DESCRIPTION OF PREFERRED EMBODIMENTS In connection with Figs. 7 to 38, the fabrication of various high performance electronic components will be described, all of which may be fabricated simultaneously on the same substrate. Some of these figures, which show cross-sections through a substrate, are highly schematic, while others show better the resulting structures, which are of course best shown in the photographic images. It should also be pointed out that for certain components, which are described below as made and built up of materials with certain doping types, the corresponding component can also be made of materials with opposite doping types, ie a component made up of certain 5-doped first materials and certain N-doped second materials may in some cases just as well be composed of corresponding N-doped first materials and corresponding P-doped second materials.

I ñg. 7 shows a cross section of a P-type silicon wafer 1, preferably doped with boron, before the formation of a bottom diffusion or buried layer of the N-type (so-called "buried N-type layer"). The silicon wafer 1 can either consist of a homogeneous very low doped P-type wafer, with typical resistivity of 10 - 20 ohm-cm, which can be described as being of type P--, or of a so-called epi-wafer, in which the substrate 1 'consists of a highly doped P-type (P +) wafer with typically a resistivity of a few tens of mohm-cm, on which a P-type epitaxially low doped layer has been grown, of type P--. The cultured epitaxial layer of type P-- is typically 5 - 10 μm thick with a resistivity of 10 - 20 ohm-cm. A starting material similar to that used in the latter case is used in the bipolar structure, which is shown in the article by V. dela Torre et al., "MOSAIC V - A Very High Performance Technology", BCTM 1991, pp. 21 - 24. According to this article, a highly doped type P + substrate is used and then an epitaxial intrinsic layer, i.e. a layer without actual doping. At the surface of the intrinsic layer, structures similar to those to be described below are then formed, such as bottom diffusions, etc.

A protective layer 2 of silica is applied to the surface of the silicon wafer 1 by means of known techniques, for example by thermal oxidation. The thickness of the oxide layer 2 is preferably selected to be about 0.8 μm. It is patterned by lithographic means, by applying and patterning a photoresist layer 3, after which the oxide is dissolved or etched away in the portions which are not protected by the photoresist layer 3, as illustrated in fig. 7. The removal of oxide can take place by means of well-known wet chemical or dry chemical methods, after which the photoresist layer 3 is removed in a known manner.

A thin protective oxide layer 4, with a thickness typically of a couple of hundred Ångström, is thermally grown over the surface of the disc 1, see fi g. 8, this protective layer lying in particular on the surfaces between the comparatively much thicker remaining portions of the previously applied silica layer 2, while due to its small thickness it is not noticeable in the said portions, which are moreover of the same type of material. Thereafter, a bottom diffusion layer of type N + (so-called "N + buried layer") is provided, by first performing an ion implantation, as indicated by the arrows in fi g. 8. In this ion implantation step, arsenic is preferably used, which is implanted so with an energy of about 50 keV and a dose of about 3-1015 ions / cm 2. The remaining portions of the thick oxide layer 2 should serve as a mask during the implantation and then the energy during the implantation must be adjusted so that only the ions which hit the thin oxide 4 are able to penetrate into the silicon substrate 1, as indicated by the crosses at 4a in fi g. 8, while the others are hindered by the thick oxide layer. After completion of implantation, a heat treatment is performed to collect the implanted dopant, ie of the arsenic atoms, at high temperature, typically for 30 minutes at 100 ° C, to create a bottom diffusion layer 5, see fi g. 8. The resulting depth of the bottom diffusion orbits 5 of type N + ("N + buried layer") after this collection is about 1.5 μm, see fi g. 9. During the recovery, a further oxidation of the silicon surface takes place at the same time, whereby silicon atoms at the surface are consumed, so that the thickness of the protective layers 4 of thin silicon oxide increases to about 200 mn, whereby layer 6 of greater thickness is obtained. The consumption of silicon atoms also results in a step or a ledge in the surface of the monocrystalline silicon substrate itself between the areas which are covered by the previously applied thick oxide layer 2 and the areas which have now been made thicker and yet are covered. of an still significantly thinner oxide layer, which step in the further process is used as a pass mark (so-called "alignment ground").

Of course, other N-type dopants can also be used in the implantation for the production of the bottom diffusion layers 5, such as, for example, antimony. However, the use of antimony requires a heat treatment at a slightly higher collection temperature, typically for some half an hour at about 1250 ° C.

After the drive in to produce the bottom diffusion of type N +, all oxide, preferably wet chemically, is released from the surface of the disk, the previously mentioned steps appearing in the surface of the monocrystalline silicon plate, see fi g. 10. A thin protective oxide layer 7, typically 30 - 40 nm thick, is then prepared over the surface of the disc, preferably by tennis cultivation. An additional P-type doping is created in the areas which lie between the bottom diffusion areas 5 of type N +, by carrying out over the entire surface of the disk an ion implantation of preferably boron with an energy of about 100 keV and a dose of about 4-1012 ions / cm2, as indicated by the arrows in fi g. 10. This implantation energy and dose are adjusted so that the boron atoms implanted therein in the arsenic doped bottom diffusion regions 5 of type N + are completely enclosed and thus compensated by the doping in these regions, whereby the bottom diffusion 5 remains of type N + with only a relatively small or negligible reduction in the content of donor atoms.

It is worth noting that one can very well do without the just mentioned implantation of boron and obtain well-functioning components, by increasing the degree of doping in the starting material 1 from the very beginning from being very low doped, almost intrinsically. to be of type P-. However, the capacitance contribution from the bottom diffusion areas 5 of type N + in the final component will be higher in this case. The general procedure for making N + type bottom diffusions and P-type intermediate regions is also shown in U.S. Pat. patent 5,374,845 to Havemann, see the description of fi g. 2 and 3 of this patent. After the preferred drilling implantation described above, when areas with weak P-doping, ie of type P-, are obtained between the bottom diffusion areas 5, all oxide, preferably wet chemically, is dissolved away from the surface of the disc, so that steps reappear , after which an epitaxial silicon layer 9 is cultured on the substrate surface by means of known technology, see Fig. 11. The epitaxial layer 9, which is about 1.2 μm thick, is preferably undopated (so-called "intrinsic silicone"). If desired, the layer 9 can be doped to N-type already at the epitaxial growth. The degree of doping in that case is typically of the order of 1-1016 / cm3. In the aforementioned U.S. Pat. patents for Havemann, the corresponding epitaxial layers are very easily doped with resistivity greater than 10 ohm-cm, but are nevertheless stated to be essentially intrinsic, ie undoped. However, a homogeneously doped epitaxial layer makes it difficult for later contact of the substrate from the surface (so-called "top-down contacts"). At the epitaxial growth, temperatures are used such that the acceptor atoms in the previously implanted types of type P- will diffuse into the substrate 1 and the co-formed epitaxial layer 9, so that buried areas 8 of type P- (so-called "Buried") P - surface.

The epitaxial layer 9 will, as will be seen from the description below, be selectively doped to obtain areas of the respective N- and P-type (so-called "N-wells and P-wells"). In the N-type regions, which are located directly above the N + type bottom diffusion regions, bipolar transistors and capacitors will be formed. In intermediate P-areas, after completion of production, there will be connections which serve as a connection between the circuits or components formed at the surface and the substrate 1.

After culturing the epitaxial silicon layer 9, a thin barrier oxide layer 10 is produced, preferably by means of thermal oxidation, over the surface of the disk, see Fig. 12. The thickness 1s of the oxide layer is typically about 40 nm. On top of the barrier oxide layer 10, a thin silicon nitride layer 11, typically about 130 nm thick, is deposited by means of LPCVD technology (= "Low Pressure Chemical Vapor Deposition", chemical deposition from vapor phase at low pressure). This nitride layer 11 is lithographically patterned by applying a photoresist layer 11 'and patterning it, after which the nitride is etched away in the portions not protected by the photoresist layer 11', as illustrated in Fig. 12, these portions comprising the component areas themselves, in which now only the silica layer 10 is found. The silicon nitride layer 11 is preferably etched by means of a suitable dry etching process, which selectively removes only the nitride and leaves the oxide layer 10 lying below the nitride layer. N-type or N-wires 13 (so-called "N-Wells") in the epitaxial silicon layer 9, the underlying thin silicon oxide layer 10 acts as a protective layer for the surface of the epitaxial layer 9.

In a preferred embodiment, this ion implantation step is performed to form the N-ion regions 13, see Fig. 13, by preferably implanting phosphorus with an energy of about 450 keV and a dose of about 151012 ions / cm 2. However, the implantation conditions can be changed if such a different doping profile in the N-order regions 13 is desired.

After implantation, the photoresist layer 11 'is removed in a known manner, after which the thin oxide layer 10 in the openings in the nitride layer 11 is thickened or built up by thermal culture, so that after the culture an approximately 450 nm thick silicon oxide layer 12 is obtained, see fi g. 13. The dopant used in the implantation just described, which in the preferred case is phosphorus, as mentioned above, will during this oxidation step diffuse into the epitaxial layer 9, whereby the N-one regions 13 are partially finished. Some definition of dopants therefrom will occur during those of the following steps, which include high temperatures. The remaining areas of the nitride layer 11, which act as a barrier layer in thermal oxidation of the surface of the silicon wafer, cause oxide in this thermal culture to grow only in the areas in which the nitride layer 11 has been removed, ie in the areas which have been implanted. After oxidation, the nitride layer 11 is completely removed from the disk, preferably by means of wet chemical methods.

The underlying thin oxide layer 10 remains and forms steps at its edges towards the thicker silica areas 12. The turma oxide layer 10 acts as a protective layer in the subsequent implantation, which is intended for the production of the above-mentioned areas of P- type or P-areas (so-called "P-wells") and which is illustrated by the arrows in fi g. 13.- The energy at this ion implantation step is adjusted so that the ions are only able to penetrate the areas which have the thin oxide layer 10 at their surface, and are blocked by the areas with the thicker oxide layer 12 at their surface. This gives P-regions 14, which are self-aligned (so-called "self-aligned") to previously implanted N-regions 13. In the preferred embodiment, this ion implantation is performed to form the P-regions 14, by preferably being implanted with an energy of about 50 keV and a dose of about 2-1013 ions / cmz. However, as above, the implantation conditions can be changed if a different doping profile in the P-areas 14 is desired. After implantation, friend treatment is performed to recover the implanted dopants at high temperature, typically for 4 hours at about 1000 ° C, to obtain the desired diffusion depth for the N- and P-one regions 13, 14. The resulting structure after heat treatment is shown i fi g. 13. Also, the above-described method of creating N and P regions is described in the said U.S. Pat. the patent for Havemann.

After rubbing, by means of preferably wet etching, all oxide layers are dissolved away, ie both areas with a thin oxide layer 10, areas with a thick oxide layer 12 and any extra oxide, which has also been formed at the surface of the board during the just previous heat treatment performed for rubbing. of implanted atoms. After release of the oxide, the ledges appear in the surface of the silicon wafer. Then known LOCOS technology ("Local Oxidation of Silicon") technology is used, see the above mentioned article by J.A. Appel et al., "Local oxidation of zs silicon and its application in semiconductor technology", Philips Research Report, Vol. 25, 1970, pp. 118 - 132, to define active openings for the components to be manufactured. Thus, first, a thin barrier oxide layer 15, typically 15 nm thick, is applied over the entire surface of the wafer by preferably thermal oxidation, see fig. 14. On top of this oxide layer 15, a significantly thicker nitride layer 16, with a thickness of typically 200 nm, is deposited by means of preferably LPCVD technology. The nitride layer 16 is patterned by lithographic means by applying a photoresist layer 17 and patterning it to define the component threads, after which the nitride layer 16 is etched away in the portions thereof which are not protected by the photoresist layer 17, as shown in fi g. The nitride layer 16 is preferably etched using a mandatory dry etching process, which selectively removes only the nitride and leaves the underlying thin barrier oxide layer 15.

I fi g. 14 shows three different N-regions 13, in which a lateral PNP transistor, a capacitor and a vertical NPN transistor are to be formed from left to right. The silicon nitride layer 16 here essentially covers areas within which the base connection, collector and emitter of the lateral NPN transistor are to be formed, an area within which a part of an electrode connection 522 038 11 is to be formed, and another area within which both electrode connection and dielectric shall be formed in the capacitor, and an active region and a collector connection region in the vertical NPN transistor.

After etching away the nitride layer 16 in the openings of the photoresist layer 17, the latter layer is removed in a known manner, after which a silicon oxide layer 18, so-called field oxide, is cultured in the openings in the nitride layer 16. In the preferred embodiment, the felt oxide 18 is preferably grown in a wet atmosphere. at typically 950 ° C. The presence of the nitride layer 16, which acts as a barrier layer in the thermal oxidation of the silicon surface, causes the silicon oxide to grow only in the areas within which the nitride has been removed. Since some silicon in the openings in the nitride layer 16 is consumed upon conversion to silica, the field oxide 18 will thereby be partially "semi-recessed" in the substrate surface or the actual surface of the epitaxial layer 9. The result is shown in FIG. 15a and 15b, of which fig. 15a shows the ranges within which the capacitor and the NPN transistor and fi g. 15b shows the range within which the lateral PNP transistor is to be fabricated. The latter figure also shows how the areas of field oxide layer 18 have grown under the edges of the silicon nitride layer 16.

After the field oxidation, the nitride layer 16 and the silica layer 15 are removed, preferably by wet chemical means, after which a silica layer 15b with a thickness of about 30 nm, so-called KOOI oxide, is thermally cultured. This layer becomes visible only in areas between the areas of field oxide 18.

Then a thin barrier layer 19, typically about 60 nm thick, of polycrystalline silicon (polio Si) is deposited over the surface of the board, see Fig. 16. In the preferred embodiment, the polysilicon layer is deposited by means of LPCVD technology. However, the barrier layer 19 can advantageously also consist of another type of silicon equivalent here, such as microcrystalline or amorphous silicon. A silicon oxide layer 20, typically 250 nm thick, is deposited on top of the barrier layer 19 of polysilicon. In the preferred embodiment, the oxide layer 20 is deposited by LPCVD technique by thermal decomposition of TEOS (tetrazyl ethyl orthosilicate). After deposition, the oxide layer 20 is densified by heat treatment, typically for 3 hours at 800 ° C, in a wet atmosphere. The oxide layer 20 can also consist of so-called LTO oxide ("Low Temperature Oxide") or PECVD oxide (oxide produced by means of PECVD, "Plasma Enhanced Chemical Vapor Deposition", plasma assisted chemical deposition from vapor phase), since the purpose with this oxide layer is only to serve as a hard-mask ("hard-mask") in the subsequent steps of etching trenchs, see also US U.S. Patent 4,958,213 to Eklund et al.

In the known process, however, a nitride layer is used instead of the oxide layer 20.

The structure is then patterned by lithographic means by applying a photoresist layer 21 and making openings therein, for the purpose of defining deep electrically insulating trenches, so-called trenches, around the respective component and / or groups of components, ss to be produced. , see Figure 16. In the preferred embodiment, the openings for making trenches are located so as to lie above areas of the felt oxide layer 18 and completely or partially overlap the steps in the silicon surface itself which mark the transition between the P-wells 14 and P-wells. The areas 13 (N-wells), which areas lie mainly in the epitaxial layer 9. In the places not protected by the photoresist layer 21, the upper oxide layer 20, the underlying barrier layer 19 of polysilicon and the lower field oxide layer 18 are etched away. at the bottom surface of the epitaxial silicon layer 9. This etching, which is carried out in fl your steps, which are adapted for removal of the respective material, takes place before by dry etching. After etching, the photoresist layer 21 is removed in a known manner, after which deep trenches 22 are etched down through the epitaxial layer 9 to the silicon substrate 1 according to the pattern defined by the just lithographically created openings in the top oxide layer 20. This oxide layer 20 serves during this trench etching step. as a layer of worms, a hard worm. In the preferred embodiment, the trenches 22 are about 1 μm wide and about 6.5 μm deep. They can be made so that the side walls are almost vertical near the surface of the epitaxial silicon layer 9 and so that the trenchs taper downwards and end with a slight rounding of their bottom, as illustrated in fi g. 16. The purpose of the test is to facilitate subsequent filling (plugging) of the trenches 22 with polysilicon and to reduce mechanical stresses in the substrate 1, ie to reduce the tendency of the substrate to rupture at the deep trenches 22, which constitute fracture indications. Such trenchs are also shown in Swedish patent application 9701934-3, "Integrated circuit, components therein, and the manufacturing process". In the preferred embodiment, according to the above, the starting material consists of a so-called episcax or epitaxial disk, i.e. the substrate consists of a highly doped silicon wafer of type P +, typically with a resistivity of a few tens of mohm-cm, on which an epitaxially low doped silicon layer of type P has been cultivated. The cultured epitaxial layer is typically about 6 μm thick with a resistivity of 10 - 20 ohm-cm. As a result, the depth of the trenches 22 will be such that they always reach down to the highly doped type P + silicon bulk, see the above-cited article by V. dela Torre et al. This ensures a high electric field threshold along the lower part of the trenches 22 and thereby prevents leakage currents from passing along the mantle surface of the trenches 22. thereby further a good electrical insulation between the various components to be manufactured. In the case where a low doped substrate 1 of type P- is used, typically having a resistivity of 10 - 20 ohm-cm, an additional ion implantation step is performed after the etching to make the trenches 22 to raise the electric field threshold along the lower ao portion of trench channels 22 (so-called "trench channel stop"). Preferably, then, boron atoms (having a "tilt angle" of 0 °) are implanted with an energy of about 20 keV and a dose of about 5-1013 ions / cm 2, see U.S. Pat. patent for Eklund et al. The energy and dose of this implantation may vary slightly depending on the conditions of the processing steps for making the trenches 22. The treatment in this case with low doped substrate is briefly described in the article by P.C. Hunt as et al., "Process HE: A Highly Advanced Trench Isolated Bipolar Technology for Analogue and Digital Applications", Proceeding of IEEE 1988, Custom and Integrated Circuits Conference, New York, May 16-19.

After the etching of the trenches is completed, the remaining portions of the oxide layer 20 ("hard-mask") are etched away. In this case, the layer closest to the underlying layer 19 of polysilicon serves as an etching stop. Thereafter, the polysilicon layer 19 is etched away with a choice of etching and etching conditions which leave the tent oxide portions 18 immediately below the polysilicon layer 18 and the silica 15b virtually unaffected. In this way the good uniformity of the thickness of the field oxide is maintained.

This etching process can preferably be performed immediately after the etching of the trenches s 22 is completed by means of sequential dry etching in a multi-chamber system ("cluster system").

After the etching of the trenches 22 and after removal of the silica hard mask 20 and the polysilicon barrier layer 19 and the silica layer 15b, the surface of the wafer is thermally oxidized at about 900 ° C in a wet atmosphere. The walls of the trench 22 are also oxidized and the resulting thickness of the oxide layer 23 on the walls of the trench becomes about 30 nm, see fi g. 17. The thus obtained barrier oxide layer 24 on the upper surface of the disk, which is grown simultaneously with (by thermal oxidation) with the oxide layer 23 on the walls of the trenches, has a thickness of about 30 nm, see fi g. 17.

A thin layer of silicon nitride 25 is then deposited on top of the barrier oxide layer 24, preferably by means of LPCVD technology, see fi g. 18. A further oxide layer 26, about 30 nm thick, is then deposited thereon, by preferably thermal decomposition of TEOS, also by means of ice LPCVD technology. Surface layers corresponding to the nitride layer 25 and the oxide layer 26 thus obtained are also found along the mantle surface and the bottom of the trenches 22 due to the conformal deposit obtained by LPCVD technology. Finally, a thick layer 27 with a thickness of about 1.5 μm of microcrystalline silicon or polysilicon, also by means of LPCVD technology, is deposited over the surface of the disc, so that all the trenches 22 are completely filled (grow together) by this chisel seal layer. In the preferred embodiment, microcrystalline silicon is used, as this gives a better degree of filling.

After deposition of the layer 27 of microcrystalline silicon or polysilicon, this layer 27 is removed (removed) on all upper or outer surface portions of the disc by means of dry etching, see fi g. 18, so that material from this silicon layer remains only in the trenches 22. In the preferred process, the etching is stopped when the oxide layer 26 closest to the layer 27 of microcrystalline silicon has been exposed at the upper or outermost surface portions of the disc. This avoids unnecessary over-etching of the microcrystalline silicon or polysilicon, which constitutes the filling material in the trenches 22. Nevertheless, it may happen that the trenches 22 do not remain completely filled after this step. ao After etching is completed, the silicon wafer is oxidized tennis at about 950 ° C in a wet atmosphere. At its upper surface, the silicon 27 which fills the trenches 22 is oxidized, so that an approximately 0.4 hour thick insulating layer 28 (so-called "cap oxide") of silica is formed in the mouths or openings of the trenches, see fi g. 19. The existing nitride layer 25, which acts as an oxidation barrier, prevents the other portions of the disk from being further oxidized. The top thin oxide layer 26 and ss the nitride layer 25 directly below it on the upper surface of the disc are then removed by sequential dry etching. This dry etching is stopped at the layers immediately below the nitride layer 25, i.e. when the surface of the field oxidor regions 18 and the barrier oxide layer 24 have been exposed.

It was initially mentioned that it is well known that a bottom diffusion of type N + is used as a low-resistance collector electrode in an NPN transistor. To ensure low resistance between the collector connection at the silicon surface and the buried bottom diffusion 5, a so-called collector plug is formed. Demia plug is defined in lithographic way, see fi g. 20a, by applying a photoresist layer 31 over the entire surface of the disc and a pattern is made of this layer, so that an opening for an area 30 'of the plug in the photoresist layer 31 is formed over the relevant component area. In the preferred embodiment, the bottom diffusion 5 also functions as one electrode in a plate capacitor, which is to be produced simultaneously. Accordingly, in this process step, an opening for a 30 "electrode wire for electrodes in the photoresist layer 31 is also defined, within which area this capacitor is to be manufactured and which area comprises two separate areas of connection plugs to the buried area 5 of type N + to reduce the series resistance to 10o. The openings in the photoresist layer 31 are made so as to cover entire areas between areas of the field oxide layer 18, which also means that the remaining portions of the photoresist layer 31 cover other whole areas between areas of the field oxide shield 18. This condition can also be expressed as such that the edges of the apertures in the photoresist layer always lie ice over areas of the field oxide layer 18. Apertures are also present over areas 30 "'for base connection of the lateral PNP transistor to be produced, see fi g. 20b.

After the patterning of the photoresist layer 31, a doping is performed at the openings in the photoresist layer 31, i.e. at the openings for the area 30 * of the collector plug, the opening at the area 30 "for the capacitor electrodes 30" and at the openings 30 "'for the areas for the base connection, for the creation of N-type strongly doped regions, as illustrated by the arrows in fi g. 20a and 20b. It is important that the energy of this implantation is chosen so that the extent of the defects which are introduced into the silicon at the implantation stage itself does not pass down to the depth determined by the lower surface or bottom of the phthalate oxide layer 18, i.e. the level , where this layer ends, seen in the direction down from the surface of the disc. the transition with associated leakage problems in the NPN transistor to be fabricated. Consequently, the implantation energy and the dose may vary somewhat depending on the conditions of the field oxidation previously carried out for the production of the field oxide layer 18, see in particular the above-mentioned Swedish patent application 9701934-3.

After implantation, the thin protective oxide layer 24 on top of implanted areas is removed, preferably by means of dry etching, see still fi g. 20a and 20b. It can be observed, however, that this oxide layer 24 remains on the surface portions covered by the photoresist layer 31, i.e. on the parts of the bipolar NPN transistor, among others, where a base region 36 'will later be defined. se fi g. 21a. Thereafter, the photoresist layer 31 is removed in a known manner, after which the disk, for recovery of the dopant introduced during implantation, is heat-treated at typically 900 ° C for about half an hour in a preferably non-oxidizing atmosphere, for example containing NZ or Ar. The resulting collector plug 31 of type N +, one of the capacitor electrodes 32 and a connection 32 "thereto, also of type N +, and plugs 32" for connection of the buried base connection layer 5 in the lateral PNP transistor after this heat treatment is shown in fi g. 21a and 21b.

After heat treatment is completed, any (thin) oxide layer formed in the area 30 "of the capacitor and in the area 30 ', on top of the collector plug 31 of the NPN transistor and in the areas 30"' of the base connection of the PNP transistor, is removed by for a brief moment etched in dilute hydrochloric acid. Immediately after this etching, a thin silicon nitride layer 34 is deposited over the disk, preferably using LPCVD technology, see fi g. 21a and 21b. This nitride layer 34 serves two special purposes in the manufacturing process: wi) The part of the nitride layer 34 which is in direct contact with the area of the silicon wafer surface which is included in the capacitor region 30 " act as a dielectric in the capacitor to be produced.

Since silicon nitride has a higher dielectric number (approx. 2 times) than silica, capacitors with a higher capacitance per unit area are obtained by using nitride compared with capacitors made of silica as a dielectric. The thickness of the nitride layer is adjusted so that the capacitor has a capacitance of approx. 2.4 fF / umz. This corresponds to a nitride layer 34 deposited by LPCVD with a thickness of about 27 nm. ii) The part of the nitride layer 34 which is deposited on top of the remaining oxide layer 24 in the active region 36 ', where the base connection to the bipolar NPN transistor to be produced is later to be formed, gives an increased thickness of its insulating dielectric and consequently a lower parasitic capacitance for the collector-base junction.

After applying the nitride layer 34, still see fi g. 21a and 21b, the disk is patterned by lithographic means, by first applying a photoresist layer 35 and then making appropriately located apertures therein for denining a base region 36 'of the NPN transistor to be made, and by apertures 37 ", 37. "'for the collector and emitter of the lateral PNP transistor to be manufactured, and for the definition of openings for connections for substrate contacts 37' in the P-wires. The aperture for defining the base region 36 'of the NPN transistor to be manufactured is located so that it lies over areas where there is no field oxide layer 18, and so that the edges of the aperture are not too small a distance from the area zones. of the field oxide layer 18. Openings for collector and ernitter in the lateral PNP transistor to be produced are likewise placed over areas where no field oxide layer 18 fi mis. However, the edges of the openings are placed next to the edges of the field oxide layer 18, see fi g. 21b. These openings also lie over N-areas 13 and thus over bottom diffusions 5 of type N +. The openings in the photoresist layer 35 for connections for substrate contacts, on the other hand, overlie P-areas 14 and then over bottom diffusions 8 of type P-. Thereafter, an etching is performed in the openings in the photoresist layer 35, preferably by dry etching. This dry etching step is performed sequentially, with the nitride layer 34 being removed first. Thereafter, the underlying oxide layer 24 is etched away, the etching process is graded, when the silicon surface is exposed. This patterning step, which is specific to the embodiment described here, reduces for the NPN transistor to be manufactured the surface area of the base region, which would otherwise have been determined by apertures in the field oxide layer but which is here determined by the edges of apertures in the photoresist layer 35. Furthermore, it is avoided that the base region to be produced in the NPN transistor is brought into close contact with the edges of the field oxide layer, where an increased concentration of dopants prevails due to "piles up" of dopants from The N-wells (N-wells) 13, as mentioned above. The pattern for making apertures in the nitride layer 34 and in the oxide layer 24 between areas of the field oxide layer 18 is made in order to reduce the capacitance between collector and base of the NPN transistor to be produced, by obtaining an inverted aperture. , and the remaining portions of the nitride layer are used to form a dielectric layer for the capacitor to be produced. Furthermore, the same sampling step can be used to increase the distance between the emitter and the collector of the lateral PNP transistor to be produced. The advantage of this method is that the distance between the emitter and the collector in it is well defined at the same time as the emitter and collector openings can be made smaller, which reduces the capacitive connection between these electrodes. This distance would otherwise be defined by the field oxide ice strands 18, as shown in Fig. 21b.

The advantage of the method described above is that the dielectric of the capacitor, which consists of the nitride layer on top of the plug 32, which forms one electrode of the capacitor, is produced simultaneously with the layer defining the emitter-base region 36 'of the NPN transistor to be produced. that the parasite contribution from the capacitor between base and base for this NPN transistor is reduced and that the emitter base region 36 is well defined in the NPN transistor to be produced, as well as that the distance between emitter and collector regions in the lateral PNP transistor to be produced is produced, also becomes well-determined, by being defined by lithographic means.

After etching the nitride layer 34 and the oxide layer 24 to define base regions 36 'zs for the NPN transistor to be produced, collector windows 37 ", 37"' for the lateral PNP transistor to be produced, and substrate connections 37 ", the photoresist layer 35 is removed. in a known manner. In the preferred embodiment, a thin layer of amorphous silicon 38 with a thickness of about 200 nm over the surface of the disk is then deposited, preferably by means of LPCVD technology, see Fig. 22. This silicon layer 38, which later in the process will form the base conductor to the NPN transistor to be manufactured, the top electrode of the capacitor to be manufactured, the conductor of the emitter and collector of the lateral PNP transistor to be manufactured, and the connection to the substrate contacts, may also consist of microcrystalline silicon or polysilicon .

In a subsequent ion implantation, which is illustrated by the arrows in Fig. 22, the amorphous silicon layer 38 is doped to become of heavily doped P-type. In the preferred embodiment as, this ion implantation step is performed, by preferably implanting BFZ with an energy of about 50 keV and a dose of about 2-1015 ions / cm 2. The energy at implantation is so adapted that the implanted boron atoms do not reach down to the surface of the epitaxial layer 9. Dose and energy may vary slightly depending on the thickness of the just deposited amorphous silicon layer 38 and on its nature. Other boron compounds and / or atomic boron can also be used in the ion implantation in this silicon layer. In this case, energy and dose must be adjusted to appropriate values.

A silicon oxide layer 39 with a thickness of typically 150 nm is deposited on top of the amorphous silicon layer 38. In the preferred embodiment, this oxide layer 39 is deposited by means of PECVD technology, but also other types of such so-called low-temperature oxides, deposited by means of any suitable CVD technology, eg LTO, can be used. In the preferred embodiment, the temperature upon deposition of the oxide layer 39 is kept so low that the amorphous silicon layer 38 is not caused to recrystallize. The advantages of using a combination of amorphous silicon, which is implanted with BFZ, under a protective layer 39 of silicon oxide, deposited with PECVD technology, w in the manufacture of base conductors for NPN transistors are described in Swedish patent application 9504150-5.

After depositing the silicon oxide layer 39, the surface of the disk is coated with a photoresist layer 40 and patterned by lithographic means, defining an area shown at 40 ', which is included in the capacitor region 30 "and is intended for an upper electrode belonging to the plate capacitor 15. which is located on top of the nitride dielectric 34 which is present in the entire region 30 ", and which region 40" is thus covered by the photoresist layer 40. Further, areas of the photoresist layer 40 cover surfaces around the incipient emitter base region 36 'of the NPN transistor to be manufactured, and further it covers areas 37 "" for emitter electrodes and areas 37 "for collector electrodes for the lateral PNP transistor to be manufactured, and areas 37 'for substrate contact terminals, see fi g. 23a and 23b. With the now applied and patterned photoresist layer 40 as a mask, the silica layer 39 and the underlying layer 38 of amorphous silicon are etched away in the openings in the resist layer. The etching, which is stopped when the silicon nitride layer 34 is completely exposed in the openings in the photoresist layer 40, where this nitride layer is present as on top of the field oxide and in the area 40 "where connection is to be made via zs the buried diffusion to the lower electrode in that capacitor, The result is reproduced by means of sequential dry etching in a multi-chamber system ("cluster system"). 40 nm of the substrate in the opening of the incipient emitter-base area 36 'is consumed during the final stage ao of the etching process (which is a so-called over-etching step).

After the etching is completed, an additional doping of the area which is to become the collector of the NPN transistor is carried out, in order to minimize so-called "base widening" and thereby improve the high frequency properties of the transistor, see the article by MC Wilson, "The application of a selective implanted collector to an advanced bipolar process ", ESSDERC'90, Nottingham, September 1990. In the preferred method, this doping takes place by means of ion implantation of phosphorus, as indicated by the arrows in fi g. 23a and 23b, and preferably in two steps. During the first step, phosphorus is implanted with an energy of about 200 keV and with a dose of about 1-1012 ions / cm2. During the second stage, phosphorus is implanted with an energy of 460 keV and a dose of about 1.8-1O12 ions / cm2. The relative order between these two implantation steps may vary. A minor adjustment of the respective implantation dose and energy during actual production may always be necessary to compensate for minor process variations, eg minor changes in the thickness of the epitaxial layer 9, etc. It should be noted that the doping is aligned or oriented (""). aligned ") with the opening of the incipient emitter base region 36 'and that the photoresist last layer 40 remains on the disk during implantation to prevent the dopant (in the preferred case phosphorus) from penetrating the epitaxial layer 9 at an unintended location. Therefore, after completed production steps, no increased collector doping will be found under the so-called extrinsic base, ie the area along the edge of the area 36 ”, where the amorphous silicon layer 38 of type P + is in contact with the surface of the epitaxial silicon layer 9. As a result, a low capacitance between collector and base can be maintained in the NPN transistor to be produced.

After completion of implantation, the photoresist layer 40 is removed in a known manner, whereupon a thin silica layer 42, with a thickness of about 20 nm, is deposited over the surface of the disk, so that it specifically covers the openings 36 'at the incipient emitter base area, see fi g. In the preferred ice embodiment, this oxide layer 42 is preferably deposited by thermal oxidation in a wet atmosphere at 800 ° C. In this oxidation step, the previously applied oxide layer 39, which has been deposited at low temperature by means of, for example, PECVD technology as above, will be densified at the same time as silica layer 41 is formed on the vertical free side walls or edge surfaces of the amorphous silicon layer 38. , which in itself comprises a heat treatment, so the amorphous silicon layer 38 is converted to polycrystalline silicon (polysilicon), ie it crystallizes partially, at the same time as the implant should be redistributed. The previously amorphous silicon layer 38 will hereinafter be referred to as a polysilicon layer of type P +. The result is illustrated by fi g. 24.

After preparation of the silica layer 42 as above, boron is preferably implanted in the disk, as illustrated by the arrows in fi g. 24, to form the intrinsic base region or zs the effective base region of the NPN transistor to be fabricated. In the preferred embodiment, boron is implanted with an energy of about 10 keV and with a dose of about 7-1013 ions / cm 2. A minor change in thickness of the top layer of oxide 42 results in a corresponding adjustment of energy and / or dose. The implantation penetrates only through the various applied oxide, silicon and nitride layers just where only the silicon oxide layer 42 lies directly on top of the upper surface of the epitaxial layer 9, i.e. in the incipient ernitter-basonium council 36 ”.

After the so-called basic implantation described above, the disk is thermally oxidized, preferably in a wet atmosphere at 800 ° C for about 20 minutes, which further reduces the surface concentration of boron atoms. In the preferred embodiment, the wafer is then coated conformally with an approximately 180 nm thick nitride layer 44 using LPCVD technology, see fi g. 25a. In the preferred embodiment, this nitride layer is etched by means of a special anisotropic dryer, until in a known manner an edge strand (so-called "spacer") of silicon nitride remains, where large steps are present in the silicon nitride layer 44, as in the opening of the starting emitter base region 36 'of the NPN transistor to be manufactured. In this etching step, not only the nitride layer 44 is etched away but also the previously applied nitride layer 34 at the areas where it is directly below the last applied nitride layer 44. The etching is stopped when the surface of the areas of the field oxide layer 18 and of the silica layer 42 has been exposed. The opening in the incipient emitter-base region 36 °, which is formed by this etching of the nitride layer 44, will constitute the so-called emitter opening 36 ".

Upon completion of production, the sockets in the manufactured NPN transistor will be separated from the polysilicon layer 38, which is of type P +, by the nitride edge strands 45 and by the oxide layer 41 at the edge surfaces of the polysilicon layer. The etching also exposes the silicon surface in the area 40 ", where a connection to the lower electrode is to be formed in the capacitor to be produced. The silicon surface is also exposed in areas 45 ', where base connections are to be formed to the lateral PNP transistor, which to be prepared, see 23 g. 23b. of RIE ("Reactive Ion Etch", reactive ion etching) in a plasma of Ar / CHF3 / CF4 followed by a mild isotropic silicon etching in situ in an atmosphere of Ar / NF3 to remove impurities and radiation damage 1s from the previous RIE step This etching step in Ar / NF3 removes a thickness of about 150 - 200 Å of silicon from the free surface of the epitaxial layer 9 (the intrinsic base) in the emitter opening 36 ". Since this etching affects the intrinsic base coil, the etching depth may vary slightly depending on the requirement for current gain (Hfe) in the transistor to be produced. zo In an alternative embodiment, which is illustrated in fi g. 25b, where a so-called "disposable spacer" is used, the silicon nitride layer 44 is replaced by a slightly thinner nitride layer 144, with a thickness of about 50 mn. This silicon nitride layer 144 is also deposited confonantly over the disk by means of preferably LPCVD technology. On top of this nitride layer, an approximately 150 nm thick silica layer 148 is deposited. The oxide layer 148 is characterized in that it is produced at a low temperature, for example at about 400 ° C, and thereby does not consist of stoichiometrically composed silica but is considerably more "porous". The latter property is used in the following cases.

After deposition, the oxide layer 148 and the underlying silicon nitride layer 144 are etched by anisotropic dry etching. In the case described here, the ether etching is performed as a three-step RIE process, in which the oxide layer 148 is first removed in a gas mixture of Ar, CHF 3 and CF 4. The etching is stopped when the nitride layer 144 has been exposed on flat, horizontal surfaces, for example at nitride surfaces on top of the field oxide areas 18, whereby edge strands of the porous oxide layer 148 remain on vertical surfaces. Then, in step two, the nitride layer 144 is etched away with the resulting ss oxide edge strands as a mask, ie in principle on all horizontal surfaces. The etching process is stopped when the surface of the field oxide areas 18 and the silica layer 42 in the emitter orifice have been exposed. Analogously to the preferred embodiment, in step three, the remaining oxide layer 42 in the emitter orifice is removed by means of RIE, followed by a mild silicon etching in Ar / NF 3 to remove surface contaminants and radiation damage. Upon completion of dry etching, the emitter orifice will be surrounded by a composite edge strand ("composite spacer") consisting of "porous" oxide / nitride / oxide 148, 144, 39. A brief exposure of the composite edge strand in HF (hydrochloric acid) ) removes the outermost "porous" oxide without appreciably attacking areas of thermal oxide. Dissolution of the "porous" oxide is advantageously carried out in HF steam in the appropriate equipment (eg "FSI / Excalibur"), but alternatively an HF-based wet chemical bath can also be used. The resulting edge strings after the etching will not have a triangular cross-section, but their cross-section is more reminiscent of an "L", see fi g. 25b.

The advantage of the technique just described with so-called "disposable spacer" is that the opening in the polysilicon layer 38 of type P + is not compressed. This facilitates subsequent deposition and diffusion of the dopant from the polysilicon layer 46 of type N +, ie the so-called "poly-plug effect" is suppressed.

I fi g. 25c below shows a cross section of an NPN transistor manufactured according to it in connection with fi g. 25a, ie with nitride edge strands left in the emitter opening. I fi g. 25d shows the corresponding structure made using technology with "disposable spacer" ice as above, see also fi g. 25b. The cross-sectional images are taken with transmission electron microscopy, XTEM.

After exposing the single crystalline silicon surface in the emitter port 36 "and at the collector plug 31 of the NPN transistor to be manufactured, and at the contact surface in the region of 40" to the lower capacitor electrode 32 and at the base connection to the lateral PNP transistor, which to be produced, an approximately 250 nm thick polysilicon layer 46 is deposited using LPCVD technology, see fi g. 26a and 26c. The polysilicon layer 46 is then doped by means of preferably ion implantation of arsenic and / or phosphorus, which is illustrated by the dashed arrows in fi g. 26a and 26c. It should be noted that the polysilicon layer 46 is displayed both before (dashed line) and after (solid line) final pattern, which is described below. In the preferred embodiment, this ion implantation takes place in three working steps before a patterning of the polysilicon layer just applied below, described in the first step. .

The disc is then patterned by lithographic means by applying a photoresist layer 48 and receiving apertures therein, leaving the photoresist layer 48 on portions of the disc, so that high resistance resistors, so-called RHI, will later be defined. With this photoresist layer 48 as a mask, another arsenic implant is performed, but this time with a dose of about 12-1016 ions / cm 2 and an energy of about 150 keV, the situation being illustrated in fi g. 26b. It should be noted that all portions of the disc, with the exception of areas of high resistance RHI, receive both implants. es The disc is then patterned once more on a lithographic path, defining areas for low-resistance resistors RLO. In the latter case, a photoresist layer applied to this patterning step, not shown, will remain on all portions of the disk surface with the exception of apertures for low resistivity resistors RLO. With this photoresist layer as a mask, phosphorus is then implanted with an energy of about 25 keV and a dose of about 4-1015 ions / cm 2. The process is not shown in the figures, however, compare Fig. 26b. Upon completion of the entire manufacturing process described herein, the above-mentioned implantation procedure results in highly resistive resistors RH; with a surface resistance of about 500 Ohm / square and low-resistance resistor RLO with a surface resistance of about 100 Ohm / square was achieved. A minor adjustment of implantation dose and / or energy can of course be performed to compensate for other process variations.

After completion of varied doping of the polysilicon layer 46, this layer is patterned, as indicated above, in a conventional lithographic manner. In this case, contact areas are defined for emitter 49 'and collector 50' for the NPN transistor to be produced, contact area 51 'for lower electrode for the plate capacitor to be produced, see fi g. 26a, base connection 51 "to m the lateral PNP transistor to be manufactured, see fi g. 26b, and low-resistivity 52 'and high-resistivity 53' resistors, RHI and RLO, respectively, see fi g. 26b. Where the polysilicon bearing 46 has direct contact with the single crystalline silicon surface in the emitter orifice 49 ", this highly doped polysilicon layer will at a later stage of the manufacturing process serve as a doping source when driving the emitter into the intrinsic base region. With a photoresist layer patterned for this purpose as a mask, not shown in the figures, but the result of which can be seen in part in Figs. This etching is preferably performed by means of RIE in a plasma consisting of C12, HBr and O2. After the etching of the polysilicon layer 46, the photoresist layer is removed in a known manner.

Thereafter, the oxide layer 39 is etched away, which is located on top of the previously prepared zo polysilicon layer 38 of type P +. This etching, which is preferably performed by means of dry etching, can either be performed globally across the disk or preferably be performed, after the affected portions have been defined by lithographic means, as described below.

In the preferred embodiment, the disc is thus first patterned by lithographic means, apertures in an applied photoresist layer 52 being taken up over the polysilicon layer 38 and other areas, e.g. over areas of the later applied polysilicon layer 46, see fi g. 27a and 27b. Thereafter, the oxide layer 39 is etched away in the openings in the photoresist layer 52 by dry etching (RIE) in a plasma consisting of Ar, CHF3 and CF4. The etching is stopped when the polysilicon layer 38 has been exposed in the openings. The advantage of this method of non-global etching and instead a lithographic pattern before etching is that the field oxidone strands 18, which would otherwise also have been eroded in the dry etching step used, are protected by the photoresist layer 52 and thereby remain intact. A further advantage is that the oxide layer 39 can be left on the portions where silicide, see below, is not desired, for example at the area 52 'of the emitter of the lateral PNP transistor to be produced, see fi g. 27b. This provides better reproducibility of the process. The result after the oxide etching, according to the procedure just described, is illustrated by fi g. 27a as and 27b.

Upon completion of etching, the photoresist layer 52 is removed in a known manner. A thin oxide layer 56, about 30 nm thick, is then deposited over the surface of the disk, see fi g. 28a and 28b. In the preferred embodiment, this oxide deposition is performed by thermal decomposition of TEOS. However, the oxide layer can be deposited using other methods, such as LTO or PECVD. On top of the now applied oxide layer 56, an approximately 100 nm thick silicon nitride layer 58 is then deposited by means of preferably LPCVD technology. This nitride layer 58 is applied conformantly over the surface of the disc.

After this deposition of the nitride layer 58, the disk is heat treated at high temperature for recovery and activation of previously implanted dopants. In the preferred embodiment, this recovery is performed in two steps. First, the disk is heat-treated in an oven at 850 ° C for about 30 minutes in a gas mixture of oxygen and nitrogen, in order to distribute the dopants more evenly in implanted layers. The disk is then heat-treated again, in a nitrogen atmosphere at about 1075 ° C for about 16 seconds, in a so-called RTA equipment (RTA stands for "Rapid Thermal Annealing"). In the preferred embodiment, a so-called "Hot-liner" is used in the RTA equipment to control the temperature during this recovery step. The combination of drive temperature and duration of processing in the RTA equipment may vary slightly depending on the data required by the transistor to be produced. It should be noted that during this heat treatment process, silicon nitride layers and silicon oxide layers remain as protective layers over the disk to prevent diffusion of implanted dopants into the environment. is In this friendly treatment, the arsenic implanted in the upper polysilicon layer 46 of type N + will penetrate into the intrinsic base by diffusion and there form the emitter-base transition 61 ”. For the overall production process described here, the emitter depth is about 60 nm and the remaining thickness of the intrinsic base (below the emitter) is about 100 nm. The concentration of arsenic in the emitter orifice at the transition between the surface of the epitaxial monocrystalline silicon layer 9 and the polysilicon layer 49 'of type N + is typically about 4-1020 atoms / cm 3. The corresponding concentration of boron (in the intrinsic base) at the emitter-base junction is typically about 8-1017 atoms / cm3.

At the same time, the boron which has been implanted in the lower polysilicon layer 38 of type P + will, due to diffusion, penetrate and connect to the intrinsic base. For the total manufacturing process described, the extrinsic base depth is about 200 nm and the corresponding concentration of boron at the interface between this polysilicon layer 38 of type P + and the epitaxial monocrystalline silicon layer 9 is typically about 2-1019 atoms / cm 3. The resulting highly doped region 62 'of type P + is called extrinsic base. The substrate contacts 60 'are formed analogously by means of diffusion of boron from the polysilicon layer 38 of type P +, see fi g. 28a. In an analogous manner eo, emitter electrodes 62 "'and collector electrodes 62" are formed for the lateral PNP transistor to be produced, see fi g. 28b.

I fi g. 29 shows the profile measured by SIMS for dopants under the polysilicon emitter of type N +. The polysilicon thickness is marked by the shaded part to the left in fi g. 29. A certain broadening of the arsenic signal, originating from the emitter, has taken place during the analysis. Consequently, the rear arsenic edge will extend deeper into the absorbed drill signal (which marks the extent of the base) than is actually the case.

After driving, the disk is patterned by lithographic means, after which a protective layer 60 of photoresist will only remain over the resistor bodies of the resistors RHI and RLO, see fi g. 30. End portions of the resistors will be exposed. After the pattern of the photoresist layer 60, the silicon nitride layer 58 and the silicon oxide layer 56 are etched away in the surface portions not covered by the photoresist layer 60 by means of anisotropic dry etching, so that so-called spacers or edge strands 54 appear along the edge of the polysilicon layer 46 of type N +. . 28a.

In the event that the oxide layer 39 has been left on, for example, the nitrite of the lateral PNP transistor to be produced, in order to avoid silicide formation, this etching of oxide is stopped (after removal of the layer 56), before these portions have been exposed, see fi g. 28b. The process described herein for making such so-called silicon nitride spacers on top of a thin silicon oxide layer substantially follows the production process disclosed by U.S. Pat. U.S. Patent 4,740,484 to H. Norström et al. In the preferred embodiment, an anisotropic, i.e. direction-dependent, plasma etching process is used to remove the silicon nitride layer. The etching process, which preferably uses the gases SF6, HBr and O2, is stopped when all the silicon nitride on the horizontal field oxidizer means 18 of the disk has been removed. Since the silicon nitride layer 58 has been deposited with good conformity, i.e. with evenly thick coverage over the entire surface, after etching strands of silicon nitride (spacers) will be left along the sharp steps or ledges on the surface of the disc which have been provided by the patterned polysilicon layer 46. of type N +.

Thereafter, the thin silicon oxide layer 56 is etched away by means of RIE, whereby the spacers 54 get their final shape. This etching process, which preferably uses the gases Ar, CHF 3 and CF 4, is stopped when both surfaces of the polysilicon layer 46 of type N + and of the polysilicon layer 38 of type P + have been exposed. zo Thereafter, the photoresist layer 60 is removed in a known manner. The result is represented by fi g. 28a, 28b and 31. The latter fi clock is an enlargement of the area in which an NPN transistor is to be produced, after driving in the dopants at the rivets and base and after etching to produce edge strings. Av fi g. 31 shows that the extrinsic base wire, which is lithographically de they are fi initiated by the aperture in the silicon nitride layer 34 and the silicon oxide layer 24, is well separated zs from the nearest edge of the field oxidor region 18. This results, as previously pointed out in the description of fi g. 16, the capacitance between collector and base to be reduced in the N PN transistor to be manufactured.

After removal of the photoresist layer 60, if desired, the polysilicon layer 46 of type N + and the polysilicon layer 38 of type P + can be provided with a thin silicide layer to reduce the resistance of conductors to the different electrode regions of the components to be manufactured (these leads will be shunted by such a silicide layer). This silicide layer can consist of, for example, PtSi, CoSiz or T iSiz. In the preferred embodiment, titanium disilicide TiSiz is used, which is formed by means of so-called "self-aligning technique" on top of exposed silicon surfaces.

In such self-aligned silicidation ("SALICIDE"), see U.S. Pat. U.S. Patent 4,789,995 to Brighton et al. and 4,622,735 for Shibata, a thin metal layer 70 is deposited, in this case a layer of titanium with a thickness of about 50 nm, preferably by means of sputtering technique (so-called "sputtering") over the surface of the disc, see fi g. 32a and 32b. The metal layer 522 038 24 is then reacted for a short time (for about 20 seconds) with exposed silicon at an elevated temperature of about 715 ° C in a nitrogen atmosphere in an RTA equipment. In some cases, a mixture of nitrogen and ammonia can also be used. Then the titanium, which has not reacted with silicon (ie from the parts that lacked exposed silicon surface before the application of metal) is removed by means of wet chemical methods. This etching step, which selectively removes unreacted titanium, affects the titanium silicide itself only to a small extent. After the wet chemical etching, the board is heat-treated at about 875 ° C for about 30 seconds, so that a low-resistance form of titanium disilicide is formed. The silicide layer thus produced, which has an outer resistance of about 2 - 5 ohrn / square, will then only be applied to the previously exposed silicon surfaces of the board, ie be self-aligned with these surfaces.

After silicidation, a passivation layer 80 of silica is deposited, see fi g. 33. This oxide layer 80 may preferably be a TEOS-based oxide, which has been deposited either by thermal decomposition or by PECVD technology. The oxide layer 80, which will later be planarized with so-called Resist Etch Back (REB), is deposited to a thickness of about 1 μm. Then a photoresist layer, not shown in the figures, with a thickness also of about 1 μm (measured on larger flat portions) is applied over the surface of the disc. The resist layer is then heat treated for a few minutes at about 190 ° C. Due to the surface-leveling properties of the resistance, its upper surface will be relatively flat despite the underlying surface topography, which can be rather uneven. The wafer is then plasma etched for the purpose of removing this photoresist layer and also protruding or protruding portions of the silica passivation layer 80 at the same rate. In this way, as a final result, after complete removal of the photoresist layer, it is achieved that the surface of the passivation oxide layer 80 has a smoothed topography, ie that the surface becomes rather flat and horizontal. This planarization method (REB) is described in A.C. Adams, C.D. Capio, "Planar- ization phosphorous doped silicon dioxide", Journal of the Electrochem. Soc., Vol. 128, 251981, p. 423ff.

The planarized oxide layer 80 is then coated with an approximately 400 nm thick doped oxide layer 82. This oxide layer 80, which consists of TEOS-based oxide, is preferably doped with about 4% phosphorus for so-called gettering purposes (for bonding of slightly diffusing Na ions ). Other combinations of dopants are also possible, such as 3% boron and 6% phosphorus. On top of the doped ox-ao idle layer 82, an approximately 250 nm thick undoped TEOS oxide layer 84 is then deposited, preferably by means of PECVD technology. This oxide layer will later function as a so-called hardworm.

The oxide layers are then densified by heat treatment in nitrogen at 700 ° C for a period of about 40 minutes. Alternatively, an RTA process can be used at 875 ° for 20-30 s. This RT A process can also replace the previously performed heat treatment to produce low-resistance titanium disilicide.

In the preferred embodiment, the disk is then patterned in a lithographic manner, thereby deepening substrate contacts. These are obtained by first transferring the pattern in an applied photoresist layer 81 to the underlying oxide layer 84 (82, 80) by anisotropic plasma etching. Then the photoresist layer 81 is removed in a known manner and about 7 μm deep holes 85 are taken up in the substrate (9, 522 038 25 1) by means of dry etching. The method is analogous to that described for etching trenches 22 for insulation purposes. In the etching of the holes 85 for contacting the substrate, the uppermost oxide layer 84, the so-called hard mask, will be completely or partially consumed. The result after etching of substrate connections is shown in fi g. 33. s After the etching of the substrate connection holes 85, boron is implanted in the disk with a dose of about 3-1015 ions / cm 2 and an energy of about 30 keV, as illustrated by the arrows in fi g. 33. The implantation energy is so adapted that the boron atoms are blocked by the doped layer 82 of passivation oxide and only manage to penetrate into the silicon substrate by first passing through the openings of the holes 85. After implantation, the wafer is typically treated at typically 875 ° C in nitrogen 10 for about 30 seconds. The advantage of manufacturing and implementing the above-mentioned deep substrate contacts in the manufacture of IC circuits for radio frequency use fi mis described in the international patent application PCT / SE97 / 00487.

After implantation and heat treatment, the disc is re-coated with a photoresist layer and this time contact holes are patterned into active and passive components, see fi g. 34a and 34b. Contact holes 86, 87 are then received in the laminated oxide layer 82, 80 by means of anisotropic plasma etching. Due to different depths of the contact heel, due to the underlying topography, fixed lengths of etching are used. Some connection layers will thereby be exposed to stronger over-etching than others due to topographical differences. After this etching of contact holes, the photoresist layer is removed in a known manner. In this position, both contact holes 86 zo for substrates and contact holes 87 for connections of passive and active components will be defined. The result is illustrated by fi g. 34a and 34b.

The wafer is then coated by sputtering with a two-layer structure (sandwich structure) consisting of at least about 100 nm layer of Ti and above it a layer of T iN with a thickness of about 50 mn. In the preferred embodiment, the Ti layer is deposited by means of a sputtering ring in a so-called "Ion Metal Plasma" equipment (IMP equipment), such as a "Vectra Source" (trademark of the company Applied Materials) in order to better coat the bottom of the deep substrate contact holes 85. The TiN layer is deposited by reactive sputtering (in an Ar / Nz gas mixture). This can be done with the help of so-called collimation technology (coherent sputtering).

Deposition of the TiN layer can also take place by reactive sputtering with IMP-Vectra Source so analogous to the Ti layer.

After depositing the contact metal layer of Ti and the layer of metal nitride TiN, which forms a barrier layer of the underlying metal layer, the wafer is heat treated at elevated temperature, reacting the Ti layer with underlying silicon, where free silicon surfaces are present (ie in the substrate contact holes), or with titanium silicide layer (ie in the contact holes for components). In the preferred embodiment, this heat treatment takes place in an oven in a mixture of Nz / Hz at typically about 600 ° C for about 1/2 hour. Alternatively, heat treatment can be performed in an RTA equipment at a higher temperature and for a shorter time in, for example, an atmosphere of NZ or ammonia. This can also be used to reinforce the barrier in the deep substrate contacts, so that the implanted boron atoms diffuse into the substrate material. Thereafter, an approximately 1 μm thick tungsten layer is deposited by means of CVD technology. This deposition, which has good configuration, is performed over the entire surface of the disc. In this case, all contact holes will be completely (conformally) filled with tungsten. In direct connection with the deposition of tungsten, a re-etching step takes place, which aims to remove all tungsten on the flat, ie horizontal, parts of the disc. The etching process is stopped when the surface of the TiN layer has been exposed.

As a result, tungsten will be left in the contact holes and form so-called contact plugs.

Then a first conductor layer consisting of approx. 50 nm TiN (deposited in the same way as above) is deposited covered with an approx. 600 nm thick layer of aluminum. The aluminum layer, which is deposited by sputtering, preferably contains 0.5 - 2.0% copper in order to suppress electromigration. The constituent layer thicknesses of these metal layers may vary slightly depending on the intended application. A thin layer with a thickness typically about 50 nm of TiN is deposited on top of the aluminum layer by means of reactive sputtering to facilitate subsequent patterning and suppress so-called "hillocking". The metal layer structure consisting of Ti / TiN / Al-Cu / TiN is then patterned by lithographic means, after which connection between mutual components is de-ionized by dry etching.

More metal layers can be added to the process, by depositing a passivation layer on top of the first connecting layer, whereupon via connections are defined by means of lithographic and dry etching. Then a two-layer structure of Ti / TiN is deposited by means of sputtering as above, whereupon the via openings are plugged with tungsten according to the method described above. A second metal layer structure consisting of a laminate of TiN / Al-Cu / TiN is then deposited by sputtering. The connection layer is then fi niered by means of lithography fi and dry etching. The sequence is repeated in the event that förb your connection layers are desired. The thickness of the Al-Cu layer used can vary from a few hundred nm up to a couple of μm depending on the complexity of the metal system and the circuit application. A metal system of the fl-bearing type with relatively thick conductor layers of, for example, Al-Cu can be advantageous in the event that flat coils are to be integrated on the circuit. A manufacturing method which uses fl your parallel-connected metal layers on top of a substrate slit by means of trenches in the production of flat coils for RF-IC applications is described in international patent application PCT / SE97 / 00954. This previously known procedure can be performed in the process described above. ao The end result, after fl your layers of metal have been added to the process, is shown by fi g. 35. Far left in fl g. 35 shows a cross section of the manufactured plate capacitor (referred to as "CapDn"). The electrodes for this consist of an underlying monocrystalline silicon layer doped to N + and a polysilicon layer of type P + lying above a nitride dielectric.

Just to the right of the capacitor is a lateral PNP transistor, which uses polysilicon of the A type P + to form an emitter and collector. The base connection consists of the plug diffusion of type N + from the surface in series with the bottom diffusion of type N +. The far right then shows a cross section of the manufactured NPN transistor and a resistor made of polysilicon of type N +. It should be noted that all components located in silicon substrates are mutually insulated by means of deep trenches. The deep, tungsten-filled substrate contacts in the holes 522 058 27 85 and / or the substrate connections driven from P + polysilicon are conveniently placed between the insulation trenches 22, which surround each component row, for the best possible electrical disconnection.

Av fi g. It can also be seen that an additional capacitor (CapMIM), in addition to the one already described (CapDn), has been integrated between the upper metal layers. The manufacturing process for the realization of this metal-metal capacitor (CapMIM), which uses PECVD nitride as a dielectric, has been adapted to the use of tungsten-plugged wires. The advantage of the manner in which the production of this latter capacitor is incorporated into the overall manufacturing process is described in Swedish patent application 9701618-2. m I fi g. 36 shows an electron microscope image of the final fabricated circuit in which deep tungsten-filled substrate contacts, a polysilicon resistor, and a trench-isolated N PN transistor are visible.

In the top view in fi g. 37 shows the extent of the various components in the horizontal direction, along the surface of the disc. The NPN transistor extends in depth, perpendicular to the plane of the paper in the cross-sectional views. The lateral PNP transistor, on the other hand, has a square design with the socket lying in the center.

Claims (7)

522 038 o o | n a po 28 PATENTKRAV A capacitor at the surface of a substrate comprising - a dielectric layer disposed over a portion of the surface of a region of the substrate, said region having a first doping type doped to a first doping level, s - a conductive layer disposed over the dielectric layer to form of an electrode in the capacitor, an electrically conductive connection to an area below the dielectric layer from a surface of a part of the substrate which is not covered by the dielectric layer, characterized in that the dielectric layer lies over a buried , highly doped region 10 of the substrate doped to a second doping level substantially higher than the first doping level, to which region a high doping contact plug of the first doping type and doped to a third doping level substantially higher than the first doping level is arranged from a part of the surface of the substrate, which is not covered by the dielectric layer. Capacitor according to claim 1, characterized by a high doping electrode plug of the first doping type and doped to substantially the third doping level to form a lower electrode in the capacitor, which electrode plug extends from the underside of the dielectric layer to the buried, high-doped area. Capacitor according to any one of claims 1 to 2, characterized by the region of the substrate which is of the first doping type and is doped to the first doping level, so also comprises the surface of a part of the substrate from which the electrically conductive the connection is arranged. Capacitor according to one of Claims 1 to 3, characterized in that the dielectric layer is a silicon nitride layer. A method of manufacturing a capacitor at the surface of a substrate comprising zs - applying a dielectric layer over a portion of an area at the surface of the substrate, which area is with a first doping type doped to a first doping level, - a conductive layer applied over the dielectric layer to form an electrode in the capacitor and - an electrically conductive connection is provided with an area below the dielectric layer ao from a surface of a part of the area of the substrate which is not covered by the dielectric layer, characterized in that before applying the dielectric layer to the surface of the substrate, a buried, highly doped area doped with the first type of doping is prepared to a second doping level substantially higher than the first doping level, which buried highly doped area is placed at a distance from the surface of the substrate and below the surface where the dielectric layer is to be applied, after which a contact plug with high doping is doped with the first doping type to a third doping level substantially higher than the first doping level is produced from a surface of a part of the substrate, where the dielectric layer is not to be applied. A method according to claim 5, characterized in that prior to the application of the dielectric layer, a high doping electrode plug doped with the first doping type is produced to substantially the third doping level to form a lower electrode in the capacitor, which electrode plug extends from the surface of a part of the substrate, over which the dielectric layer is to be applied, to the buried, highly doped area. 7. A method according to any one of claims 5 to 6, characterized in that upon application of the dielectric layer it is applied as a silicon nitride layer.