SE521704C2 - Method for arranging coupling between different layers of a circuit board and circuit board - Google Patents

Method for arranging coupling between different layers of a circuit board and circuit board

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Publication number
SE521704C2
SE521704C2 SE9903923A SE9903923A SE521704C2 SE 521704 C2 SE521704 C2 SE 521704C2 SE 9903923 A SE9903923 A SE 9903923A SE 9903923 A SE9903923 A SE 9903923A SE 521704 C2 SE521704 C2 SE 521704C2
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SE
Sweden
Prior art keywords
circuit board
layer
extension
layers
coupling element
Prior art date
Application number
SE9903923A
Other languages
Swedish (sv)
Other versions
SE9903923L (en
SE9903923D0 (en
Inventor
Leif Bergstedt
Per Ligander
Original Assignee
Ericsson Telefon Ab L M
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Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Priority to SE9903923A priority Critical patent/SE521704C2/en
Publication of SE9903923D0 publication Critical patent/SE9903923D0/en
Priority to AU13212/01A priority patent/AU1321201A/en
Priority to PCT/SE2000/002103 priority patent/WO2001031983A1/en
Publication of SE9903923L publication Critical patent/SE9903923L/en
Publication of SE521704C2 publication Critical patent/SE521704C2/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Multi-Conductor Connections (AREA)

Abstract

The present invention relates to a method of arranging connection between different layers (14, 14'', 17, 17'', 19, 19'') of a circuit board (10, 10'') provided with at least one electric component (12, 12''), having connector elements (13, 13'') at least partly extending from a first covering layer (14, 14'', 20''), at least partly covering said components. The method comprises the steps of depositing an amount of a conductive material on at least one connector element (13, 13'') for producing an extension (16, 16', 16'', 16''') of said connector element (13, 13'') before arranging a possible second covering layer (17, 17'').

Description

20 25 30 . . - . .e 521 704 2 ledningsskiktet, i vilken den första ledningen är i huvudsak plan på kontakthålet och arean av genomföringshålet är mindre än den för kontakthålet. 20 25 30. . -. .e 521 704 2 the conductor layer, in which the first conduit is substantially flat on the contact hole and the area of the lead-through hole is smaller than that of the contact hole.

WO 9 804 107 beskriver en metod för att tillverka förbindelser längs z-axeln mellan intilliggande kretsskikt med hjälp av elektriskt ledande spår i kretsar med flera skikt, innefattande att koppla ett ledande organ av ett deformerbart material till ett skikt i ett kretskort och deponera ett vidhäftande skikt över ett närliggande kretskortsskikt. De närliggande kretskortsskikten inrättas i förhållande till varandra, med det ledande organet i huvudsak i linje med de ledande spåren i de närliggande kretsskikten, och kretsskikten förs samman med hjälp av tryck på ett sådant sätt att det ledande organet tränger igenom det vidhäftande skiktet och deformerar detsamma tills det ”spricker”.WO 9 804 107 describes a method for making connections along the z-axis between adjacent circuit layers by means of electrically conductive grooves in circuits with fl your layers, comprising coupling a conductive member of a deformable material to a layer in a circuit board and depositing an adhesive layer over a nearby circuit board layer. The adjacent circuit board layers are aligned with each other, with the conductive member substantially aligned with the conductive grooves in the adjacent circuit layers, and the circuit layers are brought together by pressure in such a way that the conductive member penetrates the adhesive layer and deforms the same. until it "cracks".

Sprickningen exponerar fräscht (icke oxiderat) material som kontaktar ett ledande spår, och sammanfo gar kretsskikten och skapar elektrisk koppling med låg resistans.The crack exposes fresh (non-oxidized) material that contacts a conductive track, joining the circuit layers and creating a low-resistance electrical connection.

Häftmassan begränsar expansion av det deformerbara ledande organet, och reducerar potentiella kontakter med intilliggande ledande organ.The adhesive mass limits the expansion of the deformable conductive member, and reduces potential contacts with adjacent conductive members.

Sammanfattning Ett av ändamålen med den föreliggande uppfinningen är att minska eller eliminera ”fanout” runt kopplingarna till en komponent med kompakta kopplingstenninaler eller pitch, dvs. avgränsning mellan kopplingspunkterna.Summary One of the objects of the present invention is to reduce or eliminate "fanout" around the couplings to a component with compact coupling terminals or pitch, i.e. delimitation between the connection points.

Dessutom tillhandahåller den föreliggande uppfinningen kortare ledningsvägar, till exempel genom att minska antalet genomföringshål mellan komponenternas kopplingar, vilket ger upphov till mindre förluster och följaktligen till bättre prestanda.In addition, the present invention provides shorter lead paths, for example by reducing the number of lead-through holes between the couplings of the components, which gives rise to less losses and consequently to better performance.

Därför innefattar metoden för att ordna koppling mellan de olika skikten i ett kretskort försett med elektriska komponenter, med kopplingselement som åtminstone delvis sticker ut från det första täckande skiktet, att deponera en viss mängd av ett ledande material på åtminstone ett kopplingselement för att åstadkomma en förlängning av nämnda kopplingselement innan ett eventuellt andra täckande skikt ordnas. .ni i. 10 15 20 25 30 521 704 -, u. 3 Företrädesvis är nämnda kopplingselement en utbuktning. I ett utförande är nämnda täckande skikt ett dielektriskt skikt eller ett skikt av lack. Helst tillhandahålles nämnda förlängning genom plätering och genom toppeffekt.Therefore, the method of arranging coupling between the various layers of a circuit board provided with electrical components, with coupling elements protruding at least partially from the first covering layer, comprises depositing a certain amount of a conductive material on at least one coupling element to provide an extension. of said coupling element before a possible second covering layer is arranged. .ni i. 10 15 20 25 30 521 704 -, u. 3 Preferably, said coupling element is a bulge. In one embodiment, said covering layer is a dielectric layer or a layer of lacquer. Preferably, said elongation is provided by plating and by peak power.

Företrädesvis täcker nämnda andra skikt nämnda förlängning åtminstone delvis.Preferably, said second layer covers said elongation at least in part.

Nämnda andra skikt och nämnda åtminstone delvis täckta förlängning är försedda med ytterligare deponering av metall så att en ny förlängning bildas. Dessutom är nämnda första och andra skikt försedda med ledande mönster.Said second layer and said at least partially covered extension are provided with further deposition of metal so that a new extension is formed. In addition, said first and second layers are provided with conductive patterns.

I ett utförande är nämnda elektriskt komponent inbäddad i kretskortet, medan nämnda elektriska komponent i ett annat utförande är monterad på ytan av kretskortet med kopplingsterminaler, och nämnda elektriska komponent placeras i mottagande genomföringar innan den stöttas och vänds upp och ner för att förses med nämnda ledande material.In one embodiment, said electrical component is embedded in the circuit board, while in another embodiment said electrical component is mounted on the surface of the circuit board with connection terminals, and said electrical component is placed in receiving bushings before being supported and turned upside down to be provided with said conductive material.

Uppfinningen hänvisar även till ett kretskort försett med åtminstone en elektrisk komponent och som har förbindelse mellan olika skikt, där nämnda komponenter har kopplingselement som åtminstone delvis sticker ut från ett första täckande skikt. Det innefattar dessutom kopplingar mellan nämnda skikt innefattande en förlängning av nämnda kopplingselement, där nämnda förlängning bildas genom att deponera en viss mängd ledande material på åtminstone ett kopplingselement.The invention also refers to a circuit board provided with at least one electrical component and which has a connection between different layers, said components having coupling elements which at least partially protrude from a first covering layer. It further comprises couplings between said layers comprising an extension of said coupling element, wherein said extension is formed by depositing a certain amount of conductive material on at least one coupling element.

Kortfattad beskrivning av ritningarna I det följande kommer uppfinningen att beskrivas på ett icke begränsande sätt med hänvisning till de medföljande ritningarna i vilka: Fig. l är en schematisk vy från ovan av ett kretskort som framställts i enlighet med den föreliggande uppfinningen, Fig. 2-4 är tvärsnitt längs linjen A - A i Pig. l, vilka schematiskt illustrerar olika steg i framställningen av ett kretskort i enlighet med uppfinningen, och l0 l5 20 25 30 sß nu 521 704 .en »u 4 Fi g. 5 är ett schematiskt tvärsnitt av ett annat utförande av ett kretskort som framställts i enlighet med uppfinningen.Brief Description of the Drawings In the following, the invention will be described in a non-limiting manner with reference to the accompanying drawings in which: Fig. 1 is a schematic top view of a circuit board made in accordance with the present invention, Fig. 2- 4 is a cross-section along the line A - A in Fig. 1, which schematically illustrate various steps in the manufacture of a circuit board in accordance with the invention, and now Figs. 521 704. in accordance with the invention.

Detaljerad beskrivning av utförandena Den föreliggande uppfinningen hänför sig i första hand, men inte enbart, till inbäddade komponenter i ett kretskort som har en substratstruktur i flera skikt. Fi g. l ~ 4 illustrerar ett kretskort 10, som innefattar ett substrat 20 inklusive håligheter ll i vilka elektriska komponenter 12 är ordnade. De elektriska komponenterna kan vara aktiva eller passiva kretsar, såsom uppsättningar av IC kondensatorer eller resistorer etc. Kretskortet har flera skikt. Ledarna i olika skikt illustreras med olika linjetyper, vilka kommer att beskrivas närmare nedan.Detailed Description of the Embodiments The present invention relates primarily, but not exclusively, to embedded components in a circuit board having a multilayer substrate structure. Figs. 1 ~ 4 illustrate a circuit board 10 which includes a substrate 20 including cavities 11 in which electrical components 12 are arranged. The electrical components can be active or passive circuits, such as sets of IC capacitors or resistors, etc. The circuit board has several layers. The conductors in different layers are illustrated with different line types, which will be described in more detail below.

Komponenterna 12 är ordnade med sina kontaktelement, eller med det kontaktelement som tillhandahålls med utbuktningen 13 som sträcker sig ut från håligheten ll. Denna sida av kretskoitet, dvs. sidan med exponerade utbuktningar kommer att kallas för kopplingssidan. Företrädesvis fixeras en komponent inuti håligheten, till exempel med hjälp av ett vidhäftande medel.The components 12 are arranged with their contact elements, or with the contact element provided with the bulge 13 extending from the cavity 11. This side of the circuit, ie. the side with exposed bulges will be called the coupling side. Preferably, a component is fixed inside the cavity, for example by means of an adhesive.

Enligt Fig. 2 beläggs både komponenterna och substratet, efter montering av komponenterna l2 i hålighetema ll i ett första steg åtminstone med ett skikt 14, till exempel av ett dielektriskt material, vilket endast lämnar utbuktningarnas 13 toppar fria.According to Fig. 2, after mounting the components 12 in the cavities 11 in a first step, both the components and the substrate are coated at least with a layer 14, for example of a dielectric material, which only leaves the tops of the bulges 13 free.

Ett skikt l5 av ledande material, vilket bildar ett ledannönster, deponeras selektivt på det första dielektriska skiktet 14, till exempel genom plätering. Pläteringsmaterialet, vilket företrädesvis men inte nödvändigtvis är av koppar, appliceras selektivt i enlighet med ett kopplingsmönster. Pläteringen kan vara kemisk eller galvanisk plätering. Under pläteringsprocessen pläteras även de exponerade delama av utbuktningarna. På grund av sådan s.k. ”toppeffekt” tar utbuktningarna emot fler metallj oner per ytenhet, vilket leder till att mer metall deponeras och koncentreras på de icke-metalliska delama, till exempel det dielektriska skiktet. Deponeringen av metall på utbuktningarna bildar i huvudsak spetsiga punkter 16, så som visas i Fig. 3. 10 15 20 25 30 521 704 J, u.A layer 15 of conductive material, which forms a conductive pattern, is selectively deposited on the first dielectric layer 14, for example by plating. The plating material, which is preferably but not necessarily of copper, is selectively applied in accordance with a coupling pattern. The plating can be chemical or galvanic plating. During the plating process, the exposed parts of the bulges are also plated. Due to such so-called "Peak power" the bulges receive metall your metal ions per unit area, which leads to more metal being deposited and concentrated on the non-metallic parts, for example the dielectric layer. The deposition of metal on the bulges forms substantially pointed points 16, as shown in Fig. 3. 15 20 25 30 521 704 J, u.

Det är nu möjligt att bygga upp nya skikt ovanpå de på varandra följande skikten 14 och det ledande skiktet 15. Ett nytt skikt 17 av ett dielektriskt material eller ett skikt av lack kan appliceras i en sådan tjocklek att åtminstone en övre del av vissa eller samtliga av de spetsiga punktema 16 är fria. I Pig. 4 appliceras ett nytt skikt av ledande material 15' på samma sätt som nämns ovan. De i huvudsak spetsiga punktema 16 bildar nya i huvudsak spetsiga punkter l6', Med andra ord bildar varje utbuktning 13 genom bildning av i huvudsak spetsiga ledare 16/ 16” ett kopplingselement längs kretskortets z- axel, och därmed är borrning eller etsning av de hål som normalt används onödig. l enlighet med Fig. 3 är det även möjligt att ordna ytterligare kopplingselement 18, spetsiga eller trubbi ga, kopplade till ett ledarskikt, vilka element genom deponering av pläteringsmaterial kan användas som ytterligare kopplingselement i z-axelns riktning.It is now possible to build up new layers on top of the successive layers 14 and the conductive layer 15. A new layer 17 of a dielectric material or a layer of lacquer can be applied in such a thickness that at least an upper part of some or all of the pointed points 16 are free. In Pig. 4, a new layer of conductive material 15 'is applied in the same manner as mentioned above. The substantially pointed points 16 form new substantially pointed points 16 '. In other words, each bulge 13 by forming substantially pointed conductors 16/16 "forms a coupling element along the z-axis of the circuit board, and thus is drilling or etching the holes. which is normally used unnecessarily. In accordance with Fig. 3, it is also possible to arrange additional coupling elements 18, pointed or blunt, coupled to a conductor layer, which elements can be used as deposition of plating material in the direction of the z-axis by depositing plating material.

Det utförande som visas i Fig. 5 illustrerar ett kretskort (PCB) 10” av konventionell typ, innefattande ett substrat 20”. Substratet är ordnat med hål 21” för att ta emot kopplingsterminalema 13” i komponenterna 12” ”. l detta fall är PCB: t även uppbyggt genom applicering av flera skikt av ledare 15”, l5°” och skikt av dielektriskt material / lack 14”, 17” och 19”. I detta fall är emellertid komponenterna monterade på sinai förväg utvalda platser, och PCB: t vänds sedan upp och ner medan komponenterna stöttas med en lämplig stödjande struktur. Sedan appliceras de ledande skikten 15” °, 15”' och de dielektriska skikten så som beskrivs ovan. På samma sätt bildas kopplingselementen l6”, 16”', 18” och 18” i z-riktning när ledarrnönstren appliceras.The embodiment shown in Fig. 5 illustrates a circuit board (PCB) 10 "of conventional type, comprising a substrate 20". The substrate is arranged with holes 21 "to receive the switching terminals 13" in the components 12 "". In this case, the PCB is also constructed by applying fl your layers of conductors 15 ", l5 °" and layers of dielectric material / varnish 14 ", 17" and 19 ". In this case, however, the components are mounted in their pre-selected locations, and the PCB is then turned upside down while the components are supported with a suitable supporting structure. Then the conductive layers 15 "°, 15" 'and the dielectric layers are applied as described above. In the same way, the coupling elements 16 ", 16" ', 18 "and 18" are formed in the z-direction when the conductor patterns are applied.

Uppñnningen är inte begränsad till de visade utförandena, utan kan varieras på ett antal sätt utan att avvika från omfattningen av de bifogade patentkraven, och arrangemanget och metoden kan genomföras på olika sätt beroende på tillämpning, funktionella enheter, behov och krav etc. mv uThe invention is not limited to the embodiments shown, but can be varied in a number of ways without departing from the scope of the appended claims, and the arrangement and method may be carried out in various ways depending on application, functional units, needs and requirements, etc.

Claims (1)

1. 0 15 20 25 30 521 704 Patentkrav . Metod för att ordna koppling mellan olika skikt (14, 14”, 17, 17", 19, 19”) i ett kretskort (10, 10”) försett med åtminstone en elektrisk komponent (12, 12”) med kopplingselement (13, 13' ') som sticker ut åtminstone delvis från ett första täckande skikt (14, 14” ', 20”), som åtminstone delvis täcker nämnda komponenter, kännetecknad av, att deponera en viss mängd av ett ledande material på åtminstone ett kopplingselement (13, 13”) för att framställa en förlängning (16, l6', 16”, 16”') av nämnda kopplingselement (13, 13") innan ett eventuellt andra täckande skikt (17, 17”) ordnas. . Metod enligt krav 1, kännetecknad av, att nämnda kopplingselement är en utbuktning. . Metod enligt krav 1, kännetecknad av, att nämnda täckande skikt är ett dielektriskt skikt. . Metod enligt krav 1, kännetecknad av, att nämnda täckande skikt är ett skikt av lack. . Metod enligt vilket som helst av föregående krav, kännetecknad av, att nämnda förlängning tillhandahålls genom plätering. . Metod enligt vilket som helst av föregående krav, kännetecknad av, att nämnda förlängning skapas genom en toppeffekt. 10 15 20 25 30 10. ll. 12. 13. 521 704 7 Metod enligt vilket som helst av föregående krav, kännetecknad av, att nämnda andra skikt täcker nämnda förlängning åtminstone delvis. Metod enligt krav 7, kännetecknad av, att nämnda andra skikt och nämnda åtminstone delvis täckta förlängning förses med ytterligare deponering av metall så att en ny förlängning bildas. Metod enligt vilket som helst av föregående krav, kännetecknad av, att nämnda första och andra skikt förses med ett ledande mönster. Metod enligt vilket som helst av föregående krav, kännetecknad av, att nämnda elektriska komponent (12) är inbäddad i kretskortet. Metod enligt vilket som helst av krav 1 - 9, kännetecknad av, att nämnda elektriska komponent (12” ”) är ytmonterad på kretskortet med kopplingstenninaler. Metod enligt vilket som helst av krav 11, kännetecknad av att nämnda elektriska komponent placeras i mottagande genomföringar innan den stöttas och vänds upp och ner för att beläggas med nämnda ledande material. Kretskort (10, l0”) försedd med åtminstone en elektrisk komponent (12, 12” ') och som har förbindelse mellan olika skikt (14, 14”, 17, 17”, 19, l9”), där nämnda komponenter har kopplingselement (13, 13” ') som åtminstone delvis sticker ut från ett första täckande skikt (14, 14”, 20” '), kännetecknar av 521 704 8 att det dessutom innefattar kopplingar mellan nämnda skikt innefattande en förlängning (16, l6”, l6”, 16'”) av nämnda kopplingselement (13, l3”), där nämnda förlängning bildas genom deponering av en viss mängd ledande material på åtminstone ett kopplingselement (13, 13”).1. 0 15 20 25 30 521 704 Patent claims. Method for arranging connection between different layers (14, 14 ", 17, 17", 19, 19 ") in a circuit board (10, 10") provided with at least one electrical component (12, 12 ") with connection elements (13, 13 '') projecting at least partially from a first covering layer (14, 14 "', 20"), which at least partially covers said components, characterized in that a certain amount of a conductive material is deposited on at least one coupling element (13 , 13 ") to produce an extension (16, 16 ', 16", 16 "') of said coupling element (13, 13") before arranging a possible second covering layer (17, 17 "). . Method according to claim 1, characterized in that said coupling element is a bulge. . Method according to claim 1, characterized in that said covering layer is a dielectric layer. . Method according to claim 1, characterized in that said covering layer is a layer of lacquer. . Method according to any one of the preceding claims, characterized in that said extension is provided by plating. . Method according to any one of the preceding claims, characterized in that said elongation is created by a peak effect. 10 15 20 25 30 10. ll. Method according to any one of the preceding claims, characterized in that said second layer covers said elongation at least in part. Method according to claim 7, characterized in that said second layer and said at least partially covered extension are provided with further deposition of metal so that a new extension is formed. Method according to any one of the preceding claims, characterized in that said first and second layers are provided with a conductive pattern. Method according to any one of the preceding claims, characterized in that said electrical component (12) is embedded in the circuit board. Method according to any one of claims 1 - 9, characterized in that said electrical component (12 "") is surface mounted on the circuit board with connection terminals. A method according to any one of claims 11, characterized in that said electrical component is placed in receiving bushings before it is supported and turned upside down to be coated with said conductive material. Circuit boards (10, 10 ") provided with at least one electrical component (12, 12" ') and which are connected between different layers (14, 14 ", 17, 17", 19, 19 "), said components having coupling elements ( 13, 13 "') which at least partially protrude from a first covering layer (14, 14", 20 "'), characterized in that it further comprises couplings between said layers comprising an extension (16, 16", 16). ", 16 '") of said coupling element (13, 13 "), wherein said extension is formed by depositing a certain amount of conductive material on at least one coupling element (13, 13").
SE9903923A 1999-10-29 1999-10-29 Method for arranging coupling between different layers of a circuit board and circuit board SE521704C2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
SE9903923A SE521704C2 (en) 1999-10-29 1999-10-29 Method for arranging coupling between different layers of a circuit board and circuit board
AU13212/01A AU1321201A (en) 1999-10-29 2000-10-27 Method for providing connection between layers of a circuit board
PCT/SE2000/002103 WO2001031983A1 (en) 1999-10-29 2000-10-27 Method for providing connection between layers of a circuit board

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SE9903923A SE521704C2 (en) 1999-10-29 1999-10-29 Method for arranging coupling between different layers of a circuit board and circuit board

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SE9903923L SE9903923L (en) 2001-05-16
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Publication number Priority date Publication date Assignee Title
US5121299A (en) * 1989-12-29 1992-06-09 International Business Machines Corporation Multi-level circuit structure utilizing conductive cores having conductive protrusions and cavities therein
US5046238A (en) * 1990-03-15 1991-09-10 Rogers Corporation Method of manufacturing a multilayer circuit board
DE69123175T2 (en) * 1990-05-31 1997-04-03 Canon Kk Method of wiring a semiconductor circuit
US5401913A (en) * 1993-06-08 1995-03-28 Minnesota Mining And Manufacturing Company Electrical interconnections between adjacent circuit board layers of a multi-layer circuit board
US5873161A (en) * 1996-07-23 1999-02-23 Minnesota Mining And Manufacturing Company Method of making a Z axis interconnect circuit

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SE9903923L (en) 2001-05-16
SE9903923D0 (en) 1999-10-29
AU1321201A (en) 2001-05-08

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