SE464052B - MEMORY MANAGER DRIVES COMPUTERS - Google Patents

Description

464 052 g 2 The present invention has for its object to realize an improved memory management device for use with a computer, which contains a central processing unit (CPU) and a main memory. The invention therefore relates to a computer systems of the kind initially indicated with the characteristics specified in claim 1 - sign.

The memory management units thus contain a relocation base and when they ~ the first address signals from the CPU arrive, a second set of address signals for access to memory. Memory management devices also include storage means for receiving and storing signals representative of the types of information stored in the main memory. Access means for access to these stored signals are offered when the corresponding locations in the main memory are reached. The the stored signals from the storage means are connected to the main memory to e.g. restrict access to specific types of data in the network such as operating systems.

These signals also allow use to allow only read rights to programs or read and write rights to data.

In this preferred design, the storage means are an integral part of memory management device memory. The memory manager's n 'has four times as large a capacity as is necessary to meet the relocation number and value number for the entire main memory. As described later, this form of additional capacity a so-called bank change and various processes to be executed in the computer without reprogramming the memory management device memory.

An exemplary embodiment of the invention is described in more detail below with reference to the accompanying drawings, in which Fig. 1 shows a general block diagram of a central processing unit (CPU), memory management device (MMU) and the master and their connection in a computer, Fig. 2 shows a diagram of the organization of data stored in the invented memory management device memory, Fig. 3 shows a block diagram of the invented memory management unit, and Fig. 4 shows a diagram used to describe the various data combinations. hang used in the use of the memory management device and the resulting the organization of the information stored in the computer's main memory.

A memory management device (MMU) is described for use in a computer that * contains a central processing unit (CPU) and a main memory. In the following the description indicates many specific details such as nne size sizes, part numbers' etc. to provide a thorough understanding of the present invention.

However, it will be obvious to anyone familiar with the art that these details are not required to practice the present invention. IN other cases, circuits and well-known structures are not described in detail so as not to obscure the invention with unnecessary details. 3 464 052 Referring first to Fig. 1, the connection to the CPU is illustrated memory management unit and main nne. This connection is almost the same for present invention as a prior art. The computer in Fig. 1 includes one dual-direction data bus 16, which communicates with the CPU 10, the main memory 14 and the memory management unit (MMU) 12. The address bus 18 receives address signals from The CPU 10 and one of these addresses to the MMU memory management unit 12 and a dei tiii main memory 14. Other control signals are copied with CPU 10 and MMU 12, shown by lines 35 and 37 and the MMU 12 and main memory 14, shown by line 57.

The memory management unit MMU 12 is programmed from the CPU 10 through the data bus 16. The addresses are communicated over the bus 18 to the MMU 12 from the CPU 10 to iåta iaddning av MMU 12.

In the embodiment presented here, the CPU contains a 68000 processor.

For this processor, the CPU 10 provides 24 bit addresses. (Actually is first-order bit not physically present as such but encoded in others signals but for the purpose of the discussion it will be assumed to be an ordinary one address bit.) It will also be assumed for the purpose of the discussion that the seven the highest order bits of each logical address from the CPU designate a segment in memory, the next eight other significant bits constitute a page shift and the least significant nine bits an offset. In this preferred embodiment, the segment and the side offset at each address are copied to MMU 12.

The memory management unit (MMU) 12 provides a recycling base by replace the segment number from the CPU 10 with a segment number stored in the MMU 12. Speci- fikt, the segment number from CPU 10 is addressed one nn in MMU 12 and this nnne provides a segment base, which is used to address the main memory 14.

The page offset date of the address from the CPU 10 is monitored to determine if the lateral displacement falls within predetermined limits of the segment. This skuiie for example, prevent all noiior from an unused area in the main nnnes iäses and toikas as data. The segment base from MMU 12 is added together with the side offset and copied to the main memory 14 on the buses 18a and 18b in Fig. 1. The nine the least significant bits pass directly from the CPU to the main memory via bus 18c.

As shown in Fig. 3, this preferred embodiment of memory includes management unit MMU a memory management unit memory 20. This memory is one random access memory powered by commercially available MOS static RAM. As the memory currently being implemented is three RAMs with processing number 2148 is used for memory 20 and thus gives a total capacity of 12 k pieces. The organization of the memory management device memory is discussed in more detail in in connection with Fig. 2. 464 052 4 The address from the CPU is displayed as the 24-bit address (logical address) at the top part of Fig. 3. The seven most significant bits in the address are connected the memory management unit's memory via bus 18a and is used for addressing memory management device memory. The second most significant bits (bus 18b) connected to an adder 27, and the nine least significant bits (offset ) is connected via bus l8c to register 28. The output signal from the MMU's memory 20 consists of two 12-bit words (buses 22 and 23). These words are connected through the multiplexer 25 to the 12-bit bus 30. One of the 12-bit words from the memory 20 provides the segment base from the stored relocation base. The other 12 pieces remain of eight bits for limit value control of the page offset and four others bits, which perform functions included in the present invention.

In this preferred invention, the multiplexer 25 does not physically exist.

Rather, the output of memory 20 is time multiplexed. However, it is out of writing point of view for understanding easier to introduce the multiplexer 25.

The multiplexer 25 is also used to load information from bus 16 in memory 20. The signal on line 47 from the access control logic 40 provides access memory 20 as well as the signals on line 35. The signal on line 37 controls multi- the plexing of data between either bus 22 or bus 23. The 12-bit bus 30 from the multiplexer 25 is connected to the adder 27.

This adder also receives eight bits on bus 18b. As described, used the adder 27 to determine if the page offset falls within a predetermined one area of the selected segment.

The adder 27 also combines the relocation (segment base) from the memory handling unit nnnne with the side offset to provide the 12 most significant edge the bits to the physical address. These 12 pieces along with the nine the bits from bus l8c are coupled to register 28 to provide a 21-bit address, which is sent to the main memory 14. (Register 28 does not exist in this preferred design; it is displayed to facilitate the explanation.) The four access control bits are disconnected from the multiplexer 25 over line 45 to the access logic 40. Here the signals are decoded to provide the main memory and others controls as follows: A bit controls the type of main memory access (1 = read, only, 0 = read / write).

The second bit controls in-out access (1 = in-out, 0 = no in-out access). The the third bit controls main memory access (1 = memory access, 0 = no main minnesacces). The fourth bit controls the stack (1 = stack) procedure segment-check no spill, 0 = normal segment check spill). Access the control logic 40 is shown in Fig. 3 coupled to main memory control via line 57 to control memory access and the types of access allowed (ie read or read / write). Logic 40 is connected to adder 27 via spill / transfer = carry-in lines and against memory 20 via line 47 to 5,464,052 enable access to the memory 20. The specific access control bit pattern that used in this preferred design is shown below.

Access control bits Memory in-out read only stack Pieces Address space and access 0 1 0 0 Main memory-read only stack 0 1 0 1 Main memory-read only 0 1 1 0 Main memory read / write stack 0 1 1 1 Main memory read / write 1 0 0 1 In-out space 1 1 0 0 Page invalid (segment does not exist) 1 1 1 1 Special in-out space Any other Not allowed (unpredictable results) First, assume that memory 20 has been programmed from the CPU. For a first approach to the explanation of the MMU memory management device shall be disregarded from line 35 2-bit function. When the CPU addresses the main memory, the seven address the most significant bits of MMU memory 20. The 12 bits of the relocation data segment are connected via buses 22 and 30 to the adder 27. There they are combined with side displacements. (bus 18b) and the resulting address is combined with the nine bits that indicates the offset in register 28 to indicate the final physical address.

This part of the MMU works in a way similar to the previous MMU. Thus can relocation segment master data is programmed into memory (disregarding line 35) in a manner well known in the art.

The 12 bits that form the limit value data are connected to the adder 27. The four bits constituting access data are connected to logic 40 via line 45, as before shown. Limit data is stored in the preferred format in the form of a complement form in memory 20 for a non-stack segment. For stack segments are stored the limit value as "length minus one" (eg a two-sided segment would be stored as 0000 0001 memory 20). When this limit value data is added to the page offset one in the adder 27 determines the result of the addition whether the side offset falls within the predetermined range of the segment. This is an improvement over prior art limit value control, where additional steps are required.

Example without stack Referring to Fig. 4, a representation of the main computer is illustrated. memory. Assume that this is stored in space 50. Assume further that the largest page the offset (1111 1111) for data extends to location 52 and that within this segment data extends to a page offset of (1110 0000) 464 052 (line 51). For this lateral displacement, the one complement is 20 (Fig. 3). About this segments are addressed and assuming the page offset address is 1111 1111 (ie into the free part of the memory), the adder adds 27 1111-1111 to the stored number 0001 1111. A spill occurs from the adder 27 and this spill condition is sensed by logic 57 (Fig. 3). For this example, it is indicated that the page offset one is not within the value set and a signal is given on line 57 to show that the address is incorrect. The logic 40 prevents access to the main memory via line 57 and / or an error signal is generated.

Referring again to Fig. 4, assume that programs were stored at location 53 and that the highest lateral displacement 1111 1111 extends to position 50, which is outside the current program area, which extends to place 54.

If the page offset for location 54 is 0011 0000, then 1100 1111 is stored in memory 20 (Fig. 3) for the segment beginning at location 55. If this segment is addressed and the page offset is 0000 00001 (address of the program), so add circuit 27 1100 1111 and 0000 0001. This time no spillage occurs, so no signal forwarded to logic 40, ie access is allowed. Note that if the page offset is 0100 0000 (not within the allowable range), spillage occurs when this value added to the stored value 1100 1111. This spill indicates for the logic that the page offset is not within the allowed range and memory access is made impossible.

Example with stack In some programming languages (eg Pascal) stack (in memory) is very valuable fully. Stacks can be performed by moving data up in memory but it is time consuming. demanding. Stacks in the system described here are allowed to grow down in the memory below another border control procedure.

Assume a one-page stack segment. The limit value, which is stored in the memory 20 as the one-complement to the page offset 1111 1111 0000 0000, is the same as the size minus one (0000 0001 0000 0000). The access control pieces cause logic 40 to produce a carry-in equal to 1. If the page transfer the shooting is 1111 1111, a spill occurs. This spill is sensed by logic 40 and interpreted as a valid (within permitted range) permit. If the page offset has been 1111 1110 (the stack has grown too much), no spillage occurs and this is interpreted as an address outside the permitted range.

Similarly, if the stack is two segments large, 0000 0001 stored in memory 20. Again, the carry-in is set to one. One page shift on 1111 1110 would result in spillage, as shown on a song address, while on page shift on 1111 1100 no spillage occurs and this indicates an address outside the permitted range. 464 052 Fig. 4 example Referring again to Fig. 4, assume that a process (program and data) stored in the main memory 14 between locations 0 and 500 kB. The three remaining the access bits in memory 20, which correspond to the segment address of locations between 0 up to 500 kB is used to perform a special control, as mentioned above.

For example, for those segments that only contain programs, only reading in memory is allowed.

This, of course, prevents accidental typing in programs. Both reading and writing in segments, which contain this, may be allowed. This is indicated in fig. 4 to the right of program 59 and data 60.

The memory 20 is programmed (ie the access control bits) to prevent reading some segments in the main memory except in some modes (eg supervisory = monitoring mode). This is done, for example, to prevent the user from reading and copy an operating system. Briefly referred again to Fig. 4, when the program 59 is run, no address is allowed to the memory 20, as such access could cause the relocation base, limit value data and access data to be inadvertently changed. Thus, the four access bits provide protection for programs stored in the main memory and restricts access to certain information stored in the memory. In a typical application, an operating system is loaded from disk memory into the main memory. When it well located in the main memory, the CPU has access to the operating system in the monitoring Courage. However, the user is again denied access and thus the opportunity to copy the operating system.

In the present invention, the memory 20 has four times the capacity obtained required to provide a relocation base as well as limit value and address data for the main memory. The signals from the CPU on lines 35 allow selection of each quadrant of the memory 20. Each such quadrant is called a data context (data context hang 0-3) in the following description.

Referring to Fig. 2, the organization of the memory management unit is shown memory 20 as four separate quadrants: 20a (data context), 20b (data context hang 1), 20c (data context 2), 20d (data context 3). Data context 1, 2 and 3 are organized into 256 x 12 bits each. (128 x 12 bits for the relocation base and 128 x 12 bits for limit values and access data.) Data context 0 is selected by The CPU during monitoring mode and this data context stores control data, which associated with the operating system. It should be noted that each data context can store information, which covers the entire main memory, so that there are three overlapping memory management device memories for user processes.

The value of having these overlapping memories is best shown in Fig. 4. net 14 is shown programmed with three processes P1, P2 and P3. Process 1 is stored between 0-500 kB, process 2 between 600 kB and 1 MB and process 3 between 1.2 MB 464 052 and 1.5 MB. Operating system data is stored between 1.8 MB and 2 MB.

First, assume that the operating system is loaded and stored between 1.8 MB and 2.0 MB.

A suitable relocation base is stored in memory 20 so that under monitoring modes the addresses 0-200 kB automatically end up between 1.8 to 2.0 MB in the main memory. The borders are also loaded so that during monitoring mode the free space in the memory cannot be accessed. During monitoring mode (data context O) is given, which is indicated in Fig. 4 under the heading (data context 0) access to the entire memory management unit memory and main memory (except for the access bits, which prevent writing in the operating system is stored in the main memory and thus protects the program from interference, due to program errors). Because the memory management device's memory is available, it can be programmed via bus 16, as shown in Fig. 3 and earlier described.

Assume that data context 1 is to be used for program 59 and data 60, then a quadrant is programmed in the memory 20 corresponding to data context 1 to indicate the location of the program 59 and data 60. Limit values and access bits is set as indicated under data context 1. When data context 1 is selected, can program 59 is read (only) and reading and writing of data 60 is allowed.

No other access to other memory locations is possible, nor can memory the memory of the unit is written in.

A second process can be stored in memory. The operating system knows the location of the first process and can program another quadrant in the memory 20 for process 2. The relocation base is programmed so that when the CPU addresses locations corresponding to 0-400 kB, these locations in the main memory will be 600 kB to 1 MB. As shown under the heading data context 2 in Fig. 4, the access bits are programmed for to allow writing in data 50 and reading, but only reading in program 53.

It is also not possible to write in the memory management unit's memory, nor is it access allowed to other locations in the main memory. Similarly, a third can process is stored in the main memory by data context 3 shown in Fig. 4.

The advantage of the arrangement in Fig. 4 is that three different processes are stored in the main memory and that each process can be easily designated by the memory management device memory, ie by selecting data context 1, 2 or 3. A special data context (data context 0) is saved as the starting point of the operating system in this preferred embodiment, as described. This allows driving of three different programs, without reprogramming the memory management device memory. This good versatility is obtained, as there is an overlapping memory management capacity of the memory management device memory. ¿6A 'fi R0 * f uuz ..

Here, an improved memory management unit has been described, which for ïrequires a fïertaï program to run, without reprogramming the computer's memory unit memory. The enhanced device also restricts access to some types of data and prevents accidental typing in programs.

Claims (10)

464 052 10 Patent claims A computer system, comprising a central processing unit (CPU), a main memory (14) and a memory management unit (MMU), which memory management unit is connected to the process unit and the main memory, the memory management unit comprising an MMU memory (20) containing a plurality of section stores of a plurality of relocation bases, the MMU memory receiving first addresses from the process unit (CPU) and generating second addresses for access to the main memory, characterized in that each first address selects a predetermined relocation base in each memory section, which is designed to provide access to an area in the main memory, so that a specific address in the main memory is accessible by more than one memory section (20a-d) and that control means are connected to the process unit (CPU) and the memory management unit (MMU) to generate a control signal for selecting a particular section in the MMU. memory (20), whereby the memory management unit (MMU) provides the relocation bases for access to a plurality of pr occes, stored in the main memory (14) without changing the first addresses. System according to claim 1, characterized in that one of the sections (20 a) of the MMU memory is selected as a monitoring section when the process unit (CPU) is in a monitoring mode, so that this monitoring section provides access to the entire MMU memory (20). and the entire main memory (14). System according to claim 1 or 2, characterized in that an adder (27) is connected to the MMU memory (20) and to the process unit (CPU), which adder is arranged to receive a binary complement to a limit value and add this complementing an area value of the main memory (14) accessible to the process unit to provide selected bits of the first address, an error signal being generated when the process unit attempts to access outside the address range determined by the limit value. System according to claim 3, characterized in that the sections of the MMU memory (20 a-d) store a plurality of access control bits, which generate a code signal to determine a special type of access to the main memory (14). System according to claim 4, characterized in that the MMU memory (20) comprises storage means for storing signals representative of the types of information contained in the main memory (14) for accepting the relocation bases, the limit values and the access control bits from the main memory during a program cycle of the memory management device (MMU). 11 464 'G52 System according to any one of claims 1-5, characterized in that the control means are arranged to accept the code signal and provide suitable control signals for controlling the type of access to the main memory (14). System according to claim 1, characterized in that each section (20 ad) in the MMU memory (20) is arranged to receive a first address from the process unit (CPU), the first address selecting a predetermined relocation base in each of the sections, and each of said relocation bases in each section generates a second address for access to the main memory (14). System according to any one of claims 1-7, characterized in that the storage means are connected to the process unit (CPU) for accepting at least a part of the first address, and that access means (18) are arranged to give the stored signals access to the storage means and the main memory (14). System according to one of Claims 1 to 8, characterized in that each section (20 ad) of the MMU memory (20) is arranged for storing a plurality of limit values, each of which determines an address range which is accessible in the main memory. (14) for each of the sections in the MMU. System according to claim 1, characterized in that each section (20 ad) of the MMU memory (20) contains other addresses, which overlap other addresses contained in other sections, so that each section has access to areas of the main memory (14 ) to which other sections also have access.