SE432313B - Databehandlingsanordning innefattande en for alla in/ut- enheter gemensam uppropsledning for bade cykeltilldelningskrav och avbrottskrav - Google Patents

Databehandlingsanordning innefattande en for alla in/ut- enheter gemensam uppropsledning for bade cykeltilldelningskrav och avbrottskrav

Info

Publication number
SE432313B
SE432313B SE7714244A SE7714244A SE432313B SE 432313 B SE432313 B SE 432313B SE 7714244 A SE7714244 A SE 7714244A SE 7714244 A SE7714244 A SE 7714244A SE 432313 B SE432313 B SE 432313B
Authority
SE
Sweden
Prior art keywords
requirements
data processing
processing device
device including
interruption
Prior art date
Application number
SE7714244A
Other languages
English (en)
Other versions
SE7714244L (sv
Inventor
G B Marenin
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of SE7714244L publication Critical patent/SE7714244L/sv
Publication of SE432313B publication Critical patent/SE432313B/sv

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/282—Cycle stealing DMA
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4247—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Microcomputers (AREA)
  • Executing Machine-Instructions (AREA)
SE7714244A 1976-12-27 1977-12-15 Databehandlingsanordning innefattande en for alla in/ut- enheter gemensam uppropsledning for bade cykeltilldelningskrav och avbrottskrav SE432313B (sv)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/754,193 US4181934A (en) 1976-12-27 1976-12-27 Microprocessor architecture with integrated interrupts and cycle steals prioritized channel

Publications (2)

Publication Number Publication Date
SE7714244L SE7714244L (sv) 1978-06-28
SE432313B true SE432313B (sv) 1984-03-26

Family

ID=25033801

Family Applications (1)

Application Number Title Priority Date Filing Date
SE7714244A SE432313B (sv) 1976-12-27 1977-12-15 Databehandlingsanordning innefattande en for alla in/ut- enheter gemensam uppropsledning for bade cykeltilldelningskrav och avbrottskrav

Country Status (11)

Country Link
US (1) US4181934A (sv)
JP (1) JPS6053899B2 (sv)
AU (1) AU513019B2 (sv)
BR (1) BR7708662A (sv)
CA (1) CA1100643A (sv)
CH (1) CH623947A5 (sv)
DE (1) DE2756768C2 (sv)
ES (1) ES465431A1 (sv)
GB (1) GB1543278A (sv)
HK (1) HK70684A (sv)
SE (1) SE432313B (sv)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4363091A (en) * 1978-01-31 1982-12-07 Intel Corporation Extended address, single and multiple bit microprocessor
US4417304A (en) * 1979-07-30 1983-11-22 International Business Machines Corporation Synchronous cycle steal mechanism for transferring data between a processor storage unit and a separate data handling unit
US4479179A (en) * 1979-07-30 1984-10-23 International Business Machines Corporation Synchronous cycle steal mechanism for transferring data between a processor storage unit and a separate data handling unit
US4462029A (en) * 1979-12-06 1984-07-24 Analogic Corporation Command bus
US4435758A (en) 1980-03-10 1984-03-06 International Business Machines Corporation Method for conditional branch execution in SIMD vector processors
JPS5720859A (en) * 1980-05-30 1982-02-03 Fairchild Camera Instr Co Microprocessor
US4396980A (en) * 1980-07-11 1983-08-02 Fairchild Camera & Instrument Corp. Combined integrated injection logic and transistor-transistor logic microprocessor integrated circuit design
US4400772A (en) * 1980-12-30 1983-08-23 International Memories, Inc. Method and apparatus for direct memory access in a data processing system
US4482949A (en) * 1981-07-20 1984-11-13 Motorola, Inc. Unit for prioritizing earlier and later arriving input requests
US4811279A (en) * 1981-10-05 1989-03-07 Digital Equipment Corporation Secondary storage facility employing serial communications between drive and controller
US4450525A (en) * 1981-12-07 1984-05-22 Ibm Corporation Control unit for a functional processor
US4577282A (en) * 1982-02-22 1986-03-18 Texas Instruments Incorporated Microcomputer system for digital signal processing
US4533992A (en) * 1982-02-22 1985-08-06 Texas Instruments Incorporated Microcomputer having shifter in ALU input
US4514805A (en) * 1982-02-22 1985-04-30 Texas Instruments Incorporated Interrupt operation in systems emulator mode for microcomputer
US4591972A (en) * 1982-11-15 1986-05-27 Data General Corp. Data processing system with unique microcode control
EP0155275B1 (en) * 1983-09-12 1989-04-05 Motorola, Inc. Prefetch validation
US4706190A (en) * 1983-09-22 1987-11-10 Digital Equipment Corporation Retry mechanism for releasing control of a communications path in digital computer system
US4769768A (en) * 1983-09-22 1988-09-06 Digital Equipment Corporation Method and apparatus for requesting service of interrupts by selected number of processors
USRE34052E (en) * 1984-05-31 1992-09-01 International Business Machines Corporation Data processing system with CPU register to register data transfers overlapped with data transfer to and from main storage
US4648029A (en) * 1984-08-27 1987-03-03 International Business Machines Corporation Multiplexed interrupt/DMA request arbitration apparatus and method
BG39765A1 (en) * 1985-02-14 1986-08-15 Turlakov Device for connecting 8- degree and 16- degree modules to 16- degree microprocessor system
US5255384A (en) * 1985-02-22 1993-10-19 Intergraph Corporation Memory address translation system having modifiable and non-modifiable translation mechanisms
US4899275A (en) * 1985-02-22 1990-02-06 Intergraph Corporation Cache-MMU system
US4709324A (en) * 1985-11-27 1987-11-24 Motorola, Inc. Data processor control unit having an interrupt service using instruction prefetch redirection
US4961067A (en) * 1986-07-28 1990-10-02 Motorola, Inc. Pattern driven interrupt in a digital data processor
US5001624A (en) * 1987-02-13 1991-03-19 Harrell Hoffman Processor controlled DMA controller for transferring instruction and data from memory to coprocessor
DE3788877T2 (de) * 1987-03-24 1994-06-23 Insignia Solutions Ltd Einrichtung zur software-emulation.
US4942520A (en) * 1987-07-31 1990-07-17 Prime Computer, Inc. Method and apparatus for indexing, accessing and updating a memory
DE3779313D1 (de) * 1987-08-20 1992-06-25 Ibm Schnittstellenmechanismus fuer informationsuebertragungssteuerung zwischen zwei vorrichtungen.
US5317715A (en) * 1987-12-15 1994-05-31 Advanced Micro Devices, Inc. Reduced instruction set computer system including apparatus and method for coupling a high performance RISC interface to a peripheral bus having different performance characteristics
US4916601A (en) * 1988-12-19 1990-04-10 Bull Hn Information Systems Inc. Means for transferring firmware signals between a control store and a microprocessor means through a reduced number of connections by transfer according to firmware signal function
US5144230A (en) * 1990-11-26 1992-09-01 The Boeing Company Method and system for testing integrated circuits by cycle stealing
US5363495A (en) * 1991-08-26 1994-11-08 International Business Machines Corporation Data processing system with multiple execution units capable of executing instructions out of sequence
EP0562353A3 (de) * 1992-03-27 2004-08-18 Siemens Aktiengesellschaft Verfahren zum Übertragen hochpriorer Programme und Daten in einem Kommunikationssystem
US5473757A (en) * 1992-12-11 1995-12-05 Ge Fanuc Automation North America, Inc. I/O controller using single data lines for slot enable/interrupt signals and specific circuit for distinguishing between the signals thereof
US5435001A (en) * 1993-07-06 1995-07-18 Tandem Computers Incorporated Method of state determination in lock-stepped processors
FR2720172B1 (fr) * 1994-05-20 1996-06-28 Sgs Thomson Microelectronics Dispositif de mise en Óoeuvre numérique d'une opération de division.
US5838991A (en) * 1994-12-29 1998-11-17 International Business Machines Corporation Preemptable idle time activities for constant data delivery by determining whether initiating a host command will conflict with an idle time activity being executed
TWI259356B (en) * 2004-03-26 2006-08-01 Infortrend Technology Inc Apparatus for checking data coherence, controller and storage system having the same and method therefore is disclosed

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3680054A (en) * 1970-07-06 1972-07-25 Ibm Input/output channel
US3668651A (en) * 1970-12-30 1972-06-06 Ibm Working device code method of i/o control
US3909790A (en) * 1972-08-25 1975-09-30 Omnus Computer Corp Minicomputer with selector channel input-output system and interrupt system
US3962682A (en) * 1974-10-30 1976-06-08 Motorola, Inc. Split low order internal address bus for microprocessor
US4004283A (en) * 1974-10-30 1977-01-18 Motorola, Inc. Multiple interrupt microprocessor system
US4034349A (en) * 1976-01-29 1977-07-05 Sperry Rand Corporation Apparatus for processing interrupts in microprocessing systems
US4038641A (en) * 1976-04-30 1977-07-26 International Business Machines Corporation Common polling logic for input/output interrupt or cycle steal data transfer requests
US4056847A (en) * 1976-08-04 1977-11-01 Rca Corporation Priority vector interrupt system

Also Published As

Publication number Publication date
CH623947A5 (sv) 1981-06-30
DE2756768A1 (de) 1978-06-29
CA1100643A (en) 1981-05-05
JPS5382240A (en) 1978-07-20
BR7708662A (pt) 1979-07-24
ES465431A1 (es) 1978-09-16
GB1543278A (en) 1979-03-28
AU513019B2 (en) 1980-11-06
HK70684A (en) 1984-09-21
SE7714244L (sv) 1978-06-28
DE2756768C2 (de) 1982-08-12
US4181934A (en) 1980-01-01
AU2982277A (en) 1979-05-24
JPS6053899B2 (ja) 1985-11-27

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