SE409793B - KITS IN WHICH TRANSMISSION OF PCM INFORMATION REDUCES THE NEED OF THE NUMBER OF TRANSFER BITS AND DEVICE FOR PERFORMING THE KIT - Google Patents

Description

The invention is described in more detail with the aid of an exemplary embodiment with reference to the accompanying drawing, of which Fig. 1 constitutes a block diagram of a device according to an embodiment of the invention and Fig. 2 constitutes a block diagram of a device according to another embodiment of the invention.

As can be seen from Fig. 1, the device according to the invention comprises on the transmitter side a controllable amplifier F1, with the task of adapting the level of the incoming signal to the working range of an A / D converter AD connected to the amplifier output, by switching on amplification or attenuation depending on control inputs incoming digital control signals on the amplifier. In this case, a normalized signal amplitude is obtained as an input signal to the A / D converter. By applying the non-malalized amplitudes of the signals and only transmitting information about segments, ie. the amplitude range within which the decoding takes place, when changing segments is relevant, the entire segment determination code can be output from the transmission code. Typically, the PCM code consists of 8 bits divided into, one bit for polarity determination, three bits for determining segment affiliation (C code), and four bits for amplitude determination (S code). The segment determination is performed in the device according to the invention by means of the amplitude code (S-code) in such a way that maximum positive amplitude (+ Smax), gives orders for switching to the nearest higher segment and that maximum negative amplitude (-Smax), gives orders for switching to nearest lower segment. In this way, a transmission code is obtained which contains only five bits, four bits for amplitude indication and one polarity bit.

After A / D conversion in the converter AD, the signals are applied, in parallel form the inputs of a decoder DI. According to the example, said signals are also applied in parallel form to the inputs of a parallel / series converter PS. The transmission of signals to the receiver side can also take place in parallel form. At the outputs of the decoder D1, signals are output to a control device consisting of a time measuring circuit Cdå, a logic circuit 01 and a counter CM1. When the decoder D1 has decoded a signal corresponding to the maximum positive amplitude value with the binary combination 11111, a logic ONE signal is output from the decoder output + Smax as a counting signal to a first input on the counter CM1. The counter then emits an output signal to the controllable amplifier F1, which signal indicates that an up-tuning to the nearest higher segment is to take place, whereby the signal from the amplifier, in order to be able to measure double amplitude values, is attenuated by a factor 2 determined by the signal from the counter CM1 .

When switching to lower segments, the following happens. The timing circuit CRA consists of a counter which, at a reset input, senses the most significant bit in the amplitude code transmitted from output SH of the decoder D1. At a second input, the counter receives counting pulses from a clock signal generator common to the system, not shown in the drawing, and then steps up a position, for example every 10 ms. If output SH is not activated, ie. if the most significant bit has been a logical zero all the time _ until the counter reaches the 8th position ie. after 80 ms, a signal is output from the counter GRAY to a first input of a logic circuit 01. If said output SH is activated before the "ii 'vmssa-e 3 counter reaches the 8th position, the counter is reset and the counting process is resumed. the decoder D1 decodes a signal corresponding to the zero level value (S0) of the signal with the binary combination 10000, a logic ETT signal is output from the decoder output S0 to a second input on the circuit 01. When the circuit 01 is activated, a countdown signal is output to a second input on the counter CM1, which emits an output signal to the controllable amplifier F1, which signal indicates that a down-regulation to the nearest lower segment is to take place, in which case the signal from the amplifier is amplified by a factor 2 determined by the signal from the counter C141. higher segments occur when the binary combination 11111 is decoded, while down-regulation to the nearest lower segment is dependent on a certain amplitude value, according to example half of the maximum amplitude value has been undershot for a certain time in combination with the zero level signal 10000 having to occur.

When no segment change is to occur, all signals are output unchanged to the receiver after conversion in the parallel / series converter PS. The system's receivers must also be informed of any segment changes. This information is obtained by the codes + Smax (11111) for upregulation and -Smax (00000) for downregulation.

In case the decoder D1 emits a signal corresponding to the code SO (10000), there are two possibilities, either the signal is only a level message that is not connected to segment change, the signal is then sent unchanged to the receiver, or the signal is linked to the condition for downregulation . If this is the case, the most significant bit_ (MSB) in the code must be inverted, in order for the receiver to perceive the signal as a control signal, whereby on the transmission side the code 00000 is transmitted, ie. -Smax means order to the recipient to perform down-regulation. The inversion of the HSB bit in the signal S0 is accessed so that the information about the state of the MSB bit is transmitted from the A / D converter to one input of an exclusive OR circuit 02, the other input of which is activated by the output signal from the circuit 01, ie the downregulation signal. Since the zero level signal S0 only constitutes a level indication, ie no segment change, a logic one is obtained at said one input to the circuit 02. Since no one signal for downregulation emits from the circuit 01, a zero is obtained at the second input of the circuit 02, the circuit emitting a one at the output. When the zero level signal is connected to down-regulation, the said one input on the circuit 02 still receives ONE signal while the other input, which is now activated from circuit 01, also receives ETT signal whereby circuit 02 emits zero signal on the output, the NSB bit of the signal is thus inverse. The signal -Smax indicating maximum negative amplitude can also constitute a pure level indication.

Since the code for -Smax is 00000, this signal must not be sent out on the line in this case so that the receiver does not confuse this signal with a down-regulation message. Instead, emit the nearest adjacent amplitude steps, ie. 00001, which means that the least significant bit, the LSB bit, in the data word must be inverted, which takes place in an exclusive OR circuit 05. One input of the circuit 03 is activated by the va.- 'rvíaeen-s' signal -Smax from the decoder D1. The signal indicating the state of the LSB bit is connected to the second input of the circuit 03. When the signal -Smax has been decoded, said one input receives a logic ONE, where, since the LSB bit is ZERO, an ONE is output at the output * of the circuit. In all other combinations, the LSD bit passes circuit 03 unchanged.

In the receiver, the incoming data stream is converted into parallel signals in a series / parallel1 converter SP, and a digital / analog converter DA is supplied.

A decoder D2 decodes the signal before the D / A conversion. The signal thus decoded is converted in the D / A converter so that a normalized analog signal is output at the output of the D / A converter. Said analog signal is applied to the input of a controllable amplifier F2 which, depending on control signals received at control inputs on the amplifier, by switching on amplification or attenuation cancels the normalization and restores the original analog signal incoming to the system. Control signals are output from the decoder D2 to the counter CM2. When the decoder has decoded a signal corresponding to the maximum positive amplitude value (+ Smax), a count-up signal is output to a first input of the counter CM2 which outputs a control signal to the controllable amplifier F2.

Said control signal indicates that an upregulation to the nearest higher segment is to take place, whereby the signal out of the amplifier F2 is amplified by a factor 2 which is determined by said control signal. When the decoder D2 has decoded a signal corresponding to the maximum negative amplitude value -Smax, a countdown signal is output to a second input of the counter CM2 which outputs a control signal to the amplifier F2. Said control signal indicates that a down-regulation to the nearest lower segment is to take place, whereby the signal out of the amplifier is attenuated by a factor 2 which is determined by said control signal. Since, as previously mentioned, the downlink message from the transmitter side of the system is combined with the zero level signal S0 in which the HSB bit has been inverted, the NSB bit on the receiver side must be reset before the D / A conversion. This is done so that the signal regarding the binary state of the MSB bit is applied to one input of an exclusive OR; circuit Ok. The second input of the circuit is activated by the signal -Smax when it occurs p which means that all signals pass unchanged except the signal 00000 in which the Mss bit is inverted so that the signal 10000 (so) reset In tabular form are examples of how a binary word is composed of subcodes indicating polarity, segments and amplitude levels. For simplicity, only the positive part of the signal is displayed.

As previously mentioned, the total amplitude range of the signal is divided into a number of segments and each segment comprises a number of amplitude levels. The amplitude steps within a segment are equal, while the amplitude steps of two adjacent segments are related to each other by a factor of 2. The size of the amplitude step within the segment corresponds to the amplitude value belonging to the least significant bit LSB, for the segment in question. In known systems, a certain amplitude is unambiguously bound to segments and amplitude steps, which means that between successive decodings segments and amplitude steps can be changed to any other segment and amplitude step depending on the amplitude value at the time of coding.

In the process according to the invention, however, as previously described, the segment affiliation is determined by a special segment control device, and changes in segment affiliation are allowed to take place only according to pre-set conditions. According to the example, segment areas are selected in such a way that the first segment has an LSB corresponding to 20 = 1mV and indicates with, for example, 16 amplitude steps the amplitude 0, 1, 2 ... 15mV. The next segment has an LSB corresponding to 21 = .mV and indicates in 16 amplitude steps the amplitude 0, 2, 4 ... 50mV. Additional subsequent segments have an LSB corresponding to 22 = èmV and indicate in 16 amplitude steps the amplitude 0, à, 8 ... 60mV etc. for subsequent segments.

In the table, the LSB value for each segment is expressed in a decimal number.

With the support of the table, examples of a conversion cycle according to the example are given. A signal with a large amplitude range is divided into a number of segments of which Co-C5 is shown, and where each segment is divided into a number of amplitude stages S0-S15. Each amplitude step within a segment comprises an amplitude range determined by the segment's ISB value 1, 2, 4, and so on. The table also shows the So- $ 15 binary representation of the various amplitude steps.

An amplitude, for example 8 mV, is indicated partly with segment position indication C = 0 at which segment LSB according to the above corresponds to 1 mV, partly with the amplitude step indication S = 8. The specified amplitude is obtained through the product of the LSB value of the segment position and the amplitude step indication, ie in the example 1x8 = 8mV. The same amplitude can also be specified with another segment position indication C = 1 at which segment, according to the example above, 1SB corresponds to 2 mV, and with the amplitude step indication S = k, ie according to the example 2x4 = 8mV. The amplitude can similarly also be specified in segment positions C = 2 and C = 5. In higher segments, 0. As shown in the table, greater accuracy is achieved the lower segment the signal is specified in, and that in the device according to the invention, by changing the gain, one constantly works in the segment that gives the greatest accuracy. 7711964-9 ".6 1 1111 S15 15 30 60 120 2110 11011 1 1110, sm 111. 2s 56 112 2211 111.8 i I 1 1 | 000 ss s 16 32 611 128 256 1 0111 gs? 7 111 28 56 112 2211. 1 I 1 0100 sk 4 s 16 _ 32 611 122 1 0011 S3 3 6 12 21 as 96 1 0010 S2 2 11 16 .32 611 _1 0001 sl 1 2 16 i 32 10000 so 0 0 0 0 Po1 + Sf od C Co C1 C2 G3 Ch C5 etc. Lsn 1 _ 2 11 s 16 32 With reference to Fig. 2, a further embodiment is described, in which a device according to the invention cooperates with an A / DD / A converter of conventional type in a PCM Such an A / D converter itself indicates in which segment the coding is to take place, while said counter CM1 indicates in which segment the coding should take place.By performing a comparison between said two segment indications, the code can be converted and adapted in accordance with the invention. In this embodiment, the amplifier F1 is output on the transmitter side and instead a code converter CRB, a comparator J, a shift register SRI and a number of OR circuits C1-G5 are added. - the amplifier F2 is output and a code converter CRC, a shift register SR2 and a control circuit 05 are added instead. Other circuits have the same task and function as described in connection with Fig. 1.

On the transmitter side, a converter AD converts an incoming analog signal to a digital signal and outputs this at its outputs in parallel form, whereby information on segment code is applied to inputs on the code converter CRB and information on amplitude code is applied to inputs on the shift register SRI and an additional ONE bit E occupies the first position in the register. The polarity bit is applied directly to an input of the decoder D1. Thus, in this embodiment, 6 bits are used in the codeword, a polarity bit, four amplitude bits and said extra ONE bit E. The segment determination value in the counter CM1 is a temporary segment value because to this value one (1) can be added or subtracted, depending of control signals at the inputs, in the manner described in connection with Fig.1 In the previously mentioned comparison between the segment determination code from the A / D converter and the said temporary segment value from the counter CM1, the following three cases may occur: '7714964-9 (a) The codes are the same (b) The code from the A / D converter is larger than the code from the counter (c) The code from the A / Ü converter is smaller than the code from the counter From the outputs of the code converter CRB, the segment determination code of the A / D converter is deleted to inputs on the comparator J. The comparator receives on other inputs the temporary segment determination value from the counter CMI, after which it compares the received codes.

If the comparison shows that the codes are the same, and if neither + Smax nor -Smax is present, the amplitude code from the shift register SRI remains unchanged via the OR »circuits C1-G5 and the parallel / serial converter PS, to the receiver side. The mentioned extra signal E always accompanies the amplitude code of the receiver.

On the receiver side, the signal is subjected to a series / parallel conversion in the converter SP, after which the amplitude code passes unchanged on the shift register SR2 and to the input of a digital / analog converter DA. The said D / A converter is of the same type as the A / D converter on the transmitter side and thus requires information on segment determination code. A decoder D2 decodes the signal and states that neither + Smax nor -Smax is present, which is why the contents of the counter CM2 are added to the D / A converter without change via a code converter CRC, as the final segment determination code.

If the comparison on the transmitter side between the segment codes shows that the segment code from the A / D converter is greater than the said temporary segment determination value, the comparator issues. J logical ONE signal as control signal to one input on all OR circuits Cl-CS.

Regardless of which amplitude code is now transmitted from the shift register SRI, all outputs from the OR circuits are coated with ETTOR, ie the binary combination that corresponds to the maximum positive amplitude value + Smax. This signal is applied to the decoder D1 which outputs a counting signal to the counter CMI to increase its content by one, in addition the signal is transmitted in the manner previously described to the receiver. The comparator J now performs a new comparison between the segment codes after the content of the calculator CMI has been increased by one. If inequality still prevails, the process is repeated until its equality is achieved.

On the receiving side, the decoder D2 senses the transmitted maximum positive amplitude + Smax, and outputs a counting pulse to the counter CM2 to increase its content by one (1). whereby the new sogment value formed thereby is sent to the D / A converter via the code converter CHÉ. If the comparison on the transmitter side finally shows that the value from the A / D converter is lower than the said temporary segment value, the comparator J emits a control signal which partly constitutes a step pulse to the code converter CRB and increases its content by one (1 When the register receives the first shift pulse, the amplitude code word entered in the register is shifted one step, whereby the least significant bit in the word is replaced. The extra ETT bit E entered in the first position of the register is moved now to the second position and instead a zero is entered in the first position.

If the difference between the segment codes in the comparison is so large that another shift pulse is output to the shift register, the extra ETT bit E is moved to the third position, the first position entered zero is moved to the second position "and a new zero is entered in the first position while now the least significant bit is replaced. If the codeword in the shift register before the shift had the appearance 10000, it then gets the appearance 00100 after the shift. This new password is sent to the recipient side in unchanged form, since neither + Smax nor -Smax can occur. Of course, the polarity bit is also transmitted together with the rest of the code word. The step pulse from the comparator J increases the content of the code converter CRB, after which the new value from the code converter is added to the comparator J for a new comparison. The process is repeated until the segment code from the A / D converter is equal to the said temporary segment value from the calculator CMI. If the segment code from the A / D converter at the beginning of the comparison was for example 3, ie the specified amplitude is to be decoded in segment 3, and the temporary segment value from the counter CM1 was for example 5, ie the most suitable segment to encode the amplitude value in is segment no. 5, the difference is equal to two segment steps. This means that the code converter CRB is counted up two steps and that the shift register SRI receives two shift pulses which shift the entered word two steps. : l: On the receiver side "the received and series / parallel-converted codeword are applied to both inputs to the register SR2 and inputs to the decoder D2. Since neither + Smax nor -Smax has been received, the decoder does not emit any activation signals on these outputs, which means that the segment determination value previously entered in the counter CM2 is entered in the code converter CRC in the unchanged state.As mentioned, the codeword is written, without polarity bit, also in the shift register SR2.To obtain from this register the signal originally received to the transmitter side, this register must be stepped back as many This corresponds so that in the first position in register SR2 the polarity of the signal is sensed, if this is a zero a signal is given to a first, inverting input on an AND circuit 03, which senses the number of zero bits preceding the additional ONE bit E. The circuit 05 receives at a second input signals from a system (not shown in the drawing) common to the system m clock signal generator. Upon activation, the circuit 05 emits a control signal which partly rises

Claims (2)

1. 7714964-9 shift register up one step for va; and one of the zero bits received before the ETT bit E, and changes the contents of the code converter CRC so that one (1) is subtracted from its written value for each received control signal. When the contents of the register SR2 are shifted two steps corresponding to the first two zeros in the received code word, the signal E is sensed, which is a logic one. The register outputs this one to the AND circuit 05, which is thereby blocked and no further control signals are output to the shift register or the code converter. The shift register now outputs the original amplitude code to the converter DA and the code converter CRC now outputs to the converter DA the segment code 5 originally transmitted from the converter AD, since the segment value 5 from the counter CM2 is reduced by two steps through the code conversion in the converter CRC. The polarity bit complements the transmitted codeword on a special input to the D / A converter. After the Q / A conversion, the original analog signal incoming to the transmitter is transmitted. CLAIM 1 'Method for reducing the need for the number of bits transmitted when transmitting PCM information, the data of which regarding the polarity, segment affiliation and amplitude of the signal are expressed, characterized in that only amplitude and polarity information is transmitted from the transmitter side. to the receiver side without segment code, and that information on segment affiliation is transmitted in the form of segment change information, whereby a selected upper limit value in the amplitude code word is sensed on the transmitter side to determine that transition to a higher segment is to take place, and that a selected lower limit value is sensed. in the amplitude code word has been undershot for a certain time to determine that the transition to a lower segment should take place, said limit values are transmitted to the receiver side and used on both transmitter and receiver side to generate count signals, the count signals are registered on both transmitter and receiver side to give a value as an expression c - increases the segment affiliation and with the help of the registered value a control signal is generated to increase or decrease the segment value of the transmitted signal. 2. A method according to claim 1, characterized in that on the transmitter side said upper and lower limit values are used to reduce or increase the amplitude value of the signal fed to the transmitter so that a normalized signal amplitude is obtained before transmission to the receiver, said limit values being used. is pressed on the receiver side to increase or decrease the gain of the signal emanating from the receiver. A method according to claim 1, characterized in that the signal received at the transmitter side is subjected to an analog-to-digital conversion for obtaining binary. codewords which indicate the polarity, segment affinity and amplitude of the signal, of said generated counting signals a temporary segment value is formed, this temporary. segment value is compared with the segment determination code obtained by the A / D conversion, whereby in the case the segment determination code is greater than the temporary segment value, said selected upper limit value is generated regardless of the current amplitude value 'and this upper limit value is used to increase the temporary segment value. with one and transmitted simultaneously to the receiver, while each time the segment determination code is lower than the temporary segment value, the Vamplit code word for transmission is shifted one step down so that the word is supplemented by a zero-bit, which. zero bits are transmitted before an extra one-bit inserted in the amplitude code word, and that the segment determination code is incremented by one, and that on the receiving side of the count signals. a segment value is formed which is output as a reset segment determination code which, when supplementary zero bits have been received, is also shifted as many positions as the number of obtained complementary zero bits, the content of the amplitude codeword being shifted back as many positions corresponding to the number of obtained complementary zeros. pieces . A method according to claim 1, characterized in that the maximum positive amplitude value (+ Smax) is used on both the transmitter and receiver side to directly cause transition to a higher segment, while for transition to lower segments on the transmitter side the condition must be met that a determined amplitude value has been undershot for a certain time together with the condition that the zero level value of the signal appears, and that when the said conditions are met, the negative maximum value (-Smax) is emitted as a control signal to the receiver for transition to lower segments. 5. A method according to claim 1, characterized in that transmission of the negative maximum amplitude value (-Smax) is effected by inverting the polarity bit in the occurring zero level signal (S0). 6. A method according to claim 11, characterized in that said determined amplitude value is half of the maximum amplitude value. 11 7711664-9 - 7 Method according to claim 2, characterized in that such a strong force as attenuation is changed by a factor of 2. 8 Device for performing methods for transmitting PCM information, the data of which regarding the signal polarity, segment affiliation and amplitude are expressible in the form of binary codewords, reducing the need for the number of transmitted bits, characterized in that it contains a decoder (DI) on the transmitter side to detect in the signals transmitted to the receiver side that a selected upper limit value in the amplitude code achieved, and to detect and determine by means of a time measuring circuit (CRA) that a selected lower limit value in the amplitude code word has been undershot for a certain time, in order to generate from said limit values a counting pulse or a counting down pulse, a counter (C respectively downwards of said counting pulses, so that it expresses the segment affiliation of the signals, the counter values constituting control signals for in ano the input means which are influenced by said control signals and in dependence on them effect increase and decrease of the segment affiliation of the transmitted signal and on the receiver side contain a decoder (D2) for detecting said selected limit values and for generating a positive or negative counting pulse therefrom, a counter (CM2) which is stepped upwards and downwards of said counting pulses, so that it expresses the segment affiliation of the received signals, the counter values constituting control signals for means included in the device which are influenced by said control signals and depending on these causes decrease and increase of the received signal. segment affiliation; Device according to claim 8, characterized in that it contains on the transmitter side an amplifier (F1) through which the signals input to the transmitter pass, and an analog-to-digital converter (AD) which converts the output signal of the amplifier into binary signals which indicate the amplitude of the incoming signal. and polarity, the control signals emanating from said counter (CMI) changing the gain of said amplifier in such a way that, when the counter steps up and down respectively, the gain decreases or increases by a certain factor, so that a normalized amplitude value is obtained at the output of the amplifier, and on the receiver side contains a digital / analog converter (DA) which converts the received signals into analog signals and feeds them to an amplifier (F2) through which the output signal of the receiver passes, the control signals obtained from the counter (CM2) changing the gain of said amplifier in such a way that when the counter is stepped up the respective downward gain is increased or decreased by a certain factor, so that the received normalized amplitude value in the amplifier is converted to the value originally input to the transmitter. Device according to claim 8, characterized in that it contains on the transmitter side an analog-to-digital converter (AD) which converts the incoming signal into binary codewords indicating the polarity, segment affiliation and nmplitude of said incoming signal, a comparison circuit (J) which on a number of inputs 7714964-9 _ '12 receives the segment determination code from the A / D converter through a code converter (ßkn) and compares the segment determination code with the control signals indicating the segment affiliation sent from said counter (CMI), and if the segment determination code is larger, the value from the counter CM1), outputs a control signal to a limit value circuit (C1-G5) for transmitting said upper limit value, and if the segment determination code is less than said value from the counter (CMI), outputs a control signal to an input of the code converter (CRB) for increment of the segment determination code fed from the A / D converter to the comparison circuit, and that said control signal to the code converter at the same time makes a control signal to a shift register (SRI) which contains the amplitude code from the A / O converter together with an extra one-bit E which is always transmitted together with the amplitude code word, said control signal causing a shift in the shift register so that for each control signal a zero-bit is transmitted before the amplitude code supplemented by said extra ~ one-bit, and on the receiving side contains a code converter (CRC) which receives control signals from said counter (CM2), and which at its outputs outputs the segment determination code to a digital / analog converter (DA) whose output signal constitutes the output signal of the receiver, a shift register (SR2) in which the received amplitude code word is stored together with said extra one-bit E, a logic circuit (05) which senses the number of zero bits preceding the extra one-bit the bit in the codeword stored in the shift register and for each of these zero bits a shift pulse emits partly to the shift register to shift the codeword one step upwards, partly to the said k odom converter (CRC) to change its setting in such a way that to the value of the counter (CM2) a unit for each shift pulse is subtracted to thereby provide a tcorrected segment word at the input of the D / Ä converter, while in the absence of nell- bits before the aforementioned extra one-bit, the 1nhå11 of the counter (GM2) constitutes the segment code word output to the D / A converter. Device according to claim 8, characterized in that said counter (CMI) is provided with a counting input and a counting down input, the counting input being connected to the decoder w (D1) directly to obtain a signal corresponding to the positive maximum value (+ Sm8x). , while the countdown input is connected to the output of a gate circuit (01), one input of which receives a signal corresponding to the zero level value (SO), and the other input of which receives a signal from said ten-measurement circuit (cnA) after said determined ten. Device according to claim 8, characterized in that for utilizing the zero level value as said lower limit value, on the transmitter side it contains a logic circuit (02) which at a first input receives said countdown pulse and at a second input receives the polarity bit of the simultaneously transmitted zero level signal by inverting the polarity of said polarity bit, converting the occurring zero level value to negative maximum value and transmitting it as a control signal to the receiver, and on the receiving side contains a logic circuit (Oh) which by inverting the polarity bit in the received negative maximum value said value to a zero level signal before the D / A conversion. Device according to claim 8, characterized in that it contains on the transmitter side a logic circuit (03) which, when the maximum negative amplitude value (-Smax) only appears as amplitude level without being assigned to segment change order, inverts the least significant bit in the amplitude codeword before transmission to the receiver. Device according to claim 8, characterized in that the said counter (CM2) included in the receiver is provided with a counting input and a counting down input, the counting input being connected to the decoder (D2) to obtain a signal corresponding to the maximum positive amplitude value (+ Smx ), while the countdown input is connected to the decoder (D2) to obtain the maximum negative amplitude value (-Smax). Device according to claim 10, characterized in that said limit value circuits C1-C5 consist of logic circuits whose first input each receives its bit in the amplitude code word from the outputs of said shift register (SR1), the second input of all logic circuits C1-CS receives the said control signal from the comparator J, so that, upon the occurrence of said control signal, a code word determined by said logic circuits is transmitted regardless of the contents of the shift register. _ PROMISED PUBLICATIONS: