CN116318143A

CN116318143A - Error calibration circuit for high-speed digital-to-analog converter

Info

Publication number: CN116318143A
Application number: CN202310165607.4A
Authority: CN
Inventors: 黄永恒; 王楠; 王浩南; 李承哲
Original assignee: Jiyiwei Semiconductor Shanghai Co ltd
Current assignee: Jiyiwei Semiconductor Shanghai Co ltd
Priority date: 2023-02-24
Filing date: 2023-02-24
Publication date: 2023-06-23

Abstract

The application discloses an error calibration circuit of a high-speed digital-to-analog converter. Comprising the following steps: the system comprises a transmitting end circuit, a serial-to-parallel conversion circuit, a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), a calibration circuit and a reference clock generation circuit which are sequentially connected, wherein the reference clock generation circuit outputs a reference clock to the analog-to-digital converter, the calibration circuit controls data types according to error calibration types, for different error calibration types, the calibration circuit calculates error calibration words according to the output of the analog-to-digital converter and outputs the error calibration words to the digital-to-analog converter to perform corresponding error calibration, and the calibration circuit obtains reference clock calibration words according to the sampling result of the rising edge of the output waveform of the analog-to-digital converter by the analog-to-digital converter and outputs the reference clock calibration words to the reference clock generation circuit; the sequence positioning process of the sub digital-to-analog converter is also included between the reference clock calibration and the phase delay error calibration. According to the digital-to-analog conversion circuit, a reasonable reference clock frequency and various calibration methods are utilized to realize a high-precision digital-to-analog conversion circuit through an ADC and DAC combination method.

Description

Error calibration circuit for high-speed digital-to-analog converter

Technical Field

The present disclosure relates to integrated circuit technology, and more particularly, to an error calibration circuit for a high-speed digital-to-analog converter.

Background

Digital-to-analog converters (DACs) are widely used in electronic systems. The digital circuitry processes and generates discrete digital signals that, if communicated over a channel, need to be converted to continuous analog signals and transmitted after processing by analog circuitry. The DAC input is a discrete digital signal, and the summed voltage signal is generated by the value (0 or 1) and weight of each digit,

the high-speed DAC is an indispensable component of a high-speed serial interface chip and an incoherent/coherent optical chip, and the sampling precision of the high-speed DAC directly determines the overall performance of the chip. There are increasing demands on the chip rate at present, however, high rate DACs suffer from various errors, severely degrading chip performance. In the current research in the academia and industry, some DAC itself is optimized, and more excellent materials or optimized processes are adopted, but engineering implementation difficulty and cost increase are brought. In general, there is currently no effective technique for calibrating for multiple errors in high speed DACs.

Disclosure of Invention

The present application aims to provide an error calibration circuit for a high-speed digital-to-analog converter, which realizes a high-precision digital-to-analog converter circuit by using a reasonable reference clock frequency and various calibration methods through an analog-to-digital converter (ADC) and DAC combination method.

The application discloses error calibration circuit of high-speed digital to analog converter includes: the digital-to-analog converter comprises a transmitting end circuit, a serial-to-parallel conversion circuit, a digital-to-analog converter, an analog-to-digital converter, a calibration circuit and a reference clock generation circuit which are sequentially connected, wherein the reference clock generation circuit outputs a reference clock to the analog-to-digital converter, the digital-to-analog converter comprises a plurality of sub digital-to-analog converters, the frequency division ratio of the reference clock is equal to the number of the sub digital-to-analog converters by any integer, the transmitting end circuit adopts the length of a sequence +0.5, the calibration circuit transmits a control signal to the transmitting end circuit according to an error calibration type and controls the data type transmitted by the transmitting end circuit to the serial-to-parallel conversion circuit, and for different error calibration types, the calibration circuit calculates an error calibration word according to the output of the analog-to-digital converter and outputs the corresponding error calibration, and the calibration circuit obtains a reference clock calibration word according to the sampling result of the rising edge of the output waveform of the digital-to the analog converter to the reference clock generation circuit;

the calibration process of the calibration circuit to the digital-to-analog converter is offset error calibration, proportional error calibration, reference clock calibration, phase delay error calibration and unit delay error calibration, wherein the sequential positioning process of the sub digital-to-analog converters is further included between the reference clock calibration and the phase delay error calibration.

In a preferred embodiment, the transmitting end circuit adopts a PRBS3, PRBS7 or PRBS9 sequence, the length of the PRBS3 sequence is 7, when the transmitting end circuit adopts the PRBS3 sequence, the number of the sub digital-analog converters is 4, the arbitrary integer is 4, and the frequency division ratio of the reference clock is 112.5T.

In a preferred embodiment, when the error calibration type is a bias error, the type of data sent by the sending end circuit is: the input of the sub digital-to-analog converter calibrated at present is the data of positive maximum and negative maximum orderly circulation, the input of other sub digital-to-analog converters is all 0, and the offset error calibration process of the calibration circuit comprises the following steps: calculating a target value according to the positive maximum and the negative maximum or register configuration; calculating a bias error; the bias error control word is updated.

In a preferred embodiment, when the error calibration type is a proportional error, the type of data sent by the transmitting-side circuit is: the input of the sub digital-to-analog converter calibrated at present is the data of positive maximum and negative maximum orderly circulation, the input of other sub digital-to-analog converters is all 0, and the proportional error calibration process of the calibration circuit comprises the following steps: calculating a target value according to the positive maximum and the negative maximum or register configuration; calculating a proportional error; the proportional error control word is updated.

In a preferred embodiment, the process of determining, by the calibration circuit, whether the data output by the analog-to-digital converter is positive or negative maximum includes: judging that one value is larger than a positive threshold value/smaller than a negative threshold value, if the value is positive maximum/negative maximum; judging that more than two values are larger than a positive threshold/smaller than a negative threshold, if the values are met, adding 1 to the positive threshold or subtracting 1 from the negative threshold; and judging that no value is larger than the positive threshold/smaller than the negative threshold, if the value is satisfied, adding 1 to the counter, and if the counter reaches the counting threshold, subtracting 1 from the positive threshold or adding 1 to the negative threshold.

In a preferred embodiment, when the error calibration type is reference clock calibration, the type of data sent by the sending end circuit is: the input of the sub digital-to-analog converter calibrated at present is the data with the positive maximum, and the input of the other sub digital-to-analog converters is the data with the negative maximum; and the calibration circuit adopts a dichotomy or a scanning method to process the sampling result of the rising edge of the output waveform of the digital-to-analog converter by the analog-to-digital converter to obtain the reference clock calibration word.

In a preferred embodiment, when the calibration circuit performs the sequential positioning process of the sub-digital-to-analog converters, the type of data sent by the sending end circuit is: the input of the sub digital-to-analog converter calibrated currently is PRBS3 sequence, the input of the other sub digital-to-analog converters is the data with the maximum negative, and the sub digital-to-analog converter sequential positioning process comprises: it is determined whether the first 1 is found and whether the subsequent 1 is found by 16, 8, 24 data in turn, and if so, it is locked which sub-digital-to-analog converter these 1 are from and which bit of data is PRBS3 and are denoted dac_idx and prbs_idx, respectively.

In a preferred embodiment, when the calibration circuit performs phase delay error calibration, the data type sent by the sending end circuit is a PRBS3 sequence, and the phase delay error calibration process of the calibration circuit includes: determining the position of a rising edge according to dac_idx and prbs_idx obtained in the sequential positioning process of the sub-digital-to-analog converters, and calculating a phase delay control word according to a formula hr (n+1) =hr (n) +g (Dr (n) -Vth), wherein hr (n+1) and hr (n) are phase delay control words at time n+1 and time n respectively, g is an adjustment rate, dr (n) is a sampling value of the rising edge at time n, and Vth is an offset value of register configuration.

In a preferred embodiment, when the calibration circuit performs unit delay error calibration, the data type sent by the sending end circuit is a PRBS3 sequence, and the unit delay error calibration process of the calibration circuit includes: determining the position of a falling edge according to dac_idx and prbs_idx obtained in the sequential positioning process of the sub-digital-to-analog converters, and calculating a unit delay control word according to a formula hf (n+1) =hf (n) +g (Df (n) -Vth), wherein hf (n+1) and hr (n) are unit delay control words at n+1 time and n time respectively, g is an adjustment rate, df (n) is a sampling value of the falling edge at n time, and Vth is an offset value of register configuration.

In a preferred embodiment, the method further comprises: and the positioning failure protection circuit is used for gradually adding 1 to the dac_idx obtained in the sequential positioning process of the sub digital-analog converters, gradually calculating the phase delay control word or the unit delay control word corresponding to each sub digital-analog converter, and selecting a group of phase delay control words or unit delay control words with the least number of saturated phase delay control words or unit delay control words if the saturated phase delay control words or the unit delay control words are arranged in a plurality of sub digital-analog converters obtained by each calculation.

In the embodiment of the application, the following beneficial effects are achieved:

1. by adopting a DAC and ADC combination method and utilizing reasonable reference clock frequency, a DAC calibration circuit is designed, and the calibration precision is high. The foreground calibration (calibration is performed before the chip is formally operated) has no influence on power consumption. Only one low-rate ADC and digital circuit are added, so that the area influence is small.

2. The sampling circuit is used for sampling the DAC output signal, and the digital circuit finishes the error calibration of the DAC according to the calibration method, including the calibration method of offset error, proportion error, phase delay error and unit delay error, the calibration method of the reference clock and the positioning method of the sub DAC sequence, thereby having comprehensive error type calibration and greatly improving the performance of the DAC.

3. And a protection circuit for sub DAC positioning failure is designed, so that the stability and the robustness of the system are improved.

In the present application, a number of technical features are described in the specification, and are distributed in each technical solution, which makes the specification too lengthy if all possible combinations of technical features (i.e. technical solutions) of the present application are to be listed. In order to avoid this problem, the technical features disclosed in the above summary of the present application, the technical features disclosed in the following embodiments and examples, and the technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (which should be regarded as having been described in the present specification) unless such a combination of technical features is technically impossible. For example, in one example, feature a+b+c is disclosed, in another example, feature a+b+d+e is disclosed, and features C and D are equivalent technical means that perform the same function, technically only by alternative use, and may not be adopted simultaneously, feature E may be technically combined with feature C, and then the solution of a+b+c+d should not be considered as already described because of technical impossibility, and the solution of a+b+c+e should be considered as already described.

Drawings

Fig. 1 is a schematic diagram of an error calibration circuit of a high-speed digital-to-analog converter according to one embodiment of the present application.

Fig. 2 is a diagram of DAC output waveforms and ADC sampling points in accordance with one embodiment of the present application.

Fig. 3 is a sampling relationship of an ADC and a DAC in an embodiment according to the application.

Fig. 4 is a schematic diagram of a DAC calibration procedure in an embodiment according to the application.

FIG. 5 is a schematic diagram of a bias error calibration procedure in accordance with one embodiment of the present application.

FIG. 6 is a schematic diagram of a proportional error calibration procedure in accordance with one embodiment of the present application.

Fig. 7 is a flow chart of a method for determining a positive maximum value according to an embodiment of the present application.

FIG. 8 is a flow chart diagram of a reference clock calibration method in accordance with one embodiment of the present application.

Fig. 9 is a flow diagram of a sub-DAC sequential positioning method according to an embodiment of the application.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be understood by those skilled in the art that the claimed invention may be practiced without these specific details and with various changes and modifications from the embodiments that follow.

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

One embodiment of the present application relates to an error calibration circuit of a high-speed digital-to-analog converter, whose structure is shown in fig. 1, comprising: a transmitting-side circuit 101, a serial-parallel conversion circuit 102, a digital-to-analog converter (DAC) 103, an analog-to-digital converter (ADC) 104, a calibration circuit 105 for the digital-to-analog converter, and a reference clock generation circuit 106, which are sequentially coupled. It will be appreciated that the digital-to-analog converter 104 is responsible for converting discrete digital signals to continuous analog signals and sending to analog circuitry at a later stage for processing or directly to receiver side circuitry via a channel. To achieve error calibration of a high-rate DAC, the present application contemplates a calibration circuit that combines a high-speed DAC and a high-speed analog-to-digital converter (ADC).

Specifically, the transmitting-end circuit 101 transmits different data types according to the control signal of the calibration circuit, and the different data types are suitable for calibration of different errors. The transmission data of the transmitting-side circuit 101 is sent to a digital-to-analog converter (DAC) 103 after passing through a serial-to-parallel conversion circuit 102, is sent to an analog-to-digital converter (ADC) 104 after being converted into an analog signal, is then converted into a digital signal, is sent to a calibration circuit 105 for calibration, and the output data of the ADC 104 is converted into parallel data (parallelism 4, not limited to 4) by a register and is sent to the calibration circuit 105. The reference clock generation circuit 106 generates a reference clock to the ADC 104 and serves as a sampling trigger signal for the ADC 104. The digital-to-analog converter calibration circuit 105 obtains a reference clock calibration word by analyzing the fed data and feeds the reference clock calibration word to the reference clock generation circuit 106, and obtains calibration words of offset error, proportional error, phase delay error, and unit delay error and feeds the calibration words to the DAC 103 for calibration.

In one embodiment, DAC 103 is comprised of a plurality of sub-digital-to-analog converters (sub-DACs) (e.g., four

sub-DACs

1, 2, 3, 4 may be employed) that are sampled sequentially to achieve a high rate DAC with a low speed sub-DAC.

The frequency division ratio of the reference clock is equal to the number of the sub digital-to-analog converters, an arbitrary integer is used for the transmitting end circuit, and the length of the adopted sequence is +0.5. In one embodiment, the sender-side circuitry employs a PRBS3, PRBS7, or PRBS9 sequence.

The sampling sequence shown in fig. 2 and 3 can be realized by designing reasonable data types of the transmitting end, the number of sub-DACs and the reference clock frequency. In practice, the relationship between the reference clock frequency and the number of sub-DACs needs to be satisfied: reference clock division ratio = number of sub-DACs x length of the data sequence of the transmitting circuit m+0.5, where M is any integer. For example, the transmitting end adopts PRBS3 sequence (pseudo-random sequence with period of 7, 0010111 or 0100111), the number of sub-DACs is 4, and the reference clock frequency is 112.5T. Then the adc 104 may sample the output of one DAC 103 per interval 112.5t. Assuming that the input of DAC 103 is 1011 (each bit corresponds to the input of sub-DAC 1, sub-DAC 2, sub-DAC 3, sub-DAC 4, respectively), the output analog voltage waveform of DAC 103 is shown by the curve of fig. 2, and each sampling point of ADC 104 is shifted forward by 0.5UI on the curve, as shown by the dots in fig. 2. Fig. 3 further shows the sampling relationship between the ADC and DAC, and the ADC can sample completely to obtain the PRBS3 sequence points and the 0.5UI points between the sequences.

Fig. 4 is a schematic diagram of a DAC calibration procedure in an embodiment according to the application. The calibration process of the calibration circuit to the digital-to-analog converter is bias error calibration, proportion error calibration, reference clock calibration, phase delay error calibration and unit delay error calibration. And a sub digital-to-analog converter sequential positioning process is further included between the reference clock calibration and the phase delay error calibration. FIG. 5 is a schematic diagram of a bias error calibration procedure in accordance with one embodiment of the present application. In order to calibrate for different errors, the transmitting end needs to transmit different types of data, as shown in table 1.

Table 1 data types sent by the sender circuit in different calibration flows

In one embodiment, when the error calibration type is a bias error, the type of data sent by the sending end circuit is: the inputs of the sub digital-to-analog converters calibrated at present are the data of positive maximum and negative maximum orderly circulation, and the inputs of other sub digital-to-analog converters are all 0. The offset error calibration process of the calibration circuit comprises the following steps: calculating a target value according to the positive maximum and the negative maximum or register configuration; calculating a bias error; updating the bias error control word; and judging whether all sub-DACs are calibrated, if so, ending, and if not, switching the sub-DACs and the data of the transmitting end. FIG. 5 is a schematic diagram of a bias error calibration procedure in accordance with one embodiment of the present application.

In one embodiment, when the error calibration type is a proportional error, the type of data sent by the sending end circuit is: the inputs of the sub digital-to-analog converters calibrated at present are the data of positive maximum and negative maximum orderly circulation, and the inputs of other sub digital-to-analog converters are all 0. The proportional error calibration process of the calibration circuit comprises the following steps: calculating a target value according to the positive maximum and the negative maximum or register configuration; calculating a proportional error; updating a proportional error control word; and judging whether all sub-DACs are calibrated, if so, ending, and if not, switching the sub-DACs and the data of the transmitting end. FIG. 6 is a schematic diagram of a proportional error calibration procedure in accordance with one embodiment of the present application.

In practice, it is mentioned above that the positive and negative maxima need to be determined by an algorithm whether there are positive and negative maxima in the 4 data received per beat, as shown in fig. 7. Fig. 7 shows a method for judging whether each beat has a positive maximum value by using a positive threshold, and similarly, a negative threshold can be obtained by using the same method, or can be obtained by using a positive threshold plus a register configuration value.

Specifically, the process of the calibration circuit determining whether the data output by the analog-to-digital converter is positive maximum or negative maximum includes: judging that one value is larger than a positive threshold value/smaller than a negative threshold value, if the value is positive maximum/negative maximum; judging that more than two values are larger than a positive threshold/smaller than a negative threshold, if the values are met, adding 1 to the positive threshold or subtracting 1 from the negative threshold; and judging that no value is larger than the positive threshold/smaller than the negative threshold, if the value is satisfied, adding 1 to the counter, and if the counter reaches the counting threshold, subtracting 1 from the positive threshold or adding 1 to the negative threshold.

The reference clock is used to trigger the ADC 104 to sample, and if the reference clock deviates too far from the data center point, the ADC 104 cannot sample an accurate signal, which is equivalent to a large delay error on the DAC 103. The reference clock calibration method finds the optimal control word by sampling the rising edge and using a dichotomy or a scanning method.

In one embodiment, when the error calibration type is reference clock calibration, the data type sent by the sending end circuit is: the inputs of the sub-digital-to-analog converters calibrated currently are the positive maximum data, and the inputs of the other sub-digital-to-analog converters are all the negative maximum data. And the calibration circuit adopts a dichotomy or a scanning method to process the sampling result of the rising edge of the output waveform of the digital-to-analog converter by the analog-to-digital converter to obtain the reference clock calibration word.

FIG. 8 is a flow chart diagram of a reference clock calibration method in accordance with one embodiment of the present application. Specifically, firstly finding the maximum value, obtaining the value of the rising edge, sampling for a plurality of times to obtain the average value, judging whether all sub-DACs are calibrated, if not, switching the sub-DACs and the data of the transmitting end, if yes, judging the current state, finding the control word by using a dichotomy or a scanning method, judging whether the stop condition is reached, if yes, ending, and if not, switching the control word.

In one embodiment, when the calibration circuit performs the sequential positioning process of the sub-digital-to-analog converters, the type of data sent by the sending end circuit is: the inputs of the sub-digital-to-analog converters currently calibrated are PRBS3 sequences, and the inputs of the other sub-digital-to-analog converters are all the most negative data. The sub-digital-to-analog converter sequence positioning process comprises the following steps: it is determined whether the first 1 is found and whether the subsequent 1 is found by 16, 8, 24 data in turn, and if so, it is locked which sub-digital-to-analog converter these 1 are from and which bit of data is PRBS3 and are denoted dac_idx and prbs_idx, respectively.

As described above, unless a particular data type is used (only one sub-DAC has a value), under a normal PRBS3 sequence, we cannot know from which sub-DAC the first data received in the calibration circuit originates, and thus sub-DAC sequential positioning is required. As shown in fig. 9, the data type transmitted by the transmitting-side circuit at this time is data in which 1 sub-DAC is PRBS3, and the other sub-DACs are all negative maximum. We therefore decide on the received data, 1 above the positive threshold and 0 below. The data received by the valued sub-DACs should be in the order 0010111 or 0100111. Taking 0010111 as an example, the circuit starts counting the first time a 1 is received, if the first 1 in 0010111 is received, then when the 16 th data (e.g., 4 sub-DACs) is received, the data should be the second 1 in 0010111, and so on to determine the next plurality of 1's, the count threshold of which is 16, 8, 24, 16, 8, … …. The design shown in FIG. 9 is that the 5 th 1 found is considered to have locked the sequence. The circuit can now determine which sub-DAC samples the four data fed into the calibration circuit were obtained and which bit of data in the PRBS3 sequence. The results, named dac_idx and prbs_idx, respectively, will be used in the phase delay error and unit delay error calibration.

In one embodiment, when the calibration circuit performs phase delay error calibration, the data type sent by the sending end circuit is a PRBS3 sequence, and the phase delay error calibration process of the calibration circuit includes: determining the position of a rising edge according to dac_idx and prbs_idx obtained in the sequential positioning process of the sub-digital-to-analog converters, and calculating a phase delay control word according to a formula hr (n+1) =hr (n) +g (Dr (n) -Vth), wherein hr (n+1) and hr (n) are phase delay control words at time n+1 and time n respectively, g is an adjustment rate, dr (n) is a sampling value of the rising edge at time n, and Vth is an offset value of register configuration.

In one embodiment, when the calibration circuit performs unit delay error calibration, the data type sent by the sending end circuit is a PRBS3 sequence, and the unit delay error calibration process of the calibration circuit includes: determining the position of a falling edge according to dac_idx and prbs_idx obtained in the sequential positioning process of the sub-digital-to-analog converters, and calculating a unit delay control word according to a formula hf (n+1) =hf (n) +g (Df (n) -Vth), wherein hf (n+1) and hr (n) are unit delay control words at n+1 time and n time respectively, g is an adjustment rate, df (n) is a sampling value of the falling edge at n time, and Vth is an offset value of register configuration.

For each received data (sent by the ADC) by the calibration circuit, it is noted with two values (dac_idx, prbs_idx), dac_idx indicating which sub-DAC this data is sampled to, and prbs_idx indicating which data in the PRBS3 sequence this data is. When prbs_idx is the rising edge (between the second and third numbers, between the fourth and fifth numbers) and the falling edge (between the third and fourth numbers, between the seventh and first numbers) of the known PRBS3 sequence (0010111), this number is the number we want to find. The calibration circuit calculates the error based on this number and then updates the control word for the corresponding sub-DAC (each sub-DAC having an independent control word) based on DAC idx.

The error control word is obtained by sampling the calibration errors of the rising edge and the falling edge, namely the phase delay and the unit delay, sending the errors to an updating circuit and utilizing an LMS algorithm. Meanwhile, the positions of the rising edge and the falling edge are directly obtained by utilizing the results in the sub-DAC sequential positioning method. Since the phase delay and the unit delay affect the values of the rising edge and the falling edge at the same time, but affect the opposite directions, and the output control words actually control the rising edge and the falling edge, the calculation methods of the two control words are as shown in formulas (1) and (2):

rising edge: hr (n+1) =hr (n) +g (Dr (n) -Vth) (1)

Falling edge: hf (n+1) =hf (n) +g×df (n) -Vth) (2)

Where hr (n+1) and hr (n) are rising edge control words at times n+1 and n, respectively, and hf (n+1) and hf (n) are falling edge control words at times n+1 and n, respectively. g is an adjustment rate that can be adaptively adjusted according to duration. Dr (n) and Df (n) are sampling values of a rising edge and a falling edge at time n, respectively, and Vth is an offset value of the register configuration.

In one embodiment, the calibration circuit further comprises: and the positioning failure protection circuit is used for gradually adding 1 to the dac_idx obtained in the sequential positioning process of the sub digital-analog converters, gradually calculating the phase delay control word or the unit delay control word corresponding to each sub digital-analog converter, and selecting a group of phase delay control words or unit delay control words with the least number of saturated phase delay control words or unit delay control words if the saturated phase delay control words or the unit delay control words are arranged in a plurality of sub digital-analog converters obtained by each calculation.

The sub-DAC sequential positioning determines the results of the phase delay calibration and the unit delay calibration, so a protection circuit is required to be designed, and the subsequent process can still be completed correctly when the sub-DAC positioning fails. When the skew saturation is detected, the dac_idx sequence obtained by the sub-DAC positioning method is added with 1, the prbs_idx (namely the PRBS sequence) is kept unchanged, and the calibration of the phase delay error and the unit delay error is carried out again. Repeating for 4 times (sub DAC number) at most, if saturation occurs in 4 times, selecting the time with the least saturation number as the final output result.

It should be noted that in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, and two cases are included: the act is performed solely on the basis of the element and is performed on the basis of the element and other elements. Multiple, etc. expressions include 2, 2 times, 2, and 2 or more, 2 or more times, 2 or more.

The term "coupled to" and its derivatives may be used herein. "coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are in indirect contact with each other, but still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between elements that are referred to as being coupled to each other.

This specification includes combinations of the various embodiments described herein. Separate references to embodiments (e.g., "one embodiment" or "some embodiments" or "preferred embodiments") do not necessarily refer to the same embodiment; however, unless indicated as mutually exclusive or as would be apparent to one of skill in the art, the embodiments are not mutually exclusive. It should be noted that the term "or" is used in this specification in a non-exclusive sense unless the context clearly indicates otherwise or requires otherwise.

All documents mentioned in the present specification are considered to be included in the disclosure of the present application as a whole, so that they may be regarded as a basis for modification if necessary. Furthermore, it should be understood that the foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, or the like, which is within the spirit and principles of one or more embodiments of the present disclosure, is intended to be included within the scope of one or more embodiments of the present disclosure.

Claims

1. An error correction circuit for a high-speed digital-to-analog converter, comprising: the digital-to-analog converter comprises a transmitting end circuit, a serial-to-parallel conversion circuit, a digital-to-analog converter, an analog-to-digital converter, a calibration circuit and a reference clock generation circuit which are sequentially connected, wherein the reference clock generation circuit outputs a reference clock to the analog-to-digital converter, the digital-to-analog converter comprises a plurality of sub digital-to-analog converters, the frequency division ratio of the reference clock is equal to the number of the sub digital-to-analog converters by any integer, the transmitting end circuit adopts the length of a sequence +0.5, the calibration circuit transmits a control signal to the transmitting end circuit according to an error calibration type and controls the data type transmitted by the transmitting end circuit to the serial-to-parallel conversion circuit, and for different error calibration types, the calibration circuit calculates an error calibration word according to the output of the analog-to-digital converter and outputs the corresponding error calibration, and the calibration circuit obtains a reference clock calibration word according to the sampling result of the rising edge of the output waveform of the digital-to the analog converter to the reference clock generation circuit;

2. The circuit of claim 1, wherein the transmitter circuit employs a PRBS3, PRBS7, or PRBS9 sequence, the length of the PRBS3 sequence is 7, the number of the sub digital-to-analog converters is 4 when the transmitter circuit employs a PRBS3 sequence, the arbitrary integer is 4, and the frequency division ratio of the reference clock is 112.5T.

3. The circuit of claim 1, wherein when the error calibration type is a bias error, the data type sent by the transmitting circuit is: the input of the sub digital-to-analog converter calibrated at present is the data of positive maximum and negative maximum orderly circulation, the input of other sub digital-to-analog converters is all 0, and the offset error calibration process of the calibration circuit comprises the following steps: calculating a target value according to the positive maximum and the negative maximum or register configuration; calculating a bias error; the bias error control word is updated.

4. The circuit of claim 1, wherein when the error calibration type is a proportional error, the data type transmitted by the transmitting-side circuit is: the input of the sub digital-to-analog converter calibrated at present is the data of positive maximum and negative maximum orderly circulation, the input of other sub digital-to-analog converters is all 0, and the proportional error calibration process of the calibration circuit comprises the following steps: calculating a target value according to the positive maximum and the negative maximum or register configuration; calculating a proportional error; the proportional error control word is updated.

5. The circuit of claim 3 or 4, wherein the calibration circuit determining whether the data output by the analog-to-digital converter is positive or negative maximum comprises: judging that one value is larger than a positive threshold value/smaller than a negative threshold value, if the value is positive maximum/negative maximum; judging that more than two values are larger than a positive threshold/smaller than a negative threshold, if the values are met, adding 1 to the positive threshold or subtracting 1 from the negative threshold; and judging that no value is larger than the positive threshold/smaller than the negative threshold, if the value is satisfied, adding 1 to the counter, and if the counter reaches the counting threshold, subtracting 1 from the positive threshold or adding 1 to the negative threshold.

6. The circuit of claim 1, wherein when the error calibration type is a reference clock calibration, the data type transmitted by the transmitting circuit is: the input of the sub digital-to-analog converter calibrated at present is the data with the positive maximum, and the input of the other sub digital-to-analog converters is the data with the negative maximum; and the calibration circuit adopts a dichotomy or a scanning method to process the sampling result of the rising edge of the output waveform of the digital-to-analog converter by the analog-to-digital converter to obtain the reference clock calibration word.

7. The circuit of claim 1, wherein the type of data transmitted by the transmitting circuit when the calibration circuit performs the sub-digital-to-analog converter sequential positioning process is: the input of the sub digital-to-analog converter calibrated currently is PRBS3 sequence, the input of the other sub digital-to-analog converters is the data with the maximum negative, and the sub digital-to-analog converter sequential positioning process comprises: it is determined whether the first 1 is found and whether the subsequent 1 is found by 16, 8, 24 data in turn, and if so, it is locked which sub-digital-to-analog converter these 1 are from and which bit of data is PRBS3 and are denoted dac_idx and prbs_idx, respectively.

8. The circuit of claim 7, wherein when the calibration circuit performs phase delay error calibration, the data type sent by the transmitting-side circuit is a PRBS3 sequence, and the phase delay error calibration process of the calibration circuit includes: determining the position of a rising edge according to dac_idx and prbs_idx obtained in the sequential positioning process of the sub-digital-to-analog converters, and calculating a phase delay control word according to a formula hr (n+1) =hr (n) +g (Dr (n) -Vth), wherein hr (n+1) and hr (n) are phase delay control words at time n+1 and time n respectively, g is an adjustment rate, dr (n) is a sampling value of the rising edge at time n, and Vth is an offset value of register configuration.

9. The circuit of claim 7, wherein when the calibration circuit performs unit delay error calibration, the data type sent by the transmitting circuit is a PRBS3 sequence, and the unit delay error calibration process of the calibration circuit includes: determining the position of a falling edge according to dac_idx and prbs_idx obtained in the sequential positioning process of the sub-digital-to-analog converters, and calculating a unit delay control word according to a formula hf (n+1) =hf (n) +g (Df (n) -Vth), wherein hf (n+1) and hr (n) are unit delay control words at n+1 time and n time respectively, g is an adjustment rate, df (n) is a sampling value of the falling edge at n time, and Vth is an offset value of register configuration.

10. The circuit of claim 8 or 9, further comprising: and the positioning failure protection circuit is used for gradually adding 1 to the dac_idx obtained in the sequential positioning process of the sub digital-analog converters, gradually calculating the phase delay control word or the unit delay control word corresponding to each sub digital-analog converter, and selecting a group of phase delay control words or unit delay control words with the least number of saturated phase delay control words or unit delay control words if the saturated phase delay control words or the unit delay control words are arranged in a plurality of sub digital-analog converters obtained by each calculation.