SE398423B - PROCEDURE AND DEVICE FOR CREATING THE N-FOLDING FACTOR OF A NORMAL FREQUENCY - Google Patents

PROCEDURE AND DEVICE FOR CREATING THE N-FOLDING FACTOR OF A NORMAL FREQUENCY

Info

Publication number
SE398423B
SE398423B SE7415990A SE7415990A SE398423B SE 398423 B SE398423 B SE 398423B SE 7415990 A SE7415990 A SE 7415990A SE 7415990 A SE7415990 A SE 7415990A SE 398423 B SE398423 B SE 398423B
Authority
SE
Sweden
Prior art keywords
creating
procedure
normal frequency
folding factor
folding
Prior art date
Application number
SE7415990A
Other languages
Swedish (sv)
Other versions
SE7415990L (en
Inventor
R Witschi
Original Assignee
Hasler Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hasler Ag filed Critical Hasler Ag
Publication of SE7415990L publication Critical patent/SE7415990L/xx
Publication of SE398423B publication Critical patent/SE398423B/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/191—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using at least two different signals from the frequency divider or the counter for determining the time difference
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/18—Temporarily disabling, deactivating or stopping the frequency counter or divider
SE7415990A 1973-12-20 1974-12-19 PROCEDURE AND DEVICE FOR CREATING THE N-FOLDING FACTOR OF A NORMAL FREQUENCY SE398423B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH1788973A CH566089A5 (en) 1973-12-20 1973-12-20

Publications (2)

Publication Number Publication Date
SE7415990L SE7415990L (en) 1975-06-23
SE398423B true SE398423B (en) 1977-12-19

Family

ID=4428858

Family Applications (1)

Application Number Title Priority Date Filing Date
SE7415990A SE398423B (en) 1973-12-20 1974-12-19 PROCEDURE AND DEVICE FOR CREATING THE N-FOLDING FACTOR OF A NORMAL FREQUENCY

Country Status (7)

Country Link
JP (1) JPS50115458A (en)
CH (1) CH566089A5 (en)
DE (1) DE2456742A1 (en)
GB (1) GB1452559A (en)
IT (1) IT1032558B (en)
NL (1) NL7416281A (en)
SE (1) SE398423B (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE7411960L (en) * 1974-09-24 1976-03-25 Fabriker As Haustrups METHOD OF MANUFACTURING CONTAINERS LIKE POLYESTER BOTTLES OR CANS
US4290028A (en) * 1979-07-30 1981-09-15 International Telephone And Telegraph Corporation High speed phase locked loop frequency synthesizer
JPS5720052A (en) 1980-07-11 1982-02-02 Toshiba Corp Input data synchronizing circuit
JPS6051312B2 (en) * 1981-03-20 1985-11-13 日本ビクター株式会社 Horizontal scanning frequency multiplier circuit
US4389622A (en) * 1981-09-28 1983-06-21 Honeywell Inc. System for preventing transient induced errors in phase locked loop
JPS58191573A (en) * 1982-05-06 1983-11-08 Victor Co Of Japan Ltd Horizontal scanning frequency multiplier circuit
GB2132042B (en) * 1982-12-15 1986-09-24 British Broadcasting Corp Frequency and timing sources
FR2710806B1 (en) * 1993-09-28 1995-11-10 France Telecom Frequency control device.
US5410368A (en) * 1993-12-29 1995-04-25 Zenith Electronics Corp. Carrier acquisition by applying substitute pilot to a synchronous demodulator during a start up interval
IT1278538B1 (en) * 1995-12-20 1997-11-24 Sits Soc It Telecom Siemens PROCEDURE FOR MAINTAINING LOCK IN A DIGITAL PLL DURING ANY TRANSIENT INTERRUPTIONS OF THE SYNCHRONIZING SIGNAL
WO1999013582A1 (en) * 1997-09-09 1999-03-18 Advanced Fibre Communications, Inc. Perturbation tolerant digital phase-locked loop employing phase-frequency detector
EP2158677B1 (en) 2007-06-14 2018-05-30 NXP USA, Inc. Circuit arrangement for filtering unwanted signals from a clock signal, processing system and method of filtering unwanted signals from a clock signal
US8552764B2 (en) 2009-01-05 2013-10-08 Freescale Semiconductor, Inc. Clock glitch detection circuit
WO2010112969A1 (en) 2009-03-31 2010-10-07 Freescale Semiconductor, Inc. Clock glitch detection

Also Published As

Publication number Publication date
JPS50115458A (en) 1975-09-10
IT1032558B (en) 1979-06-20
DE2456742A1 (en) 1975-06-26
CH566089A5 (en) 1975-08-29
GB1452559A (en) 1976-10-13
NL7416281A (en) 1975-06-24
SE7415990L (en) 1975-06-23

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