SE329029B - - Google Patents

Info

Publication number
SE329029B
SE329029B SE15272/66A SE1527266A SE329029B SE 329029 B SE329029 B SE 329029B SE 15272/66 A SE15272/66 A SE 15272/66A SE 1527266 A SE1527266 A SE 1527266A SE 329029 B SE329029 B SE 329029B
Authority
SE
Sweden
Application number
SE15272/66A
Inventor
J Barlow
R Barton
J Belt
J Wiener
A Mclagan
L Rakoczi
M Torfeh
C Frasier
L Hittel
Original Assignee
Gen Electric
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gen Electric filed Critical Gen Electric
Publication of SE329029B publication Critical patent/SE329029B/xx

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/52Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1657Access to multiple memories
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663Access to shared memory
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18Handling requests for interconnection or transfer for access to memory bus based on priority control
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)
  • Communication Control (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
  • General Factory Administration (AREA)
  • Devices For Executing Special Programs (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
SE15272/66A 1965-11-16 1966-11-08 SE329029B (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US50816865A 1965-11-16 1965-11-16

Publications (1)

Publication Number Publication Date
SE329029B true SE329029B (de) 1970-09-28

Family

ID=24021665

Family Applications (1)

Application Number Title Priority Date Filing Date
SE15272/66A SE329029B (de) 1965-11-16 1966-11-08

Country Status (8)

Country Link
US (1) US3487373A (de)
JP (1) JPS4943819B1 (de)
CH (2) CH483061A (de)
DE (2) DE1524127B2 (de)
FR (4) FR1514164A (de)
GB (3) GB1170587A (de)
NL (3) NL6616126A (de)
SE (1) SE329029B (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3569938A (en) * 1967-12-20 1971-03-09 Ibm Storage manager
JPS5169498U (de) * 1974-11-28 1976-06-01
JPS5356934U (de) * 1976-10-16 1978-05-16
US4149243A (en) * 1977-10-20 1979-04-10 International Business Machines Corporation Distributed control architecture with post and wait logic
EP0055374B1 (de) * 1980-12-29 1988-08-24 International Business Machines Corporation Datenverarbeitungsanlage mit einem Eingangs-Ausgangs-Verarbeitungskomplex
US4550368A (en) * 1982-07-02 1985-10-29 Sun Microsystems, Inc. High-speed memory and memory management system
US4539637A (en) * 1982-08-26 1985-09-03 At&T Bell Laboratories Method and apparatus for handling interprocessor calls in a multiprocessor system
US4710868A (en) * 1984-06-29 1987-12-01 International Business Machines Corporation Interconnect scheme for shared memory local networks
US4991084A (en) * 1988-02-05 1991-02-05 International Business Machines Corporation N×M round robin order arbitrating switching matrix system
EP0730237A1 (de) * 1995-02-28 1996-09-04 Nec Corporation Multiprozessorsystem mit virtuell adressierbaren Kommunikationsregistern und Steuerungsverfahren

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL125576C (de) * 1957-01-11 1900-01-01
US3292151A (en) * 1962-06-04 1966-12-13 Ibm Memory expansion
US3270324A (en) * 1963-01-07 1966-08-30 Ibm Means of address distribution
US3311888A (en) * 1963-04-12 1967-03-28 Ibm Method and apparatus for addressing a memory
US3311887A (en) * 1963-04-12 1967-03-28 Ibm File memory system with key to address transformation apparatus
DE1218761B (de) * 1963-07-19 1966-06-08 International Business Machines Corporation, Armonk, N. Y. (V. St. A.) Datenspeidbereinrichtung
GB1051786A (de) * 1963-10-23 1900-01-01
US3323109A (en) * 1963-12-30 1967-05-30 North American Aviation Inc Multiple computer-multiple memory system

Also Published As

Publication number Publication date
GB1170434A (en) 1969-11-12
DE1524127A1 (de) 1970-01-08
US3487373A (en) 1969-12-30
NL6616125A (de) 1967-05-17
JPS4943819B1 (de) 1974-11-25
DE1524126A1 (de) 1970-06-25
FR1513353A (fr) 1968-02-16
DE1524127B2 (de) 1976-02-26
GB1170587A (en) 1969-11-12
GB1170586A (en) 1969-11-12
FR1513352A (fr) 1968-02-16
NL6616124A (de) 1967-05-17
FR1514164A (fr) 1968-02-23
CH495584A (de) 1970-08-31
CH483061A (de) 1969-12-15
FR1513354A (fr) 1968-02-16
NL6616126A (de) 1967-05-17

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