RU79361U1 - DEVICE OF ITERATIVE DECODING OF BLOCK TURBOCODES - Google Patents

Abstract

The present utility model relates to an error correction device in a digital radio communication system and, in particular, to an iterative decoding device of block turbo codes. The device consists of a first memory in which the input values received from the demodulator, the first adder, the second adder, the SISO decoder for SISO decoding of the codes C1 and C2, the decision block for deciding the transmitted codeword from the soft output values received from SISO are stored a decoder, a third memory for storing a codeword, the decision on which was made in the decision block, a second memory for storing correction values received from the second adder, a normalization circuit for multiplying by rrektiruyuschih values obtained from the second memory to the normalization coefficients α. The technical result achieved by the implementation of the utility model is to reduce the complexity of the hardware implementation of the device with constant decoding efficiency. 6 ill.

Description

The present utility model relates to an error correction device in a digital radio communication system and, in particular, to an iterative decoding device of block turbo codes.

Turbo codes were first presented in [1]. The development of turbo codes is developing in two directions: convolutional turbo codes formed by parallel connection of two convolutional encoders, and block turbo codes formed by serial connection of two block encoders.

Figure 1 presents a diagram of the construction of block turbo code. The block turbo code is displayed in the form of a rectangle and is based on two systematic codes: C1 (N1, K1) and C2 (N2, K2), the code words of which are located vertically and horizontally, respectively. The total information capacity of the code is K = K1 · K2, and the duration of the code is N = N1 · N2. Block 1 contains information symbols, and blocks 2, 3, and 4 contain verification symbols.

To decode turbo codes, the concept of the so-called iterative decoding, first described in [2], is used. The basis of an iterative decoder of turbo block codes is a decoder with a soft input and a soft output (Soft Input Soft Output - SISO), which is sequentially used to decode vertical and horizontal composite codes. During operation of the turbo decoder, SISO schemes for decoding horizontal and vertical composite codes exchange external information with each other, improving the probability of correct decoding with each iteration. The end of the decoding process occurs after performing a given number of iterations. After completion of the last iteration, a tough decision is made about the transmitted information symbols, which is the output of the iterative decoding device of block turbo codes.

At the first iteration, from the demodulator to the input of the SISO decoder of the vertical codes, estimates (soft decisions) with respect to the symbols are received. At the output of the vertical code decoding scheme, soft decisions are formed with respect to

characters, which are then used to form input information for a horizontal code decoding scheme. At subsequent iterations of decoding, soft decisions are generated at the input of SISO decoders, which are formed according to the results of SISO decoding at the previous iteration.

SISO decoding of composite codes C1 and C2 is based on the calculation of the logarithm of the ratio of posterior probabilities of binary symbols of the code words C1 and C2, whose sign determines the value of the decoded bit, and the module determines the reliability of this value.

The closest in technical essence and the achieved effect is an iterative decoding device for block turbo codes described in patent EP 1282237 A2, Н03М 13/29 dated February 5, 2003 "Decoding method and decoding apparatus of product code" [3].

The prototype patent [3] describes a device for iterative decoding of block turbo codes formed by composite block codes C1 and C2. An iterative decoding device for block turbo codes consists of a first memory, a first adder, a SISO decoder, a second adder, a decision block, a third memory, and a normalization circuit. SISO decoder includes series-connected: Chase algorithm decoding unit, likelihood codeword likelihood calculation unit, and soft output decision unit.

The values received from the demodulator are stored in the first memory. To decode the C1 code (whose code words are located vertically) or the C2 code (whose code words are horizontally), the correction value stored at the specified address in the second memory is read from it and fed to the first adder after passing through the normalization circuit. The first adder adds up the received value stored at the given address in the first memory and the correction value received from the normalization circuit, thus generating soft input values. At the first iteration of decoding, the correction values are equal to zero, therefore, the first adder outputs the values received from the demodulator to the SISO decoder without changes.

Soft input values generated by the first adder are fed to the SISO decoder. Having received soft input values corresponding to the code words of code C1 and code C2, the SISO decoder starts decoding.

The SISO decoder consists of a Chase algorithm decoding unit that generates hypothetical error vectors from a soft input vector, a likelihood code calculation unit for hypothetical code words, and a soft output value calculation unit.

The Chase algorithm decoding unit generates hypothetical error vectors from a soft input vector. Hypothetical error vectors generated in the Chase decoding block are fed to the likelihood calculation block of hypothetical codewords. The likelihood code calculating unit of hypothetical codewords calculates hypothetical codewords and scalar products between the soft input vector and hypothetical codewords, and selects a hypothetical codeword giving the maximum scalar product. Scalar products and the most probable codeword are fed to the soft output value calculation unit.

The soft output value calculating unit generates soft output values, which are outputs of the SISO decoder.

Soft output values generated in the SISO decoder soft output value calculation unit are supplied to the decision unit and the second adder. In the case of transition to the next decoding iteration, the second adder subtracts the received value from the soft output value to calculate the correction value, which is stored in the given address of the second memory. In the case of decoding, the decision block makes a tough decision about the transmitted codeword from the soft output values of the SISO decoder and stores it in the specified address of the third memory. Hard decisions are stored in the third memory and are the output of the iterative decoding device of block turbo codes.

The disadvantage of the device described in the patent prototype [3] is the complexity of the hardware implementation. It should be noted that the complexity of the device

decoding of block turbo codes is mainly determined by the complexity of the SISO decoder.

The complexity of the SISO decoder described in the prototype patent is due to the use of soft outputs for calculating hypothetical code words, their likelihood and the maximum likelihood code word. While in the Chase decoder [4], hard solutions for the elements of the input vector are calculated as intermediate parameters, hypothetical error vectors and their weights sufficient to calculate the soft SISO decoder vectors.

The purpose of this utility model is to create an iterative decoding device for block turbo codes, which has less complexity in hardware implementation, with constant decoding efficiency.

To achieve this technical result, it is proposed to use the intermediate parameters obtained in the Chase decoder to calculate the soft outputs of the SISO decoder.

The technical result is achieved in that the device for iterative decoding of block turbo codes consists of a first memory, data from which are supplied to the first input of the first adder and the inverse first input of the second adder, the output of the first adder is connected to the input of the SISO decoder, the output of which is connected to the second input of the second adder and with the input of the decision block, the output of which is connected to the third memory, the output of the second adder is connected to the input of the second memory, and the data from the output of the second memory is fed to the circuit normalization, the output of which is connected to the second input of the first adder, the SISO decoder consists of a decoding block according to the Chase algorithm, the output of which is connected to the input of the soft output value calculation unit, characterized in that the likelihood of the calculation of likelihood codewords from the SISO decoder is also excluded from the decoding unit Chase algorithm outputs hard solutions calculated at intermediate stages, hypothetical error vectors and their weights for feeding soft solutions directly to the computer.

The essence of the utility model is explained below. Figure 2 presents a block diagram of a digital radio communication system using turbo coding. System consists

from the encoder of the turbocode 201, in which the input data is encoded, of a modulator 202 for converting the encoded data into a signal that will be transmitted through a communication channel, a communication channel 203, a demodulator 204 that demodulates a received signal transmitted through a communication channel 203, and a turbocode decoder 205 which decodes the data received from demodulator 204. Encoder 201 and modulator 202 constitute a transmitter, and demodulator 204 and decoder 205 constitute a receiver.

Next, we describe the operation of the system shown in figure 2. The input bit information is encoded in the encoder turbocode 201.

The turbo encoder 201 is connected to a modulator 202, in which the encoded data is converted into a signal transmitted via a communication channel 203. A signal received through a communication channel 203 is supplied to a receiver demodulator 204.

The demodulator 204 converts the signal received from the communication channel 203 into an array of numbers representing an estimate of the transmitted data. From the output of demodulator 204, these estimates are supplied to turbo codec decoder 205.

Next, we describe the principle of operation of an iterative decoding device for block turbo codes implemented in this utility model.

An iterative decoding device for block turbo codes consists of a first memory, a first adder, a SISO decoder, a second adder, a decision block, a third memory, and a normalization circuit. The SISO decoder includes a Chase algorithm decoding unit and a soft output decision calculating unit.

The values received from the demodulator are stored in the first memory. To decode the C1 code (whose code words are located vertically) or the C2 code (whose code words are horizontally), the correction value stored in binary form at the specified address in the second memory is read from it and fed to the first adder after passing through the circuit normalization. The first adder adds up the received value stored at the given address in the first memory and the correction value obtained from the normalization circuit, thus generating soft input values represented in binary form. At the first iteration of decoding

the correction values are equal to zero, so the first adder outputs the values received from the demodulator to the SISO decoder without changes.

Soft input values generated by the first adder in binary form are fed to the SISO decoder.

A SISO decoder consists of a Chase algorithm decoding unit that generates hypothetical error vectors from a soft input vector, and a soft output value calculation unit.

Next, we describe the SISO decoding process for codes C1 and C2.

In the decoder according to the Chase algorithm [4], at the intermediate stages, in addition to the hard decision vector, hypothetical error vectors are also calculated that take the value 1 at erroneous positions and 0 at the rest, as well as the weights of hypothetical error vectors. The weight of the hypothetical error vector is equal to the scalar product of the hypothetical error vector and the soft input vector.

In accordance with the present utility model, said intermediate parameters are binary output from the Chase decoder and fed directly to the SISO decoder soft output value calculation unit.

Further, as in the prototype, in the soft output value calculation unit for each binary symbol, soft solutions are calculated based on the logarithm of the ratio of posterior probabilities represented in this unit in binary form.

Figure 3 presents a block diagram of a hardware implementation of the proposed device for iterative decoding of block turbo codes formed by composite codes C1 and C2. The block diagram consists of a first memory 301 in which the input values received from the demodulator, the first adder 302, the second adder 303, the SISO decoder 304, and the decision block 305 for deciding the transmitted codeword from the soft output values received from the SISO decoder are stored 304, the third memory 306 for storing the codeword, the decision on which was made in the decision block 305, the second memory 307 for storing the correction values received from the second adder 302, the normalization circuit 308 for multiplying the correction values th,

received from the second memory 307, normalization coefficients α. The decision block determines the sign bit from the values supplied to it.

Next, we describe the operation of the decoding device shown in Fig.3. The binary input matrix of input values received from the demodulator is stored in the first memory 301. To decode the C1 code (whose code words are arranged vertically) or C2 code (whose code words are horizontally), the correction value stored at the given address in the second memory 307 is read from it and fed to the first adder 302 after passing through the normalization circuit 308. The first adder 302 adds the received value stored at a given address in the first memory 301 and the correction values y obtained from the normalization circuit 308 to generate soft input values represented in binary form. At the first iteration of decoding, the correction values stored in binary form in the second memory 307 are zero, therefore, the first adder 302 outputs the values received from the demodulator to the SISO decoder 304 without changes.

The soft input values generated by the first adder 302 are supplied in binary form to the SISO decoder 304. Having received the soft input values corresponding to the code words of the C1 code and the C2 code, the SISO decoder 304 starts decoding.

FIG. 4 is a block diagram of a SISO decoder 304. A SISO decoder consists of a Chase 401 decoding unit and a soft vector computation unit 402. We describe the operation of the SISO decoder 304 of FIG. 4. Chase 401 decoding block generates binary data: hard decision vector, hypothetical error vector and weight. The weight of the hypothetical error vector is equal to the scalar product of the hypothetical error vector and the soft input vector.

In accordance with this utility model, the block performing the calculation of hypothetical codewords and their likelihood in the patent prototype is excluded and the output of the Chase decoder 401 is connected directly to the block for calculating soft output values 402.

The soft output values generated in the soft output value calculating unit 402 of the SISO decoder 304 are supplied in binary form to the block

decisions 305 and to the second adder 303. The second adder 303 subtracts the received value from the soft output value to calculate the correction value, which is stored in binary form at the given address of the second memory 307. The decision block 305 makes a hard decision about the transmitted codeword from the soft output values and stores it in the specified address of the third memory 306.

In the proposed utility model, in comparison with the prototype patent, the likelihood calculation unit of hypothetical codewords is excluded, which calculates hypothetical codewords and their likelihood. In addition, operations associated with the search for the most probable codeword are excluded from the decoding block according to the Chase algorithm. As a result, the hardware implementation of the SISO decoder and, accordingly, the iterative decoding devices of block turbo codes are simplified.

An advantage of the proposed device is the lower complexity of the hardware implementation, which is expressed in a decrease in the number of discrete logic elements, with constant efficiency.

The utility model can be implemented on the appropriate elemental base for standard technologies.

Information sources:

1. C. Berrou, A. Glavieux, P. Thimimajshima: "Near Shannon limit error-correcting coding and decoding: Turbo codes", IEEE Int. Conf. Communications, ICC'93, vol. 2/3, May 1993, pp. 1064-1070.

2. J. Lodge, R. Young, P. Hoher and J. Hagenauer, "Separable MAP 'Filters' for the Decoding of Product and Concatenated Codes", Proc. 1993 IEEE Int. Conf. Comm. (ICC'93), pp. 1740-1745, May 1993.

3. Patent EP 1282237 A2, H03M 13/29 of February 5, 2003, "Decoding method and decoding apparatus of product code" is a prototype.

4. D.Chase, "A Class of Algorithms for Decoding Block Codes With Channel Measurement Information" (IEEE Trans. On Information Theory, January 1972, Vol. IT-18, pp. 170-182).

Claims (1)

An iterative decoding device for block turbo codes, consisting of a first memory, the data from which are supplied to the first input of the first adder and the inverse first input of the second adder, the output of the first adder is connected to the input of the SISO decoder, the output of which is connected to the second input of the second adder and to the input of the decision block , the output of which is connected to the third memory, the output of the second adder is connected to the input of the second memory, and the data from the output of the second memory is fed to the normalization circuit, the output of which is connected to the second input of the first adder, SISO decoder comprises a decoding unit for Chase algorithm and computation portion of soft output values, characterized in that the output of the decoding unit Chase algorithm connected to the input unit calculating soft output values.