RU2819292C1 - Passive jamming rejector computer - Google Patents

Abstract

FIELD: computer equipment.

SUBSTANCE: invention can be used in automated systems for performing complex mathematical operations in order to isolate signals on the background of passive interference with a priori unknown Doppler phase. In the passive jamming rejector computer, the output of the synchronous generator is additionally connected to the synchronous inputs of the complex interface unit, the third complex multiplier, accumulators, the unit for calculating the module and dividers. Inputs of the passive jamming rejector computer are inputs of the third delay unit, and outputs—outputs of the second complex adder.

EFFECT: high efficiency of rejection of passive interference with a priori unknown Doppler phase and separation of signals from moving targets.

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Description

The invention relates to the field of computer technology and can be used in automated systems to perform complex mathematical operations in order to isolate signals against the background of passive interference with an a priori unknown Doppler phase.

A radar device for detecting a moving target is known [Japanese patent No. 63-49193, MGZh G01S 13/52], containing sequentially connected delay units, a complex number multiplier and a subtractor. However, this device has low efficiency in isolating a moving target signal.

The passive noise compensator calculator closest to this invention [patent RU No. 2760961, IPC N04V 1/10, G01S 13/02], selected as a prototype, contains a weight block, delay blocks and complex adders. However, this device has losses in the efficiency of interference rejection.

The problem solved in the invention is to increase the efficiency of rejecting passive interference and isolating signals from moving targets when processing signals from a target against the background of passive interference with an a priori unknown Doppler phase.

To solve the problem, the first and second complex multipliers and a Doppler phase meter, connected to each other in a certain way, are introduced into the passive noise rejector calculator, which contains a weight block, the first, second, third and fourth delay blocks, the first and second complex adders and a clock generator.

The essence of the invention as a technical solution is characterized by a set of essential features set out in the claims and providing a solution to the problem through optimal and coordinated processing of incoming pulses.

The technical result of the invention is to increase the efficiency of passive interference rejection with an a priori unknown Doppler phase and the selection of moving target signals.

In fig. Figure 1 shows the structural electrical diagram of the passive noise rejection computer; in fig. 2 - weight block; in fig. 3 - delay block; in fig. 4 - complex adder; in fig. 5 - complex multiplier; in fig. 6 - Doppler phase meter; in fig. 7 - complex interface block; in fig. 8 - storage; in fig. 9 - module calculation block.

The passive interference processor-rejector (Fig. 1) contains a weight block 1, delay blocks 2, 4, 7, 8, complex adders 3, 5, a clock generator 6, complex multipliers 9,10 and a Doppler phase meter 11.

Weight block 1 (Fig. 2) contains a memory block 12 and first and second multipliers 13; delay blocks 2, 4, 7, 8 (Fig. 3) contain first and second delay lines 14; the first and second complex adders 3, 5 (Fig. 4) contain the first and second adders 15; the first, second and third complex multipliers 9, 10, 20 (Fig. 5) contain two channels (I, P), each of which contains the first and second multipliers 16, 17 and an adder 18; Doppler phase meter 11 (Fig. 6) contains a complex conjugation unit 19, a third complex multiplier 20 (Fig. 5), first and second accumulators 21, module calculation unit 22 and first and second dividers 23; complex interface block 19 (Fig. 7) contains a sign inverter 24; the first and second drives 21 (Fig. 8) contain n delay elements 25 for the interval t _d and n adders 26, module calculation unit 22 (Fig. 9) contains the first and second quadrators 27, an adder 28 and a square root extraction unit 29.

The passive noise suppressor computer can be implemented as follows.

The digital samples {x _kl , y _kl ) arriving at the input of the proposed device (Fig. 1) follow through the repetition period T and in each range resolution element (range ring) of each repetition period they form a sequence of complex numbers

where k is the number of the current period, l is the number of the current range ring, ϕ _l is the Doppler phase shift over the repetition period (Doppler phase), usually interference, due to its significant excess over the signal.

Digital samples in the inventive device (Fig. 1) are supplied to the connected inputs of the third delay block 7 (Fig. 3) at interval t and the second inputs of the Doppler phase meter 11 (Fig. 6). The first inputs of the Doppler phase meter 11 receive samples from the output of the first delay block 2 for the interval T - τ. The readings at the first and second inputs of the Doppler phase meter 11 are divided into the T interval.

Samples from the output of the third delay block 7 are supplied to the inputs of the weight block 1, the first inputs of the second complex adder 5 and to the inputs of the first delay block 2, from the outputs of which the samples are supplied to the cascaded fourth delay block 8, the first complex multiplier 9, the first complex adder 3 , a second delay block 4, a second complex multiplier 10 and a second complex adder 5, the outputs of which are the outputs of the inventive device. Readings from the outputs of weight block 1 are sent to the first inputs of the first complex adder 3.

In the sign inverter 24 (Fig. 7) of the complex interface block 19 of the meter 11 (Fig. 6), the sign of the imaginary projections of the delayed samples is inverted. In the third complex multiplier 20, the corresponding complex numbers are multiplied, implemented by operations with the projections of these numbers in accordance with FIG. 5 and leading to the formation of quantities

In drives 21 (Fig. 6), with the help of delay elements 25 and adders 26 (Fig. 8), the summation of projections ReX _kl and ImX _kl with n+1 adjacent resolution elements along the range of the time strobe is carried out sliding along the range in each repetition period, except for the element number n/2+1, for which the output values of delay element 25 with number n/2 are supplied only to the subsequent delay element 25 (Fig. 8). As a result of accumulation, quantities are formed

Where - estimate of the Doppler phase shift of the interference over the repetition period, averaged over n adjacent range resolution elements.

In module calculation block 22 (Fig. 9) the values are determined

, and then at the outputs of dividers 23 (Fig. 6) - the values arriving at the second inputs of the first and second complex multipliers 9, 10. Accumulation and samples provides high-precision measurement of the quantity

In weight block 1 (Fig. 2), incoming samples are weighed by a weight coefficient g=-2, stored in memory block 12.

The fourth delay block 8 for the interval t together with the first delay block 2 for the interval T-τ form the resulting delay for the interval T. In the second delay block 4 there is a delay for the interval T.

As a result, samples are received synchronously at the inputs of complex adders 3 and 5. Taking into account complex multiplication with the quantity delayed samples and in-phase summations in complex adders 3, 5, at the output of complex adder 5, samples of the remaining interference have the form

Two-dimensional rotation of delayed samples in the first and second complex multipliers 9, 10 by angle provides the in-phase consistency of the summed samples necessary to compensate for interference. Signal samples from a moving target are not suppressed due to the preservation of Doppler phase shifts.

The introduction of the third delay block 7 for the interval τ ensures the correspondence of the estimates the average element of the training set, excluded in accumulators 21 (Fig. 8). The value of m is determined by the expression

where t _B is the time to calculate the estimate - number of elements of the training sample, t _d - interval (period) of time sampling.

In this case, the correspondence of the estimates entered into the first and second complex factors 9, 10 is achieved the middle element excluded from the training set. Then, in the case of a signal comparable in magnitude to the interference, or discontinuous interference, when compensating for interference samples from the resolution element containing the signal, the possibility of attenuation or suppression of the signal due to its influence on the used estimates is eliminated. In addition, errors are reduced due to the mismatch between the estimated and actual values of the Doppler phase of the interference.

The synchronization of the passive interference evaluator-rejector is carried out by supplying all blocks of the inventive device with a sequence of synchronizing pulses from the clock generator 6 (Fig. 1).

The achieved technical result consists in increasing the efficiency of compensation for passive interference with an a priori unknown Doppler phase and isolating signals from moving targets, which is ensured by the in-phase of the summed samples, increasing the accuracy of estimating the Doppler phase of interference and reducing the mismatch between the estimates obtained by averaging the samples of the training sample and the samples corresponding to the average element of the training sample. samples.

Thus, the passive interference calculator-rejector makes it possible to increase the efficiency of suppressing passive interference and isolating signals from moving targets against the background of passive interference with an a priori unknown Doppler phase.

Claims (1)

A passive interference calculator-rejector containing a weighting block, a first delay block, a first complex adder, a second delay block, a second complex adder, a clock generator, a third delay block, a fourth delay block, a first complex multiplier, a second complex multiplier and a Doppler phase meter containing the block complex interface, a third complex multiplier, accumulators, a module calculation block and dividers, while the inputs of the first delay block are connected to the inputs of the weighting block and the first inputs of the second complex adder, the outputs of the weighting block are connected to the first inputs of the first complex adder, the outputs of which are connected to the inputs of the second delay block, the outputs of the third delay block are connected to the inputs of the first delay block, the outputs of which are connected to the inputs of the fourth delay block, the outputs of the fourth delay block are connected to the first inputs of the first complex multiplier, the outputs of which are connected to the second inputs of the first complex adder, the outputs of the second delay block are connected with the first inputs of the second complex multiplier, the outputs of which are connected to the second inputs of the second complex adder, the outputs of the first delay block are connected to the first inputs of the Doppler phase meter, the inputs of the third delay block are connected to the second inputs of the Doppler phase meter, the outputs of which are connected to the second inputs of the first and second complex multipliers, the output of the clock generator is connected to the clock inputs of the weight block, the first delay block, the first complex adder, the second delay block, the second complex adder, the third delay block, the fourth delay block, the first complex multiplier and the second complex multiplier, characterized in that the output of the clock generator is connected with the synchronizing inputs of the complex interface block, the third complex multiplier, accumulators, the module calculation block and dividers, and the inputs of the passive noise rejector calculator are the inputs of the third delay block, and the outputs are the outputs of the second complex adder.

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