RU2810690C1 - Memory cell and method of its manufacture, as well as storage device and method of its manufacture - Google Patents

Abstract

FIELD: semiconductor technology.

SUBSTANCE: present invention relates to a memory cell and a method for its manufacture, as well as a storage device and a method for its manufacture. The memory unit includes a first dielectric layer and a second dielectric layer, which are stacked. The first dielectric layer houses the first transistor. The second transistor is placed in the second dielectric layer. The first dielectric layer is connected to the second dielectric layer via a connecting wire. The parasitic capacitance in the first transistor or the second transistor is used as a memory element to replace a capacitor in the related art, so that the volume occupied by the memory cells can be reduced to ensure that the memory cells are developed in the embedding direction. In addition, the first transistor and the second transistor are both metal oxide thin film transistors.

EFFECT: memory device can have a longer charge retention time to improve the performance of the memory device while reducing the volume of the memory device.

10 cl, 10 dwg

Description

Cross reference to related applications

The present invention requests a priority on the application for China Patent 202110753695.0, the entitled “Memory cell and the method of manufacturing, as well as the storage device and the method of its manufacture”, filed in the National Intellectual Property Directorate (CNIPA) on July 2, 2021, which is fully included in the present document by reference.

Field of technology

The present invention relates to the technical field of semiconductors and, in particular, to a memory cell and a method for its manufacture, as well as a storage device and a method for its manufacture.

State of the art

Dynamic random access memory (DRAM) is a semiconductor memory device that randomly writes and reads data at high speed and is widely used in data storage devices or hardware.

DRAM typically includes a substrate, an array of memory cells formed by multiple repeating memory cells, and peripheral circuitry located on the substrate. A plurality of memory cells are arranged at intervals along a direction parallel to the base. Each of the memory cells typically includes a capacitor structure and a transistor, the gate of which is connected to a word line in the memory cell array, the drain is connected to a bit line in the memory cell array, and the source is connected to the capacitor structure.

However, the design is not suitable for the manufacture of small-sized storage devices.

Disclosure of the invention

In a first aspect of embodiments of the present invention, there is provided a memory cell including:

a first transistor located in the first dielectric layer;

a second transistor located in a second dielectric layer, the second dielectric layer located above the first dielectric layer; And

a connecting wire disposed in the first dielectric layer and the second dielectric layer, wherein one end of the connecting wire is connected to the first transistor and the other end is connected to the second transistor; wherein

the first transistor and the second transistor are metal oxide thin film transistors.

In a second aspect of embodiments of the present invention, there is provided a storage device including:

a base, the peripheral circuit being disposed on a surface of the base;

a plurality of memory cells described above located above the peripheral circuit; And

a data line configured to connect the peripheral circuit to the memory cells.

In the memory device described above, a plurality of memory cells are arranged in a direction parallel to the base to form a horizontal array; and/or

a plurality of memory cells are stacked in a direction perpendicular to the base to form a vertical array.

In a third aspect of embodiments of the present invention, there is provided a method for manufacturing a memory cell, including:

forming a first transistor in the first dielectric layer, wherein the first transistor is a metal oxide thin film transistor;

forming a connecting wire portion in the first dielectric layer, wherein one end of the connecting wire is connected to the first transistor;

forming a second dielectric layer on the first dielectric layer;

forming another portion of a connecting wire in the second dielectric layer, wherein one end of the connecting wire proximate the first dielectric layer is connected to a connecting wire formed in the first dielectric layer; And

forming a second transistor in the second dielectric layer, the second transistor being connected to one end of the connecting wire remote from the first dielectric layer, and the second transistor being a metal oxide thin film transistor.

In a fourth aspect of embodiments of the present application, a method for manufacturing a storage device is provided, including:

providing a base, the peripheral circuit being disposed on a surface of the base;

forming a plurality of memory cells sequentially on the base, the plurality of memory cells being arranged in a direction parallel to the base to form a horizontal array; and/or a plurality of memory cells are stacked in a direction perpendicular to the base to form a vertical array; wherein the memory cell is obtained using the above-described method for manufacturing a memory cell;

forming a data transmission line, wherein the data transmission line is configured to connect the peripheral circuit to the memory cells.

In addition to the technical problems solved by the embodiments of the present invention, the technical features constituting the technical solutions, and the advantageous effects caused by the technical features of these technical solutions, other technical problems to be solved by the memory cell and the manufacturing method thereof, as well as the storage device and method of manufacturing it in embodiments of the present disclosure, other technical features included in the technical solutions, and the advantageous effects caused by these technical features are described in detail in specific embodiments.

Brief description of drawings

To more clearly describe the technical solutions in the embodiments of the present invention or in the prior art, the following briefly describes the drawings necessary to describe the embodiments or the prior art. Obviously, the drawings in the following description show some embodiments of the present invention, and a person skilled in the art can obtain other drawings from these drawings without creative effort.

In fig. 1 is a schematic diagram of a structure of a memory cell according to Embodiment 1 of the present invention.

In fig. 2 is a schematic diagram of a structure of a memory device according to Embodiment 2 of the present invention;

In fig. 3 is a circuit diagram of a memory device according to Embodiment 2 of the present invention;

In fig. 4 is a flowchart of a method for manufacturing a memory cell according to Embodiment 3 of the present invention;

In fig. 5 is a schematic diagram of a structure of an active layer formed in the memory cell manufacturing method according to Embodiment 3 of the present invention;

In fig. 6 is a schematic diagram showing a structure of a first transistor formed in the memory cell manufacturing method according to Embodiment 3 of the present invention;

In fig. 7 is a schematic diagram showing a structure of a second insulating layer formed in the memory cell manufacturing method according to Embodiment 3 of the present invention;

In fig. 8 is a schematic diagram showing a structure of a first contact portion and a metal wire formed in the memory cell manufacturing method according to Embodiment 3 of the present invention;

In fig. 9 is a schematic diagram showing the structure of the second contact portion and the active layer formed in the memory cell manufacturing method according to Embodiment 3 of the present invention; And

In fig. 10 is a schematic diagram showing a structure of a second transistor formed in the memory cell manufacturing method according to Embodiment 3 of the present invention.

Carrying out the invention

Dynamic random access memory (DRAM) typically includes a plurality of repeating memory cells that are spaced apart in a direction parallel to the substrate. Each memory cell includes capacitors and transistors, so that the storage device has a larger capacity. As dynamic random access memory devices evolve towards integration, each memory cell continues to use one transistor and one capacitor (1T1C, 1 Transistor 1 Capacitor). In particular, capacitors are limited in size, making it difficult to provide storage volume and charge retention time within a memory cell, resulting in reduced memory performance.

Based on the above technical problems, embodiments of the present invention provide a memory cell and a method for its manufacture, a storage device and a method for its manufacture. The memory cell includes a first transistor and a second transistor, which are stacked. The parasitic capacitance in the first transistor or the second transistor is used as a memory element to replace a capacitor in the related art so that the volume occupied by the memory cells can be reduced to improve the embedding of the memory cell and allow the development of the memory cells in the embedding direction.

In addition, the first transistor and the second transistor are both metal oxide thin film transistors, so that the memory device can have a longer charge retention time to improve the performance of the memory device while reducing the volume of the memory device.

To make the objectives, features and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments represent only some, and not all, embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative effort fall within the scope of the present invention.

Implementation option 1

As shown in FIG. 1, this embodiment of the present invention provides a memory cell 100. Memory cell 100 may include a first dielectric layer 120 and a second dielectric layer 140 disposed on the first dielectric layer 120. A first transistor 110 is disposed on the first dielectric layer 120. A second transistor 130 is disposed on the second dielectric layer 140. The first transistor 110 is coupled to the second transistor 130 using a connecting wire 150 disposed in the first dielectric layer 120 and the second dielectric layer 140. The first transistor 110 and the second transistor 130 may be metal oxide thin film transistors.

The memory cell 100 related to this embodiment includes a first transistor 110 and a second transistor 130 that are stacked. The parasitic capacitance in the first transistor 110 or the second transistor 130 is used as a memory element to replace a capacitor in the related art, so that the volume occupied by the memory cells 100 can be reduced to ensure that the memory cells 100 are designed in the embedding direction.

In addition, the first transistor 110 and the second transistor 130 are metal oxide thin film transistors, so that the memory device can have a longer charge retention time to improve the performance of the memory device while reducing the volume of the memory device.

It should be noted that the first transistor 110 and the second transistor 130 have the same structure. For ease of description, the first transistor 110 is used as an example in the following embodiment, and the structure of the first transistor 110 is described.

For example, with reference to FIG. 1, the first transistor 110 includes an active layer 111, a gate oxide layer 112, and a gate 113. The active layer 111 includes a channel region and a source and drain, which are respectively located on two sides of the channel region. The gate oxide layer 112 and the gate 113 are layered sequentially on the active layer 111. The gate protrusion 113 on the active layer 111 spans the channel region such that there is an overlapping region between the gate 113 and the active layer 111. Thus, when between the active layer 111 and the gate 113 a voltage difference is generated and a capacitance is formed between the gate 113 and the active layer 111. The capacitance is used as a memory element of a memory cell to read or write data.

In addition, in this embodiment, the material of the active layer 111 may include indium gallium zinc oxide, which has higher carrier mobility, thereby significantly improving the sensitivity of the first transistor and reducing power consumption of the memory cell.

The material of the gate oxide layer 112 may include silicon oxide and/or alumina, and the material of the gate 113 may include one of the group consisting of titanium nitride, tantalum nitride, aluminum and tungsten.

It should be noted that in this embodiment, the projection of the gate 113 onto the active layer 111 covers the channel region, which can be understood to mean that the projection area of the gate 113 onto the active layer 111 is equal to the area of the channel region or that the projection area of the gate 113 onto the active layer 111 is smaller area of the channel region.

In addition, the first transistor 110 further includes a protective layer 114. The protective layer 114 is located on the sides of the gate 113 and the gate oxide layer 112. A protective layer 114 is provided to electrically isolate the gate from other components.

In some embodiments, the connecting wire 150 may have one end connected to the gate of the first transistor 110 and the other end connected to the source or drain of the second transistor 130. The electrical signal at the source or drain of the second transistor 130 is used to control the first transistor 110 to turn on or off. closing.

It should be noted that the shape of the connecting wire 150 can be arbitrary. For example, the connecting wire 150 may be a straight line or a bent line.

For example, the connecting wire 150 includes a first contact portion 151, a metal wire 152, and a second contact portion 153. The first contact portion 151 and the second contact portion 153 extend in a vertical direction. That is, the first contact portion 151 and the second contact portion 153 are placed in a direction perpendicular to the first dielectric layer 120. The metal wire 152 extends in a horizontal direction. One end of the metal wire 152 is connected to the first contact portion 151. One end of the metal wire 152 is connected to the second contact portion 153.

The first contact portion 151 is connected to the gate 113 of the first transistor 110, and the second contact portion 153 is connected to the source or drain of the second transistor 130.

In this embodiment, one end of the metal wire 152 is connected to the first contact portion 151, which can be understood to mean that one end of the metal wire 152 is connected to the middle portion of the first contact portion 151 or that one end of the metal wire 152 is connected to one end of the first contact portion 151.

For example, one end of the metal wire 152 may be connected to the end of the first contact portion 151 remote from the gate 113 of the first transistor 110, and the other end of the metal wire 152 may be connected to the end of the second contact portion 153 remote from the second transistor 130.

In some embodiments, the first contact portion 151 and the metal wire 152 may be located in the first dielectric layer 120. The second contact portion 153 may be located in the second dielectric layer 140. However, the foregoing is simply a method for positioning the connection wire 150. The connection wire 150 may optionally be completely located in the first dielectric layer 120 or in the second dielectric layer 140.

To prevent the conductive materials in the first dielectric layer 120 and the second dielectric layer 140 from diffusion into each other, a barrier layer 160 is also provided between the first dielectric layer 120 and the second dielectric layer 140. The barrier layer 160 is located on the metal wire 152. The second contact portion 153 extends through barrier layer 160 and connected to metal wire 152.

The material of the barrier layer 160 may include an insulating material such as silicon nitride.

Implementation option 2

As shown in FIG. 2, this embodiment of the present invention further provides a storage device 200 that includes a base 210, a memory cell 100, and a data line 220.

The base 210 serves as a support member of the storage device and is configured to support other components provided thereon. The base 210 may be made of a semiconductor material. The semiconductor material may be one or more of the group consisting of silicon, germanium, silicon-germanium, and silicon-carbon.

Peripheral circuitry 211 is disposed on a surface of substrate 210 and may further include logic or processing circuitry.

A plurality of memory cells 100 are arranged above the peripheral circuit 211, and the memory cells 100 are connected to the peripheral circuit 211 via a data line 220.

Compared with the technical solution in the related art, in which the peripheral circuit is placed on both sides of the memory cells in the horizontal direction, this embodiment, in which the peripheral circuit is located below the memory cells, can reduce the area of the memory cells and enable the development of memory in the embedding direction.

Moreover, as shown in FIG. 2, data line 220 includes a read word line 221, a read bit line 222, a write word line 223, and a write bit line 224.

A write word line 223 and a write bit line 224 may be arranged in the second dielectric layer 140. The write word line 223 extends in a first direction and is connected to the gate of the second transistor 130 in each of the plurality of memory cells 100. The write bit line 224 extends in the second direction and is connected to the source or drain of the second transistor 130 in each of the plurality of memory cells 100, and the connection between the write bit line and the source or drain of the second transistor is different from the connection between the connecting wire 150 and the source or drain. second transistor.

In other words, if the connecting wire 150 is connected to the source of the second transistor 130, the write bit line 224 is connected to the drain of the second transistor 130.

A read word line 221 and a read bit line 222 may be disposed in the first dielectric layer 120. The read word line 221 extends in a third direction and is connected to the source or drain of the first transistor 110 in each of the plurality of memory cells 100. The read bit line 222 extends in the fourth direction and is connected to the source or drain of the first transistor 110 in each of the plurality of memory cells 100, and the connection between the read bit line and the source or drain of the first transistor is different from the connection between the read word line and the source or drain of the first transistor.

In other words, if the read word line 221 is connected to the source of the first transistor 110, the read bit line 222 is correspondingly connected to the drain of the first transistor 110.

The projection of the first direction and the projection of the second direction onto a surface parallel or perpendicular to the base form a first angle, the projection of the third direction and the projection of the fourth direction onto a surface parallel or perpendicular to the base form a second angle, and neither the first angle nor the second angle is zero . That is, a word line to be written and a bit line to be written are arranged to form an intersection, and a word line to be read and a bit line to be read are also arranged to form an intersection.

As shown in FIG. 3, when applied to the write word line 223, a high voltage may be used to drive the gate of the second transistor 130 to open, and a voltage difference is generated between the source and drain of the second transistor 130 to effect conduction between the source and drain of the second transistor. The write bit line 224 voltage operates at the gate of the first data write transistor 110 on the write bit line 224 to the first transistor.

When data needs to be read from the first transistor, the gate of the first transistor 110 is opened so that the source and drain of the first transistor are opened. In this case, the data in the first transistor 110 is transmitted to the peripheral circuit 211 by using the read bit string 222, and the peripheral circuit 211 processes the data to implement a memory read function.

In some embodiments, a plurality of memory cells 100 are arranged in a direction parallel to the base 210 to form a horizontal array, that is, a plurality of memory cells 100 are arranged sequentially in a horizontal direction. In addition, a plurality of memory cells 100 are stacked in a direction perpendicular to the base 210 to form a vertical array. Thus, in this embodiment, the number of memory cells 100 that are arranged sequentially in the horizontal direction can be reduced, the area occupied by a plurality of memory cells can be reduced, and the embedding of memory cells can be improved to ensure that the storage device evolves in the embedding direction. .

In addition, compared with the technical solution in the related art in which a plurality of memory cells are arranged in a horizontal direction, a plurality of memory cells 100 are stacked in a direction perpendicular to the base 210 to form a vertical array such that the height of the storage device increases to reduce the width of the storage device in the horizontal direction, thereby reducing the volume of the storage device and improving the embedding of memory cells.

In some embodiments, a peripheral dielectric layer 230 is placed on the base 210. The peripheral dielectric layer 230 covers the peripheral circuit 211 to electrically isolate cells in the peripheral circuit 211.

The material of the peripheral dielectric layer 230 may include silicon nitride.

In addition, a peripheral barrier layer 240 is also disposed between the peripheral dielectric layer 230 and the first dielectric layer 120 of the memory cell 100. This arrangement prevents the conductive material in the first dielectric layer from affecting the performance of the peripheral circuit.

When the peripheral barrier layer 240 is placed between the peripheral dielectric layer 230 and the first dielectric layer 120, the data line 220 must pass through the peripheral barrier layer 240 and the peripheral dielectric layer 230, and then connect to the peripheral circuit 211.

Implementation option 3

As shown in FIG. 4, this embodiment of the present invention further provides a method for manufacturing a memory cell, including:

Step S100: forming a first transistor in the first dielectric layer, the first transistor being a metal oxide thin film transistor.

The first dielectric layer 120 may be used as a support body for the first transistor 110 or an insulating medium between the first transistor 110 and another element. The material of the first dielectric layer 120 may include silicon oxide or silicon nitride.

The first transistor 110 may be manufactured, for example, as follows:

Step a: provide the first insulating layer.

It should be noted that the first insulating layer 121 is part of the first dielectric layer 120.

Step b: An active layer is formed on the first insulating layer, the material of the active layer including indium gallium zinc oxide.

For example, as shown in FIG. 5, the active layer 111 may be formed on the first insulating layer 121 using a deposition process, which may be one of a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process.

Step c: form a channel region in the active layer and a source and a drain, respectively, located on two sides of the channel region.

At this point, a photoresist layer may be formed on the active layer 111 and then patterned to form a hole therein. The hole may expose a portion of the active layer 111. Doped ions are then introduced into the hole using an ion implantation process to form a source in the active layer 111.

During the above process, a sink is also generated in the active layer 111.

Step d: forming a gate oxide layer on the active layer, wherein the length of the gate oxide layer is shorter than the length of the active layer.

Silicon oxide or aluminum oxide is deposited at a certain thickness onto the active layer 111 through a deposition process. Silicon oxide or aluminum oxide forms the gate oxide layer 112.

Step e: a gate is formed on the gate oxide layer, with the projection of the gate onto the active layer covering the channel region.

The deposition process is used continuously to form the gate 113 on the gate oxide layer 112. The material of the gate 113 may be one of the group consisting of titanium nitride, tantalum nitride, aluminum and tungsten.

Step f: forming a protective layer on the active layer, the protective layer covering the sides of the gate and the gate oxide layer, and the structure of the protective layers is shown in FIG. 6.

Initial protective layers can be formed on the active layer through a deposition process. The initial protective layers cover the side surfaces of the gate oxide layer and the top surface and side surfaces of the gate. An etching gas or etching solution is then used to remove the original protective layer on the top surface of the gate, and the original protective layers on the side surfaces of the gate and gate oxide layers are retained to form the protective layers 116.

Step g: forming a second insulating layer covering the active layer, a gate oxide layer, a gate and a protective layer on the first insulating layer, the second insulating layer and the first insulating layer forming a first dielectric layer, and the structure of the first insulating layer is shown in FIG. 7.

Step S200: forming a connecting wire portion in the first dielectric layer, with one end of the connecting wire connected to the first transistor.

For example, as shown in FIG. 8, the first contact portion 151 and a metal wire 152 connected to the first contact portion 151 are formed in the second insulating layer 122. The first contact portion 151 extends in the vertical direction and is connected to the gate 113 of the first transistor 110. The metal wire 152 extends in the horizontal direction. The first contact part 151 and the metal wire 152 form a connecting wire part.

At this stage, the first contact portion 151 and the metal wire 152 are formed using a double inlay process or may be formed using a double inlay process twice.

It should be noted that in this embodiment, one end of the connecting wire can be understood as one end of the first contact part away from the metal wire.

Step S300: forming a second dielectric layer on the first dielectric layer.

For example, a barrier layer 160 may be formed on the first dielectric layer 120, that is, a barrier layer 160 may be formed first on the second insulating layer 122. The barrier layer is used to prevent conductive materials in the first dielectric layer and the second dielectric layer from diffusion into each other.

The materials of the second dielectric layer and the first dielectric layer may be the same and both contain silicon oxide. The second dielectric layer 140 may include a third insulating layer 141 and a fourth insulating layer 142, which are stacked in series. A third insulating layer 141 is placed on the barrier layer 160.

Step S400: forming another part of the connecting wire in the second dielectric layer, and one end of the connecting wire near the first dielectric layer is connected to the connecting wire formed in the first dielectric layer.

For example, a filled groove may be formed in the second dielectric layer and exposes a portion of the metal wire 152. A conductive material is then formed in the filled groove through a deposition process. The conductive material forms the second contact portion 153. The second contact portion 153 is connected to the metal wire 152 such that the first contact portion 151, the second contact portion 153, and the metal wire 152 form a connecting wire.

Step S500: forming a second transistor in the second dielectric layer, the second transistor is connected to one end of the connecting wire away from the first dielectric layer, and the second transistor is a metal oxide thin film transistor.

For example, as shown in FIG. 9, a third insulating layer 141 is formed on the first dielectric layer 120.

After the third insulating layer 141 is formed, the active layer 111 may be formed on the third insulating layer 141 through a deposition process. The material of the active layer 111 includes indium, gallium and zinc oxide.

It should be noted that the step of forming the active layer on the third insulating layer is the same as the step of forming the active layer on the first insulating layer, which is not described in detail again in this embodiment.

Steps c to f are repeated to form the second transistor 130 on the third insulating layer 141, and the structure of the second transistor is shown in FIG. 10.

After the second transistor 130 is formed on the third insulating layer 141, a fourth insulating layer 142 is formed covering the active layer, the gate oxide layer, the gate and the protective layer. The fourth insulating layer 142 and the third insulating layer 141 form the second dielectric layer 140.

In this embodiment of the present invention, based on the preceding steps, a first transistor and a second transistor are formed, which are stacked and used as memory elements of memory cells to replace a capacitor in the related art, so as to reduce the space occupied by memory cells, improve cell embedding memory and ensure the development of memory cells in the embedding direction.

Implementation option 4

This embodiment of the present invention provides a method for manufacturing a storage device, including:

Step S10: A base is provided, with the peripheral circuit being placed on the surface of the base.

At this point, the peripheral circuit can be manufactured using a method in the relevant art, which is not described in detail again in this embodiment.

After the peripheral circuit is formed, a peripheral dielectric layer 230 may be formed on the substrate to cover the peripheral circuit.

Then, a peripheral barrier layer 240 may be formed on the peripheral dielectric layer 230 through a deposition process.

Step S20: forming a plurality of memory cells in series on the base, with the plurality of memory cells arranged in a direction parallel to the base to form a horizontal array; and/or a plurality of memory cells are stacked in a direction perpendicular to the base to form a vertical array.

The memory cells are obtained using the memory cell manufacturing method in the above embodiment, which is not described in detail again in this embodiment.

Step S30: forming a data line, wherein the data line is configured to connect the peripheral circuit to the memory cells.

It should be noted that the data line can be manufactured in two steps. One stage may be completed before the first transistor is formed. Another step can be completed after the second transistor is formed.

For example, after the first dielectric layer 120 is formed, a read word line 221 and a read bit line 222 that are isolated from each other may be formed in the first dielectric layer 120. A word line 221 for reading is configured to be connected to a source or drain of a first transistor 110 in each of a plurality of memory cells 100, a bit line 222 for reading is configured to be connected to a source or drain of a first transistor 110 in each of a plurality of memory cells 100, wherein the connection between the read bit line and the source or drain of the first transistor is different from the connection between the read word line 221 and the source or drain of the first transistor.

After the read word line 221 and the read bit line 222 are formed continuously, the first transistor 110 may be formed on the first dielectric layer 120, the second dielectric layer 140 may be formed on the first dielectric layer 120, and the second transistor 130 may be formed in the second dielectric layer 140.

After the second transistor 130 is formed, a write word line 223 and a write bit line 224 can be formed in the second dielectric layer 140. The write word line 223 is configured to connect to the gate of the second transistor 130 in each of the plurality of memory cells 100, bit line 224 for writing is configured to connect to the source or drain of the second transistor 130 in each of the plurality of memory cells 100, and the connection between the write bit line and the source or drain of the second transistor is different from the connection between the connecting wire 150 and the source or drain of the second transistor.

At this stage, the read word line, the read bit line, the write word line, and the write bit line can be produced by the double inlay process.

Compared with the technical solution in the related art in which a plurality of memory cells are arranged sequentially in a horizontal direction, this embodiment in which a plurality of memory cells are stacked in a vertical direction can reduce the area occupied by the memory cells, reduce the size of the storage device, and improve the embedding of memory cells.

In addition, compared to a prior art solution in which the peripheral circuitry is located outside the memory cell array, this embodiment in which the peripheral circuitry is located below the memory cells can further reduce the size of the storage device and improve integration.

The embodiments or embodiments of the present disclosure are described in a progressive manner, and each embodiment focuses on differences from other embodiments. The same or similar parts between embodiments may be related to each other.

In the description of this specification, a description by reference to the term “one embodiment,” “certain embodiments,” “an exemplary embodiment,” “example,” “specific example,” “certain examples,” or the like means that a particular the feature, structure, material or characteristic described in combination with the embodiment(s) or example(s) is included in at least one embodiment or example of the present invention.

In this specification, the schematic expression of the above terms does not necessarily refer to the same embodiment or example. Moreover, the particular feature, structure, material, or characteristic described may be suitably combined into any one or more embodiments or examples.

Finally, it should be noted that the above embodiments are used only to explain the technical solutions of the present invention, but are not intended to limit the present invention. Although the present invention has been described in detail with reference to the prior embodiments, those skilled in the art will appreciate that they may still modify the technical solutions described in the prior embodiments or make equivalent substitutions for some or all of the technical features in them. Modifications or substitutions do not make the corresponding technical solutions different from the essence and scope of the technical solutions of the embodiments of the present invention.

Claims (24)

1. Memory cell containing: a first transistor located in the first dielectric layer; a second transistor located in a second dielectric layer, the second dielectric layer located above the first dielectric layer; And a connecting wire disposed in the first dielectric layer and the second dielectric layer, wherein one end of the connecting wire is connected to the first transistor and the other end is connected to the second transistor; wherein the first transistor and the second transistor are metal oxide thin film transistors, and the parasitic capacitance in the first transistor or in the second transistor is used as a memory element. 2. The memory cell according to claim 1, in which each of the first transistor and the second transistor contains: an active layer, the active layer material comprising indium, gallium and zinc oxide, and the active layer comprising a channel region and a source and drain, which are respectively located on two sides of the channel region; a gate oxide layer placed on the active layer; And a gate placed on the gate oxide layer, with a projection of the gate onto the active layer covering the channel region. 3. The memory cell of claim 2, wherein each of the first transistor and the second transistor further comprises a protective layer, the protective layer being located on sides of a gate and a gate oxide layer. 4. The memory cell according to claim 2, wherein the connecting wire has one end connected to the gate of the first transistor and the other end connected to the source or drain of the second transistor. 5. The memory cell according to claim 4, in which the connecting wire includes a first contact part and a second contact part, which are placed vertically, and a metal wire placed horizontally; wherein a first contact portion is connected to a gate of the first transistor, a second contact portion is connected to a source or drain of the second transistor, and a metal wire connects the first contact portion to the second contact portion. 6. The memory cell according to claim 5, in which the first contact part and the metal wire are located in the first dielectric layer, and the second contact part is located in the second dielectric layer. 7. The memory cell according to claim 5 or 6, wherein a barrier layer is placed between the first dielectric layer and the second dielectric layer, the barrier layer is located on a metal wire, and the second contact part is connected to the metal wire after passing through the barrier layer. 8. Memory cell according to any one of claims. 1-6, wherein the plurality of memory cells constitute a storage device also comprising: a base, the peripheral circuit being disposed on a surface of the base; a data line configured to connect the peripheral circuit to a plurality of memory cells, Moreover, many memory cells are located above the peripheral circuit. 9. The memory cell according to claim 8, in which the specified plurality of memory cells are located in a direction parallel to the base, forming a horizontal array; and/or a plurality of memory cells are stacked in a direction perpendicular to the base to form a vertical array. 10. The memory cell of claim 8, wherein the data line comprises a write word line, a write bit line, a read word line, and a read bit line; wherein a line of words to be written extends in a first direction and connected to the gate of a second transistor in each of the plurality of memory cells, a line of bits to be written extends in a second direction and connected to the source or drain of a second transistor in each of the plurality of memory cells, wherein the connection between the line of bits for writing and the source or drain of the second transistor is different from the connection between the connecting wire and the source or drain of the second transistor, the line of words for reading is in the third direction and connected to the source or drain of the first transistor in each of the plurality of memory cells, the line of bits for reading is in in a fourth direction and connected to a source or drain of a first transistor in each of the plurality of memory cells, wherein the connection between the read bit line and the source or drain of the first transistor is different from the connection between the read word line and the source or drain of the first transistor.