CN116322028A

CN116322028A - Semiconductor structure, manufacturing method thereof and memory system

Info

Publication number: CN116322028A
Application number: CN202211586228.4A
Authority: CN
Inventors: 华文宇
Original assignee: ICLeague Technology Co Ltd
Current assignee: ICLeague Technology Co Ltd
Priority date: 2022-12-09
Filing date: 2022-12-09
Publication date: 2023-06-23

Abstract

The embodiment of the disclosure discloses a semiconductor structure, comprising: the active column array comprises first active columns and second active columns which are arranged in an array manner, wherein each of the first active columns and the second active columns comprises a channel region, and a first active region and a second active region which are respectively positioned at two opposite ends of the channel region along a first direction, and the first direction is the extending direction of the channel region; a word line surrounding the first active column and the second active column; a first memory structure located on a first side of the active pillar array and electrically connected to the first active region of the first active pillar; a second storage structure located on a second side of the active pillar array and electrically connected to the second active region of the second active pillar; the first side and the second side are two opposite sides of the active column array along the first direction; a first bit line located on a second side of the active pillar array and connected to the second active region of the first active pillar; and the second bit line is positioned on the first side of the active column array and connected with the first active region of the second active column.

Description

Semiconductor structure, manufacturing method thereof and memory system

Technical Field

The disclosure relates to the technical field of semiconductors, in particular to a semiconductor structure, a manufacturing method thereof and a memory system.

Background

A memory array architecture of a dynamic random access memory (DRAM, dynamic Random Access Memory) is an array of memory cells (i.e., 1T1C memory cells) that include one transistor and one capacitor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor.

As the size of dynamic random access memories continues to shrink, the size of transistors continues to shrink. How to form a dynamic random access memory with larger storage capacity, smaller size and higher performance is a problem to be solved.

BRIEF SUMMARY OF THE PRESENT DISCLOSURE

The embodiment of the disclosure provides a semiconductor structure, a manufacturing method thereof and a memory system.

According to one aspect of the present disclosure, there is provided a semiconductor structure comprising:

the active column array comprises first active columns and second active columns which are arranged in an array manner, wherein each of the first active columns and the second active columns comprises a channel region, and a first active region and a second active region which are respectively positioned at two opposite ends of the channel region along a first direction, and the first direction is the extending direction of the channel region;

a word line surrounding the first active pillar and the second active pillar;

A first memory structure located on a first side of the active pillar array and electrically connected to the first active region of the first active pillar;

a second storage structure located on a second side of the active pillar array and electrically connected with a second active region of the second active pillar; the first side and the second side are two opposite sides of the active pillar array along the first direction;

a first bit line located on a second side of the active pillar array and connected to a second active region of the first active pillar;

and the second bit line is positioned on the first side of the active column array and is connected with the first active region of the second active column.

In the above scheme, the first active columns and the second active columns form a plurality of columns of active columns arranged along a second direction and a plurality of rows of active columns arranged along a third direction, each row of active columns comprises the first active columns and the second active columns which are alternately arranged, each column of active columns comprises the first active columns or the second active columns, and the second direction intersects with the third direction and is perpendicular to the first direction.

In the above scheme, the word line extends along the second direction and surrounds the first active pillars and the second active pillars of the same row arranged along the second direction.

In the above scheme, the geometric center of the first active pillar projected on the first plane is offset from the geometric center of the first storage structure projected on the first plane along the second direction; and/or, the geometric center of the second active column projected on the first plane is offset from the geometric center of the second storage structure projected on the first plane along the second direction; the first plane is perpendicular to the first direction.

In the above scheme, the row of active pillars includes a first row of active pillars and a second row of active pillars alternately arranged in the third direction; among the plurality of first storage structures electrically connected with the first row of active columns, the geometric centers of two adjacent first storage structures projected on the first plane are C1 and C2 respectively; among a plurality of first storage structures electrically connected with a second row of active columns adjacent to the first row of active columns, the first storage structure with the smallest sum of distances between the first storage structure and C1 and C2 is projected at the geometric center of the first plane to be C3, and connecting lines of the C1, C2 and C3 are equilateral triangles;

and/or the number of the groups of groups,

among the plurality of second storage structures electrically connected with the first row of active columns, the geometric centers of two adjacent second storage structures projected on the first plane are C4 and C5 respectively; and among a plurality of second storage structures electrically connected with the second row of active columns adjacent to the first row of active columns, the second storage structure with the smallest sum of distances between the second storage structure and C4 and C5 is characterized in that the geometric center of the projection of the second storage structure on the first plane is C6, and the connecting lines of the C4, C5 and C6 are equilateral triangles.

In the above aspect, the first bit line and the second bit line extend along the third direction;

the first bit line is connected with the second active areas of the first active columns of the same column arranged along the third direction;

the second bit lines are connected to the first active regions of the second active pillars of the same column arranged along the third direction.

In the above scheme, the semiconductor structure further includes a gate oxide layer surrounding the first active pillar and the second active pillar, and the word line surrounds the gate oxide layer.

In the above scheme, the first bit line is located between the active pillar array and the second memory structure, and the second bit line is located between the active pillar array and the first memory structure.

In the above aspect, the semiconductor structure further includes:

a first contact structure located between the array of active pillars and the first storage structure for electrically connecting a first active region of the first active pillar with the first storage structure;

and the second contact structure is positioned between the active column array and the second storage structure and is used for electrically connecting the second active region of the second active column with the second storage structure.

In the above scheme, the semiconductor structure includes a dynamic random access memory, and the first storage structure and the second storage structure each include a storage capacitor.

According to another aspect of the present disclosure, there is provided a memory system including: one or more semiconductor structures as in any one of the above aspects; and

a memory controller coupled with and controlling the semiconductor structure.

According to yet another aspect of the present disclosure, there is provided a method of fabricating a semiconductor structure, comprising:

forming an active column array, wherein the active column array comprises a first active column and a second active column which are arranged in an array manner, the first active column and the second active column comprise a channel region, and a first active region and a second active region which are respectively positioned at two opposite ends of the channel region along a first direction, and the first direction is the extending direction of the channel region;

forming a word line surrounding the first active pillars and the second active pillars;

forming a second bit line and a first storage structure on a first side of the active pillar array respectively; the second bit line is connected with the first active region of the second active column, and the first storage structure is electrically connected with the first active region of the first active column;

Forming a first bit line and a second memory structure on a second side of the active pillar array respectively; the first bit line is connected with the second active region of the first active column, and the second storage structure is electrically connected with the second active region of the second active column; the first side and the second side are opposite sides of the active pillar array along the first direction.

and/or the number of the groups of groups,

In the above scheme, the method further comprises: a gate oxide layer is formed surrounding the first active pillars and the second active pillars, and the word line surrounds the gate oxide layer.

In the above scheme, forming the second bit line and the first memory structure includes:

forming a second bit line on a first side of the active pillar array;

forming a first memory structure on the second bit line;

forming a first bit line and a second memory structure, comprising:

forming a first bit line on a second side of the active pillar array;

a second memory structure is formed on the first bit line.

In the above scheme, the method further comprises:

forming a first contact structure on a first side of the active pillar array prior to forming the first memory structure; the first contact structure is used for electrically connecting the first active region of the first active column with the first storage structure;

forming a second contact structure on a second side of the active pillar array prior to forming the second memory structure; the second contact structure is for electrically connecting a second active region of the second active pillar with the second memory structure.

The embodiment of the disclosure provides a semiconductor structure, a manufacturing method thereof and a memory system, wherein the manufacturing method of the semiconductor structure comprises the following steps: forming an active column array, wherein the active column array comprises a first active column and a second active column which are arranged in an array manner, the first active column and the second active column comprise a channel region, and a first active region and a second active region which are respectively positioned at two opposite ends of the channel region along a first direction, and the first direction is the extending direction of the channel region; forming a word line surrounding the first active pillars and the second active pillars; forming a second bit line and a first storage structure on a first side of the active pillar array respectively; the second bit line is connected with the first active region of the second active column, and the first storage structure is electrically connected with the first active region of the first active column; forming a first bit line and a second memory structure on a second side of the active pillar array respectively; the first bit line is connected with the second active region of the first active column, and the second storage structure is electrically connected with the second active region of the second active column; the first side and the second side are opposite sides of the active pillar array along the first direction. In the embodiment of the disclosure, a first storage structure and a second storage structure are respectively formed on two opposite sides of an active pillar array along a first direction, and a first bit line and a second bit line are respectively formed on two opposite sides of the active pillar array along the first direction; in the second aspect, since the first storage structure and the second storage structure are disposed on opposite sides in the first direction, respectively, the area available for disposing the first storage structure and the second storage structure is increased, thereby reducing the difficulty in the process when forming the storage structure having a large storage capacity. In addition, in the embodiment of the disclosure, the word line surrounds the first active column and the second active column, so that the formation of leakage current can be better restrained, and the driving current is increased, which is beneficial to realizing effective balance between performance and power consumption.

Drawings

FIG. 1a is a schematic diagram of a DRAM memory cell formed by planar transistors according to the related art;

FIG. 1b is a schematic diagram of a DRAM memory cell formed by using a buried channel transistor according to the related art;

fig. 1c is a schematic perspective view of a semiconductor structure according to an embodiment of the disclosure;

FIG. 2a is a schematic diagram of circuit connections of a DRAM transistor provided in an embodiment of the present disclosure;

FIG. 2b is a schematic diagram of a circuit connection of a memory cell array according to an embodiment of the present disclosure;

fig. 3 is a flow chart illustrating a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;

fig. 4-28 are schematic cross-sectional views illustrating a manufacturing process of a semiconductor structure according to an embodiment of the present disclosure.

Detailed Description

In order to make the technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The present disclosure is described more specifically in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more fully apparent from the following description and appended claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the disclosure.

It will be understood that the meanings of "on … …", "over … …" and "over … …" in this disclosure should be interpreted in the broadest manner so that "on … …" means not only that it is "on" something with no intervening features or layers therebetween (i.e., directly on something), but also that it is "on" something with intervening features or layers therebetween.

Further, spatially relative terms such as "on … …," "above … …," "above … …," "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated for ease of description. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In the presently disclosed embodiments, the term "substrate" refers to a material upon which subsequent layers of material are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may comprise a variety of semiconductor materials, such as silicon, silicon germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

In the presently disclosed embodiments, the term "layer" refers to a portion of material that includes a region having a thickness. The layer may extend over the entirety of the underlying or overlying structure, or may have a range that is less than the range of the underlying or overlying structure. Further, the layer may be a region of homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure, or the layer may be between any horizontal facing at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along an inclined surface. The layer may comprise a plurality of sub-layers. For example, the interconnect layer may include one or more conductors and contact sublayers (in which interconnect lines and/or via contacts are formed), and one or more dielectric sublayers.

In the presently disclosed embodiments, the terms "first," "second," and the like are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.

Embodiments of the present disclosure relate to semiconductor structures that will be used in subsequent processes to form at least a portion of a final device structure. Here, the final device may include a memory including, but not limited to, a dynamic random access memory, which will be described below by way of example only.

It should be noted, however, that the description of the embodiments below with respect to the dynamic random access memory is only for illustrating the present disclosure, and is not intended to limit the scope of the present disclosure.

In the related art, the transistors of the mainstream memory include a Planar transistor (Planar) and a buried channel transistor (Buried Channel Array Transistor, BCAT), however, both the Planar transistor and the buried channel transistor are structured such that the source and the drain are located on both sides of the gate. Fig. 1a is a schematic perspective view of a semiconductor structure including a planar transistor; fig. 1b is a schematic diagram of a semiconductor structure including a buried channel transistor. As shown in fig. 1a and 1b, the source S and the drain D of the transistor in the related art are located at horizontal sides of the gate G, respectively. With this structure, the source and drain occupy different positions, respectively, so that the area of either the planar transistor or the buried channel transistor is large.

In addition, since a transistor can be manufactured over a silicon substrate, the transistor can be used in various memories such as a DRAM. In general, a DRAM is composed of a plurality of memory cells, each of which is mainly composed of one Transistor and one Capacitor controlled by the Transistor, that is, the DRAM is a structure of 1 Transistor (T) and 1 Capacitor (C, capacitor) (1T 1C); the main principle of the function is to use the charge stored in the capacitor to represent whether a binary bit (bit) is l or 0. As shown in fig. 1a and 1b, the source (or drain) of the transistor in the DRAM memory cell is connected to the bit line and the drain (or source) is connected to the capacitor. For Chips formed using BCAT, packaging is typically performed using Chip On Board (COB) to form a memory. Because the source and drain of the planar transistor and the buried channel transistor are respectively located at two sides of the gate level, the bit line and the capacitor in the DRAM memory cell are also located at the same side of the gate, and the connection between the bit line, the transistor and the capacitor, the connection between the Word Line (WL) and the transistor, and the like are also required to be implemented in the subsequent process, so that the circuit wiring is complex in the memory array area of the DRAM memory, and the manufacturing process is difficult.

Fig. 1c is a schematic perspective view of a semiconductor structure according to an embodiment of the disclosure; as shown in fig. 1c, the semiconductor structure includes a memory cell array 124, peripheral circuits 125, and interconnect lines 126 connecting the memory cell array and the peripheral circuits.

FIG. 2a is a schematic diagram of a circuit connection employing a 1T1C architecture provided in an embodiment of the present disclosure; as shown in fig. 2a, the drain electrode of the transistor T is electrically connected to a Bit Line (BL), the source electrode of the transistor T is electrically connected to one of the electrode plates of the capacitor C, the other electrode plate of the capacitor C may be connected to a reference voltage, which may be a ground voltage or another voltage, and the gate electrode of the transistor T is connected to a word Line; the transistor T is controlled to be turned on or off by applying a voltage through the word line WL, and the bit line BL is used to perform a read or write operation on the transistor T when the transistor T is turned on. FIG. 2b is a schematic diagram of a circuit connection of a memory cell array provided in an embodiment of the present disclosure, as shown in FIG. 2b, a DRAM is provided with a Row Access Strobe (RAS) line input and a Column Access Strobe (CAS) line input that address a particular memory cell by means of its row address and column address for reading and writing the cell.

With the development of the memory, the size of the dynamic random access memory is continuously reduced, and the process difficulty of forming the dynamic random access memory with larger memory capacity and higher performance is increasingly greater.

Based on this, in order to solve the above-mentioned problems, the embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, which can form a dynamic random access memory with larger memory capacity, smaller size and higher performance, and has relatively smaller process difficulty.

The embodiment of the disclosure provides a manufacturing method of a semiconductor structure. Fig. 3 is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the disclosure. As shown in fig. 3, a method for manufacturing a semiconductor structure according to an embodiment of the disclosure includes the following steps:

s100: forming an active column array, wherein the active column array comprises a first active column and a second active column which are arranged in an array manner, the first active column and the second active column comprise a channel region, and a first active region and a second active region which are respectively positioned at two opposite ends of the channel region along a first direction, and the first direction is the extending direction of the channel region;

s200: forming a word line surrounding the first active pillars and the second active pillars;

S300: forming a second bit line and a first storage structure on a first side of the active pillar array respectively; the second bit line is connected with the first active region of the second active column, and the first storage structure is electrically connected with the first active region of the first active column;

s400: forming a first bit line and a second memory structure on a second side of the active pillar array respectively; the first bit line is connected with the second active region of the first active column, and the second storage structure is electrically connected with the second active region of the second active column; the first side and the second side are opposite sides of the active pillar array along the first direction.

It should be understood that the steps shown in fig. 3 are not exclusive and that other steps may be performed before, after, or between any of the steps in the illustrated operations. The steps shown in fig. 3 can be sequentially adjusted according to actual requirements. Fig. 4 to 28 are schematic cross-sectional views illustrating a manufacturing process of a semiconductor structure according to an embodiment of the disclosure. It should be noted that fig. 4 to 28 are schematic views showing a complete implementation process of the manufacturing method of the semiconductor structure, and the unlabeled portions of the drawings may be shared with each other. The following describes in detail the method for manufacturing the semiconductor structure according to the embodiment of the present disclosure with reference to fig. 3 and fig. 4 to 28.

In step S100, an active pillar array is mainly formed.

In some embodiments, the first active pillars and the second active pillars constitute a plurality of columns of active pillars arranged along a second direction and a plurality of rows of active pillars arranged along a third direction, each row of active pillars including the first active pillars and the second active pillars alternately arranged, each column of active pillars including either a first active pillar or a second active pillar, the second direction intersecting the third direction and each being perpendicular to the first direction.

In some specific examples, the forming an active pillar array includes:

forming an initial active column array, wherein the initial active column array comprises initial first active columns and initial second active columns which are arranged in an array manner; the initial first active pillars and the initial second active pillars each include a bottom, a middle, and a top that are sequentially stacked along a first direction.

In some specific examples, the forming an active pillar array further comprises:

removing the top to form a first groove;

expanding the first groove along the second direction to form a second groove;

forming the first active region in the second groove;

And/or the number of the groups of groups,

removing the bottom to form a third groove;

expanding the third groove along the second direction to form a fourth groove;

and forming the second active region in the fourth groove.

In step S200, a word line is mainly formed.

In some embodiments, the word line extends along the second direction and surrounds the first active pillars and the second active pillars of the same row arranged along the second direction.

In some embodiments, the method further comprises: a gate oxide layer is formed surrounding the first active pillars and the second active pillars, and the word line surrounds the gate oxide layer.

The process of forming the active pillar array and the word lines is described in detail below in conjunction with fig. 4-14.

As shown in fig. 4 and 5, a semiconductor layer is provided, the semiconductor layer having a first face and a second face disposed opposite to each other in a thickness direction of the semiconductor layer, and a plurality of fifth grooves 135 and a plurality of sixth grooves 136 are formed by removing a portion of a material of the semiconductor layer from the first face, the fifth grooves 135 extending in the second direction, the sixth grooves 136 extending in the third direction, the fifth grooves 135 and the sixth grooves 136 dividing the semiconductor layer into a plurality of initial active pillars. The initial active pillars include initial first active pillars 101 and initial second active pillars 102; the initial first active pillars 101 and the initial second active pillars 102 each include a bottom 129, a middle 130, and a top 131, which are sequentially stacked in the first direction, and the initial first active pillars 101 and the initial second active pillars 102 are arranged in an array to form an initial active pillar array. The initial first active pillars 101 and the initial second active pillars 102 in the initial active pillar array constitute a plurality of initial column active pillars arranged in the second direction and a plurality of initial row active pillars arranged in the third direction, the initial first active pillars 101 and the initial second active pillars 102 in each initial row active pillar being alternately arranged, each initial column active pillar including an initial first active pillar 101 or an initial second active pillar 102.

Here, fig. 5 shows a cross-sectional view at the AA' position of fig. 4.

In some specific examples, the first direction may be understood as the Z-axis direction shown in fig. 4-28, and it is understood that the first direction is not limited to the Z-axis direction. The second direction may be understood as the X-axis direction shown in fig. 4-28, and it is understood that the second direction is not limited to the X-axis direction. The third direction may be understood as the Y-axis direction shown in fig. 4-28, and it is understood that the third direction is not limited to the Y-axis direction.

Here, the intersection of the second direction and the third direction may be understood that an included angle between the second direction and the third direction is less than or equal to 90 degrees. In some specific examples, the angle between the second direction and the third direction is equal to 90 degrees.

In some specific examples, the semiconductor layer may include a substrate, which may include an elemental semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a silicon germanium (SiGe) substrate, etc.), a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. Preferably, the substrate is a silicon substrate.

Next, as shown in fig. 6, a first insulating layer 117 is formed in each of the fifth groove 135 and the sixth groove 136. In some specific examples, the material of the first insulating layer 117 includes, but is not limited to, silicon oxide, silicon nitride.

In some specific examples, the method of forming the first insulating layer 117 includes, but is not limited to, a physical vapor deposition (PVD, physical Vapor Deposition) process, a chemical vapor deposition (CVD, chemical Vapor Deposition) process, an atomic layer deposition (ALD, atomic Layer Deposition) process, and the like.

Next, as shown in fig. 7, a portion of the first insulating layer 117 is removed such that sidewalls of the top 131 and sidewalls of the middle 130 of the initial first active pillars 101 are exposed, sidewalls of the top 131 and sidewalls of the middle 130 of the initial second active pillars 102 are exposed, and a first filling region 127 is formed.

In some specific examples, the method of removing a portion of the first insulating layer 117 includes, but is not limited to, an etching process.

Next, as shown in fig. 8, the exposed sidewalls of the initial first active pillars 101 and the initial second active pillars 102 are subjected to an oxidation process to form an oxide layer 115; and a first conductive material 128 is formed in the first fill region 127.

Here, the first conductive material 128 includes, but is not limited to, polysilicon, a conductive metal, or a conductive alloy, and the conductive metal may include titanium, titanium nitride, molybdenum, tungsten, copper, or the like.

Next, as shown in fig. 9 and 10, the first conductive material 128 between the top 131 of the initial first active pillars 101 and the top 131 of the initial second active pillars 102, the middle 130 of the initial first active pillars 101, and a portion of the first conductive material 128 between the middle 130 of the initial second active pillars 102 are removed, forming a second fill region 132. Here, the remaining first conductive material 128 constitutes a plurality of word lines 114, the word lines 114 extending in the second direction, and the word lines 114 surrounding the initial first active pillars 101 and the initial second active pillars 102.

It will be appreciated that in the embodiments of the present disclosure, the word line 114 surrounds the initial first active pillar 101 and the initial second active pillar 102, so that the word line 114 surrounds the first active pillar 101 and the second active pillar 102 in the finally formed semiconductor structure, which may better inhibit the formation of leakage current and increase driving current, which is beneficial for achieving an effective balance between performance and power consumption.

Here, fig. 10 shows a sectional view at the AA' position of fig. 9.

Next, as shown in fig. 11, a sixth insulating layer 122 is formed in the second filling region 132.

In some specific examples, the sixth insulating layer 122 includes, but is not limited to, silicon oxide, silicon nitride.

In some specific examples, the method of forming the sixth insulating layer 122 includes, but is not limited to PVD, CVD, ALD.

Next, as shown in fig. 12 and 14, the top 131 of the initial first active pillars 101 and the top 131 of the initial second active pillars 102 are removed, forming first recesses 133. And the first recess 133 is enlarged in the second direction and/or the third direction to form a second recess 134, and the first active region 103 is formed in the second recess 134.

In some specific examples, the method of forming the first recess 133 includes, but is not limited to, an etching process.

Here, performing the enlarging process on the first groove 133 in the second direction and/or the third direction means removing the oxide layer 115 and a portion of the sixth insulating layer 122 in the second direction and/or the third direction within the first groove 133, so that a projected area of the formed second groove 134 on the first plane is larger than a projected area of the first groove 133 on the first plane, which is perpendicular to the first direction. Here, as shown in fig. 14, the remaining oxide layer 115 constitutes a gate oxide layer 116, the gate oxide layer 116 surrounds the first active pillars 112 and the second active pillars 113, and the word line 114 surrounds the gate oxide layer 116.

Here, since the sidewalls of the bottom portion 129 of the initial first active pillars 101 and the sidewalls of the bottom portion 129 of the initial second active pillars 102 are not oxidized, a projected area of the bottom portion 129 of the initial first active pillars 101 at a first plane is larger than a projected area of the middle portion 130 of the initial first active pillars 101 at the first plane, and a projected area of the bottom portion 129 of the initial second active pillars 102 at the first plane is larger than a projected area of the middle portion 130 of the initial second active pillars 102 at the first plane. In some specific examples, the bottom 129 of the initial first active pillars 101 and the bottom 129 of the initial second active pillars 102 may no longer be removed, such that the bottom 129 of the initial first active pillars 101 and the bottom 129 of the initial second active pillars 102 directly constitute the second active region 104, while the initial active pillars between the first active region 103 and the second active region 104 constitute the channel region 105. Here, the initial active pillar array corresponds to the formation of an active pillar array, the initial first active pillar 101 corresponds to the formation of a first active pillar 112, and the initial second active pillar 102 corresponds to the formation of a second active pillar 113. The first active columns 112 and the first active regions 103 of the second active columns 113 are all close to the first side, the first active columns 112 and the second active regions 104 of the second active columns 113 are all close to the second side, the formed first active columns 112 and second active columns 113 form a plurality of columns of active columns arranged along the second direction and a plurality of rows of active columns arranged along the third direction, the first active columns 112 and the second active columns 113 in each row of active columns are alternately arranged, and each column of active columns comprises the first active columns 112 or the second active columns 113.

It should be noted that, the first active pillars 112 and the second active pillars 113 shown in fig. 14 are alternately arranged in the second direction, but fig. 14 is only for illustration of an arrangement of the first active pillars 112 and the second active pillars 113, and is not intended to limit the arrangement of the first active pillars 112 and the second active pillars 113 in the embodiment of the present disclosure.

In some specific examples, a semiconductor material may be formed in the second recess 134, and methods of forming the semiconductor material include, but are not limited to, an epitaxial growth process, a deposition process, and then forming the first active region 103 by a doping process or a diffusion process on the semiconductor material.

In some specific examples, the semiconductor structure formed may be an N-type transistor; or may be a P-type transistor. In the N-type transistor, the doping types of the first active region 103 and the second active region 104 are both N-type doping; in the P-type transistor, the doping types of the first active region 103 and the second active region 104 are P-type doping. For example, when the doping type is P-type doping, the P-type impurity source may be boron (B), aluminum (Al), or the like, and the P-type impurity source is not limited thereto; when the doping type is N-type doping, the N-type impurity source may be phosphorus (P), arsenic (As), or the like, and the N-type impurity source is not limited thereto.

It will be appreciated that, since the projected area of the second recess 134 in the first plane is larger than the projected area of the first recess 133 in the first plane, and the first active region 103 is formed in the second recess 134, the projected area of the first active region 103 formed in the first plane is larger than the projected area of the channel region 105 in the first plane.

Here, the first active region 103 may be a source or a drain of a transistor, and the second active region 104 formed later may also be a source or a drain of a transistor. Illustratively, the first active region 103 of the first active pillar 112 may be a source and the second active region 104 of the first active pillar 112 may be a drain; the first active region 103 of the second active pillar 113 may be a drain, and the second active region 104 of the second active pillar 113 may be a source.

In other specific examples, the bottom 129 of the initial first active pillars 101 and the bottom 129 of the initial second active pillars 102 may also be removed in a subsequent process, thereby forming the second active region 104 that is larger in size in the second direction and/or the third direction. In practical applications, it may be selected whether the second active region 104 is formed to be larger in size in the second direction and/or the third direction according to specific requirements.

It can be appreciated that the projected area of the first active region 103 and the second active region 104 formed in the embodiments of the present disclosure in the first plane is larger than the projected area of the channel region 105 in the first plane, so that the contact area between the first active region 103 and the second bit line 109 and the contact area between the second active region 104 and the second memory structure 107 and the contact area between the second active region 104 and the first bit line 108 are increased, and thus the contact resistance can be reduced.

It should be noted that, in the solution provided in the above embodiment, the top 131 of the initial first active pillar 101 and the side wall of the middle 130 are subjected to oxidation treatment, and the top 131 of the initial second active pillar 102 and the side wall of the middle 130 are subjected to oxidation treatment, so that the projected area of the bottom 129 of the initial first active pillar 101 on the first plane is larger than the projected area of the middle 130 of the initial first active pillar 101 on the first plane, and the projected area of the bottom 129 of the initial second active pillar 102 on the first plane is larger than the projected area of the middle 130 of the initial second active pillar 102 on the first plane. In other specific examples, instead of performing the oxidation treatment on the sidewalls of the top 131 and the middle 130 of the initial first active pillar 101 and not performing the oxidation treatment on the sidewalls of the top 131 and the middle 130 of the initial second active pillar 102, the oxide layer 115 may be directly formed on the sidewalls of the top 131 and the middle 130 of the initial first active pillar 101 by using a deposition process, and the oxide layer 115 may be directly formed on the sidewalls of the top 131 and the middle 130 of the initial second active pillar 102 by using a deposition process, and in a subsequent process, the semiconductor layer may be subjected to a thinning treatment from the second side of the semiconductor layer to expose the bottom 129 of the initial first active pillar 101 and the bottom 129 of the initial second active pillar 102, and then the bottom 129 of the initial first active pillar 101 and the bottom 129 of the initial second active pillar 102 may be removed, thereby forming the second active region 104 having a larger size in the second direction and/or the third direction.

In step S300, a first memory structure and a second bit line are mainly formed.

In some embodiments, the second bit line extends along the third direction;

In some embodiments, forming the second bit line and the first memory structure includes:

forming a second bit line on a first side of the active pillar array;

a first memory structure is formed on the second bit line.

In some embodiments, the method further comprises:

forming a first contact structure on a first side of the active pillar array prior to forming the first memory structure; the first contact structure is for electrically connecting the first active region of the first active pillar with the first memory structure.

In some embodiments, the first active pillar is offset from the first storage structure along the second direction at a geometric center of the first planar projection; the first plane is perpendicular to the first direction.

In some embodiments, the row of active pillars comprises first and second rows of active pillars alternately arranged in the third direction; among the plurality of first storage structures electrically connected with the first row of active columns, the geometric centers of two adjacent first storage structures projected on the first plane are C1 and C2 respectively; among the plurality of first storage structures electrically connected with the second row of active columns adjacent to the first row of active columns, the first storage structure with the smallest sum of distances between the first storage structure and the C1 and the C2 is characterized in that the geometric center of the projection of the first storage structure on the first plane is C3, and connecting lines of the C1, the C2 and the C3 are equilateral triangles.

The specific process of forming the first memory structure and the second bit line will be described in detail with reference to fig. 15 to 19.

As shown in fig. 15 and 16, a second bit line 109 is formed on a first side of the active pillar array, that is, on a first face of the semiconductor layer, the second bit line 109 extending in a third direction, the second bit line 109 being connected to the first active region 103 of the second active pillar 113. In some specific examples, the bit lines may be formed by forming metal lines at preset bit line locations. The metal lines include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof.

It can be understood that the second active pillars 113 in the same column of active pillars share the same second bit line 109, and the first active pillars 112 and the second active pillars 113 are alternately arranged in the second direction, the first bit line 108 connected to the first active pillars 112 is disposed on the second side of the active pillar array in the subsequent process, the adjacent second bit lines 109 form a first contact structure 110 in the subsequent process, and the distance between the adjacent second bit lines 109 is larger, so that the parasitic capacitance between the adjacent second bit lines 109 is smaller; similarly, the distance between the adjacent first bit lines 108 formed in the subsequent process is larger, so that the parasitic capacitance between the adjacent first bit lines 108 is smaller; thereby improving the performance of the memory.

Here, fig. 16 shows a cross-sectional view at the AA' position of fig. 15, and in order to more clearly show the positional relationship of the first active pillars 112, the second active pillars 113, the word lines 114, and the second bit lines 109, the top view shown in fig. 15 is a perspective view.

Here, the first side of the active pillar array and hereinafter the second side of the active pillar array are two sides of the active pillar array that are disposed opposite in the first direction.

Here, the bit line BL is used to perform a read or write operation on a transistor and the connected memory structure when the transistor is turned on.

Next, as shown in fig. 17, a second insulating layer 118 is formed on the active pillar array, the second bit line 109 is located in the second insulating layer 118, and a first contact structure 110 is formed in the second insulating layer 118, and the first contact structure 110 is used to electrically connect the first active region 103 of the first active pillar 112 with a first memory structure formed in a subsequent process.

Connection and electrical connection are understood to mean that two parts are in physical contact so as to be directly connected, whereas two parts are indirectly connected through other parts.

Here, the geometric center of the first contact structure 110 projected at the first plane overlaps the geometric center of the first active pillar 112 projected at the first plane.

It should be noted that overlapping in embodiments of the present disclosure refers to overlapping as designed, and deviations from the process are ignored in embodiments of the present disclosure.

In some specific examples, the specific process of forming the first contact structure 110 includes: a contact hole is formed in the second insulating layer 118, and a conductive material is filled in the contact hole, thereby forming the first contact structure 110.

In some specific examples, the material of the second insulating layer 118 includes, but is not limited to, silicon nitride, silicon oxide. Methods of forming the second insulating layer 118 include, but are not limited to PVD, CVD, ALD.

Next, as shown in fig. 18 and 19, a third insulating layer 119 is formed on the second insulating layer 118, and a first memory structure 106 is formed in the third insulating layer 119, the first memory structure 106 being electrically connected to the first active region 103 of the first active column 112 through the first contact structure 110.

Here, fig. 19 shows a cross-sectional view at the AA' position of fig. 18, and the top view shown in fig. 18 is a perspective view and a partial structure is omitted in order to more clearly show the positional relationship of the first active pillars 112, the second active pillars 113, the word lines 114, the second bit lines 109, and the first memory structure 106.

In some specific examples, the material of the third insulating layer 119 includes, but is not limited to, silicon nitride, silicon oxide. Methods of forming the third insulating layer 119 include, but are not limited to PVD, CVD, ALD.

As shown in fig. 18 and 19, the geometric center of the first active pillar 112 projected on the first plane is offset from the geometric center of the first storage structure 106 projected on the first plane along the second direction.

It should be noted that, the offset in the embodiments of the present disclosure refers to an offset designed at the time of design, and an offset due to a process factor is not within the scope of the embodiments of the present disclosure.

Here, since the geometric center of the first contact structure 110 projected on the first plane overlaps the geometric center of the first active pillar 112 projected on the first plane, there is an offset between the geometric center of the first contact structure 110 projected on the first plane and the geometric center of the first storage structure 106 projected on the first plane along the second direction.

Here, as shown in fig. 18, the row of active pillars includes first row of active pillars 137 and second row of active pillars 138 alternately arranged in the third direction; the first memory structure 106 electrically connected to two first active pillars 112 belonging to the same column of active pillars in adjacent first row of active pillars 137 and second row of active pillars 138 is offset in the geometric center of the second planar projection; the second plane is perpendicular to the third direction. That is, the first memory structures 106 electrically connected to the first row of active pillars 137 are offset in opposite directions from the first memory structures 106 electrically connected to the second row of active pillars 138. As shown in fig. 18, the two first memory structures 106 electrically connected to the dashed box are active pillars of the same column of active pillars, the first memory structures 106 electrically connected to the first row of active pillars 137 are each offset along the negative X-axis direction of the geometric center of the first active pillar in the first plane projection, and the first memory structures 106 electrically connected to the second row of active pillars 138 are each offset along the positive X-axis direction of the geometric center of the first active pillar in the first plane projection.

It will be appreciated that the offset direction of the first memory structures 106 electrically connected to the first row of active pillars 137 and the first memory structures 106 electrically connected to the second row of active pillars 138 is opposite, so that the distance between the first memory structures 106 electrically connected to the first row of active pillars 137 and the first memory structures 106 electrically connected to the second row of active pillars 138 is larger, and when forming semiconductor structures having the same memory capacity, the dimensions of the semiconductor structures in the third direction are reduced, so that the area of the semiconductor structures can be reduced, which is advantageous for the miniaturization development of devices.

As shown in fig. 18, among the plurality of first storage structures 106 electrically connected to the first row of active pillars 137, two adjacent first storage structures 106 have geometric centers of C1 and C2 projected on the first plane, respectively; of the plurality of first storage structures 106 electrically connected to the second row of active pillars 138 adjacent to the first row of active pillars 137, the first storage structure 106 with the smallest sum of distances between C1 and C2 has a geometric center of C3 in the first plane projection, and the connection line of C1, C2 and C3 is in an equilateral triangle shape.

It can be understood that when the connecting lines of C1, C2 and C3 are equilateral triangles, the first memory structure is distributed more uniformly, so that the area utilization rate of the semiconductor structure is larger.

In some specific examples, forming the first storage structure 106 may include the steps of: forming a storage structure hole on the first contact structure 110; a first memory structure 106, such as a memory capacitor, is formed in the memory structure hole.

In some specific examples, the storage capacitor may take on a variety of configurations. The storage capacitor may include a CUP-shaped capacitor CUP, a cylindrical capacitor CYL, and a pillar-shaped capacitor PIL, for example. The CUP-shaped capacitor CUP, the cylindrical capacitor CYL and the pillar-shaped capacitor PIL each comprise a bottom electrode, a top electrode and a dielectric layer arranged between the bottom electrode and the top electrode.

In some specific examples, the bottom electrode is electrically connected to the first active region 103 of the first active pillar 112, the top electrode of the CUP-shaped capacitor CUP may be connected to 1/2Vcc, and the bottom electrode of the CUP-shaped capacitor CUP may be used to store written data.

When the areas of the bottom electrodes in the CUP-shaped capacitor CUP, the cylindrical capacitor CYL, and the pillar-shaped PIL are equal, the area of the top electrode of the cylindrical capacitor CYL is largest, and the areas of the top electrodes in the CUP-shaped capacitor CUP and the pillar-shaped PIL are the next. Based on this, in practical application, the cylindrical capacitor CYL can be used as a storage unit of the memory, which is beneficial to improving the integration level of the memory.

It may be appreciated that the first memory structure 106 is formed on a first side of the active pillar array, the second memory structure 107 is formed on a second side of the active pillar array in a subsequent process, the first memory structure 106 is connected to the first active region 103 of the first active pillar 112, the second memory structure 107 is connected to the second active region 104 of the second active pillar 113, the first active pillar 112 and the second active pillar 113 are alternately arranged in the second direction, the first active regions 103 of the first active pillar 112 and the second active pillar 113 are all located on the same side, and the second active regions 104 of the first active pillar 112 and the second active pillar 113 are all located on the same side, so that on the premise that the overall occupied area of the memory is unchanged, the area occupied by each of the first memory structure 106 and the second memory structure 107 is increased, on the one hand, the process difficulty of forming the first memory structure 106 and the second memory structure 107 with larger memory capacity can be reduced, and on the other hand, the first memory structure 106 and the second memory structure 107 with larger memory capacity can be formed.

In step S400, a first bit line and a second memory structure are mainly formed.

In some embodiments, the first bit line extends along the third direction;

The first bit line is connected with the second active regions of the first active pillars of the same column arranged along the third direction.

In some embodiments, forming a first bit line and a second memory structure includes:

forming a first bit line on a second side of the active pillar array;

a second memory structure is formed on the first bit line.

In some embodiments, the method further comprises:

In some embodiments, the second active pillar is offset from the second storage structure along the second direction at a geometric center of the first planar projection.

In some embodiments, among the plurality of second storage structures electrically connected to the first row of active pillars, two adjacent second storage structures are respectively C4 and C5 at the geometric center of the first planar projection; and among a plurality of second storage structures electrically connected with the second row of active columns adjacent to the first row of active columns, the second storage structure with the smallest sum of distances between the second storage structure and C4 and C5 is characterized in that the geometric center of the projection of the second storage structure on the first plane is C6, and the connecting lines of the C4, C5 and C6 are equilateral triangles.

The process of forming the first bit line and the second memory structure is described in detail below with reference to fig. 20 to 28.

In some specific examples, as shown in fig. 20, the method further comprises: the carrier layer 123 is bonded on a first side of the first memory structure 106, and the material of the carrier layer 123 includes, but is not limited to, silicon oxide.

It will be appreciated that the process operation needs to be performed on the second side of the active pillar array, that is, the second side of the semiconductor layer, and the semiconductor layer needs to be flipped over in the subsequent process, so that the first memory structure 106 is disposed under the second memory structure, and the carrier layer 123 may protect the first memory structure 106, the second bit line 109, and the first contact structure 110 from being damaged during the subsequent process.

As shown in fig. 21, the second face of the semiconductor layer is subjected to a thinning process so that the first active pillars 112 and the second active regions 104 of the second active pillars 113 are exposed.

In some specific examples, the thinning process includes, but is not limited to, a chemical mechanical polishing (CMP, chemical Mechanical Polishing) process, an etching process, and the like, on the second side of the semiconductor layer.

In some specific examples, after exposing the second active region 104 of the first active pillars 112 and the second active pillars 113, the second active region 104 may be further enlarged in size in the second direction and/or the third direction. Illustratively, the second active region 104 herein may be removed, forming a third recess; expanding the third groove along the second direction and/or the third direction to form a fourth groove; and filling the fourth groove with semiconductor material so as to form a second active region with larger size along the second direction and/or the third direction.

Next, as shown in fig. 22 and 23, a first bit line 108 is formed on the second surface, the first bit line 108 extends along the third direction, and the first bit line 108 is connected to the second active region 104 of the first active pillar 112.

Here, fig. 23 shows a cross-sectional view at the AA' position of fig. 22, and the top view shown in fig. 22 is a perspective view and a part of the structure is omitted in order to more clearly show the positional relationship of the first active pillars 112, the second active pillars 113, the word lines 114, the second bit lines 109, the first memory structures 106, and the first bit lines 108.

Next, as shown in fig. 24, a fourth insulating layer 120 is formed on the second face, the first bit line 108 is located in the fourth insulating layer 120, and a second contact structure 111 is formed in the fourth insulating layer 120, the second contact structure 111 being used to electrically connect the second active region 104 of the second active pillar 113 with a second memory structure formed in a subsequent process.

Here, the geometric center of the second contact structure 111 projected on the first plane overlaps the geometric center of the second active pillar 113 projected on the first plane.

In some specific examples, the material of the fourth insulating layer 120 includes, but is not limited to, silicon nitride, silicon oxide. Methods of forming the fourth insulating layer 120 include, but are not limited to PVD, CVD, ALD.

Next, as shown in fig. 25 and 26, a fifth insulating layer 121 is formed on the fourth insulating layer 120, and a second memory structure 107 is formed in the fifth insulating layer 121, the second memory structure 107 being electrically connected to the second active region 104 of the second active column 113 through a second contact structure 111.

Here, fig. 26 shows a cross-sectional view at the AA' position of fig. 25, and the top view shown in fig. 25 is a perspective view and a part of the structure is omitted in order to more clearly show the positional relationship of the first active pillar 112, the second active pillar 113, the word line 114, the second bit line 109, the first memory structure 106, the first bit line 108, and the second memory structure 107.

In some specific examples, the material of the fifth insulating layer 121 includes, but is not limited to, silicon nitride and silicon oxide. Methods of forming the fifth insulating layer 121 include, but are not limited to PVD, CVD, ALD.

The second storage structure 107 is similar to the first storage structure 106 in structure and manufacturing method, and will not be described again.

As shown in fig. 25 and 26, the geometric center of the second active pillar 113 projected on the first plane is offset from the geometric center of the second storage structure 107 projected on the first plane along the second direction.

Here, since the geometric center of the second contact structure 111 projected on the first plane overlaps the geometric center of the second active pillar 113 projected on the first plane, there is an offset between the geometric center of the second contact structure 111 projected on the first plane and the geometric center of the second storage structure 107 projected on the first plane along the second direction.

Here, there is an offset in the geometric center of the second planar projection of the two second memory structures 107 electrically connected to the two second active pillars 113 belonging to the same column of active pillars in the adjacent first row of active pillars 137 and second row of active pillars 138. That is, the second memory structures 107 electrically connected to the first row of active pillars 137 are offset in opposite directions from the second memory structures 107 electrically connected to the second row of active pillars 138.

As shown in fig. 25, the two second storage structures 107 outlined by the dashed box are active pillars of the same column of active pillars, the second storage structures 107 electrically connected to the first row of active pillars 137 are all offset along the negative X-axis direction of the geometric center of the second active pillar in the first plane projection, and the second storage structures 107 electrically connected to the second row of active pillars 138 are all offset along the positive X-axis direction of the geometric center of the second active pillar in the first plane projection.

It can be understood that the offset direction of the second storage structure electrically connected to the first row of active pillars is different from the offset direction of the second storage structure electrically connected to the second row of active pillars, so that the distance between the second storage structure electrically connected to the first row of active pillars and the second storage structure electrically connected to the second row of active pillars is larger, and when the semiconductor structures with the same storage capacity are formed, the size of the semiconductor structures in the third direction is reduced, thereby reducing the area of the semiconductor structures and being beneficial to the miniaturization development of devices.

In some specific examples, the first storage structure 106 overlaps with a projected portion of the second storage structure 107 in the first plane. As shown in fig. 25 and 26, the first and second memory structures electrically connected to the same row of active pillars are offset in the same direction, and as shown in fig. 25 and 26, the first and

second memory structures

106 and 107 electrically connected to the first row of active pillars 137 are each offset in the negative X-axis direction, such that the projected portions of the first and

second memory structures

106 and 107 in the first plane overlap.

In other specific examples, the first storage structure 106 overlaps with a projection of the second storage structure 107 on the first plane. As shown in fig. 27 and 28, the first and

second memory structures

106 and 107 electrically connected to the same row of active pillars are offset in opposite directions, and as shown in fig. 27 and 28, the first memory structure 106 electrically connected to the first row of active pillars 137 is offset in the negative X-axis direction, and the second memory structure 107 electrically connected to the first row of active pillars 137 is offset in the positive X-axis direction, such that the projections of the first and

second memory structures

106 and 107 in the first plane overlap.

As shown in fig. 25, among the plurality of second storage structures 107 electrically connected to the first row of active pillars, two adjacent second storage structures 107 respectively have C4 and C5 at the geometric center of the first plane projection; among the plurality of second storage structures 107 electrically connected to the second row of active pillars adjacent to the first row of active pillars, the second storage structure 107 with the smallest sum of distances between the second storage structure and the C4 and the C5 is projected at the geometric center of the first plane as C6, and the connecting lines of the C4, the C5 and the C6 are in an equilateral triangle.

It can be appreciated that when the connection lines of C4, C5 and C6 are equilateral triangles, the second memory structure is distributed more uniformly, so that the area utilization rate of the semiconductor structure is greater.

In some specific examples, (pitch of active pillars) 2: (pitch of word line) 2: (pitch of bit lines) 2 is 1:3:4.

Here, pitch of an active pillar may be understood as the spacing of the geometric centers of adjacent first and second active pillars in the same row of active pillars. Pitch of a word line can be understood as the distance of the geometric centers of two adjacent word lines. The pitch of a bit line can be understood as the distance between the geometric centers of adjacent first bit lines or the distance between the geometric centers of adjacent second bit lines.

Note that (pitch of active column) 2 given in the above embodiment: the values of (pitch of word lines) 2 (pitch of bit lines) 2 are merely exemplary and are not intended to limit (pitch of active pillars) 2 in this disclosure: (pitch of word line) 2: a value of (pitch of the bit line) 2.

In some specific examples, the semiconductor structure includes a dynamic random access memory, and the first memory structure 106 and the second memory structure 107 each include a storage capacitor.

The embodiment of the disclosure provides a manufacturing method of a semiconductor structure, which comprises the following steps: forming an active column array, wherein the active column array comprises a first active column 112 and a second active column 113 which are arranged in an array manner, each of the first active column 112 and the second active column 113 comprises a channel region 105, and a first active region 103 and a second active region 104 which are respectively positioned at two opposite ends of the channel region 105 along a first direction, and the first direction is a direction in which the channel region 105 extends; forming a word line 114, the word line 114 surrounding the first active pillars 112 and the second active pillars 113; forming a second bit line 109 and a first memory structure 106 on a first side of the active pillar array, respectively; the second bit line 109 is connected to the first active region 103 of the second active pillar 113, and the first memory structure 106 is electrically connected to the first active region 103 of the first active pillar 112; forming a first bit line 108 and a second memory structure 107 on a second side of the active pillar array, respectively; the first bit line 108 is connected to the second active region 104 of the first active pillar 112, and the second memory structure 107 is electrically connected to the second active region 104 of the second active pillar 113; the first side and the second side are opposite sides of the active pillar array along the first direction. In the embodiment of the disclosure, the first storage structure 106 and the second storage structure 107 are formed on two opposite sides of the active pillar array along the first direction, and the first bit line 108 and the second bit line 109 are formed on two opposite sides of the active pillar array along the first direction, respectively, in which, in the first aspect, the first bit line 108 and the second bit line 109 are disposed on two opposite sides of the active pillar array along the first direction, respectively, so that the number of bit lines on each side is reduced, and thus the distances between the adjacent first bit lines 108 and the adjacent second bit lines 109 are increased, and the parasitic capacitance between the adjacent first bit lines 108 and the parasitic capacitance between the adjacent second bit lines 109 are reduced, thereby improving the performance of the memory; in the second aspect, since the first storage structure 106 and the second storage structure 107 are disposed on opposite sides in the first direction, respectively, the area available for disposing the first storage structure 106 and the second storage structure 107 increases, thereby reducing the difficulty in the process when forming the storage structure having a larger storage capacity. In addition, in the embodiment of the present disclosure, the word line 114 surrounds the first active pillar 112 and the second active pillar 113, so that the formation of leakage current can be better suppressed and the driving current can be increased, which is beneficial to achieving an effective balance between performance and power consumption.

According to another aspect of the present disclosure, embodiments of the present disclosure further provide a semiconductor structure, including: the active column array comprises first active columns and second active columns which are arranged in an array manner, wherein each of the first active columns and the second active columns comprises a channel region, and a first active region and a second active region which are respectively positioned at two opposite ends of the channel region along a first direction, and the first direction is the extending direction of the channel region; a word line surrounding the first active pillar and the second active pillar; a first memory structure located on a first side of the active pillar array and electrically connected to the first active region of the first active pillar; a second storage structure located on a second side of the active pillar array and electrically connected with a second active region of the second active pillar; the first side and the second side are two opposite sides of the active pillar array along the first direction; a first bit line located on a second side of the active pillar array and connected to a second active region of the first active pillar; and the second bit line is positioned on the first side of the active column array and is connected with the first active region of the second active column.

The semiconductor structure provided by the embodiments of the present disclosure includes various types of memories. For example, NAND Flash (Flash), nors Flash, DRAM, static random access Memory (Static Random Access Memory, SRAM), and Phase-Change Memory (PCM).

In some embodiments, the semiconductor structure comprises a dynamic random access memory, and the first memory structure and the second memory structure each comprise a storage capacitor.

In the embodiments of the present disclosure, some common memories are listed only by way of example, and the protection scope of the present disclosure is not limited thereto, and any memory including the semiconductor structure provided in the embodiments of the present disclosure falls within the protection scope of the present disclosure.

In some embodiments, the first active pillar is offset from the first storage structure along the second direction at a geometric center of the first planar projection; and/or, the geometric center of the second active column projected on the first plane is offset from the geometric center of the second storage structure projected on the first plane along the second direction; the first plane is perpendicular to the first direction.

In some embodiments, the row of active pillars comprises first and second rows of active pillars alternately arranged in the third direction;

two first storage structures electrically connected with two first active pillars belonging to the same column of active pillars in adjacent first row active pillars and second row active pillars are offset in the geometric center of the second plane projection;

and/or the number of the groups of groups,

two second storage structures electrically connected with two second active pillars belonging to the same column of active pillars in adjacent first row active pillars and second row active pillars are offset in the geometric center of the second plane projection; the second plane is perpendicular to the third direction.

In some embodiments, the row of active pillars comprises first and second rows of active pillars alternately arranged in the third direction; among the plurality of first storage structures electrically connected with the first row of active columns, the geometric centers of two adjacent first storage structures projected on the first plane are C1 and C2 respectively; among a plurality of first storage structures electrically connected with a second row of active columns adjacent to the first row of active columns, the first storage structure with the smallest sum of distances between the first storage structure and C1 and C2 is projected at the geometric center of the first plane to be C3, and connecting lines of the C1, C2 and C3 are equilateral triangles;

And/or the number of the groups of groups,

In some embodiments, the first bit line and the second bit line each extend along the third direction;

In some embodiments, the semiconductor structure further includes a gate oxide layer surrounding the first active pillars and the second active pillars, the word line surrounding the gate oxide layer.

In some embodiments, the first bit line is located between the active pillar array and the second storage structure, and the second bit line is located between the active pillar array and the first storage structure.

In some embodiments, the semiconductor structure further comprises:

In some embodiments, a projection of the first storage structure on the first plane overlaps a projection of the second storage structure on the first plane.

In some embodiments, the geometric center of the first contact structure projected at the first plane overlaps the geometric center of the first active pillar projected at the first plane; the geometric center of the second contact structure projected on the first plane overlaps the geometric center of the second active pillar projected on the first plane.

The semiconductor structure provided in the above embodiments is described in detail on the method side, and will not be described here again.

According to yet another aspect of the present disclosure, the presently disclosed embodiments also provide a memory system, comprising:

one or more semiconductor structures as described in the above embodiments; and

a memory controller coupled with and controlling the semiconductor structure.

Embodiments of the present disclosure relate to semiconductor structures that will be used in subsequent processes to form at least a portion of a final device structure. Here, the final device may include a memory.

In several embodiments provided by the present disclosure, it should be understood that the disclosed apparatus and methods may be implemented in a non-targeted manner. The above described device embodiments are only illustrative, e.g. the division of the units is only one logical function division, and there may be other divisions in practice, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the components shown or discussed are coupled to each other or directly.

The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments.

The present disclosure is not limited to the specific embodiments, and any person skilled in the art, who is within the technical scope of the present disclosure, can easily conceive of changes or substitutions, which are included in the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, comprising:

a word line surrounding the first active pillar and the second active pillar;

2. The semiconductor structure of claim 1, wherein the first active pillars and the second active pillars form columns of active pillars arranged in a second direction and rows of active pillars arranged in a third direction, each row of active pillars comprising the first active pillars and the second active pillars alternately arranged, each column of active pillars comprising either a first active pillar or a second active pillar, the second direction intersecting the third direction and each perpendicular to the first direction.

3. The semiconductor structure of claim 2, wherein the word line extends along the second direction and surrounds the first active pillars and the second active pillars of the same row arranged along the second direction.

4. The semiconductor structure of claim 2, wherein the geometric center of the first active pillar in a first planar projection is offset from the geometric center of the first storage structure in the first planar projection along the second direction; and/or, the geometric center of the second active column projected on the first plane is offset from the geometric center of the second storage structure projected on the first plane along the second direction; the first plane is perpendicular to the first direction.

5. The semiconductor structure of claim 4, wherein the row of active pillars comprises first and second rows of active pillars arranged alternately in the third direction; among the plurality of first storage structures electrically connected with the first row of active columns, the geometric centers of two adjacent first storage structures projected on the first plane are C1 and C2 respectively; among a plurality of first storage structures electrically connected with a second row of active columns adjacent to the first row of active columns, the first storage structure with the smallest sum of distances between the first storage structure and C1 and C2 is projected at the geometric center of the first plane to be C3, and connecting lines of the C1, C2 and C3 are equilateral triangles;

and/or the number of the groups of groups,

6. The semiconductor structure of claim 2, wherein the first bit line and the second bit line each extend along the third direction;

7. The semiconductor structure of claim 1, further comprising a gate oxide layer surrounding the first active pillars and the second active pillars, the word line surrounding the gate oxide layer.

8. The semiconductor structure of claim 1, wherein the first bit line is located between the active pillar array and the second memory structure, and the second bit line is located between the active pillar array and the first memory structure.

9. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises:

10. The semiconductor structure of claim 1, wherein the semiconductor structure comprises a dynamic random access memory, and wherein the first memory structure and the second memory structure each comprise a storage capacitor.

11. A memory system, comprising:

one or more semiconductor structures as claimed in any one of claims 1 to 10; and

a memory controller coupled with and controlling the semiconductor structure.

12. A method of fabricating a semiconductor structure, the method comprising:

13. The method of manufacturing of claim 12, wherein the first active pillars and the second active pillars form columns of active pillars arranged in a second direction and rows of active pillars arranged in a third direction, each row of active pillars including the first active pillars and the second active pillars alternately arranged, each column of active pillars including either a first active pillar or a second active pillar, the second direction intersecting the third direction and each being perpendicular to the first direction.

14. The method of manufacturing of claim 13, wherein the word line extends along the second direction and surrounds the first active pillars and the second active pillars of the same row arranged along the second direction.

15. The method of claim 13, wherein the first active pillar is offset from the first storage structure along the second direction at a geometric center of the first planar projection; and/or, the geometric center of the second active column projected on the first plane is offset from the geometric center of the second storage structure projected on the first plane along the second direction; the first plane is perpendicular to the first direction.

16. The method of manufacturing of claim 15, wherein the rows of active pillars comprise first and second rows of active pillars alternately arranged in the third direction; among the plurality of first storage structures electrically connected with the first row of active columns, the geometric centers of two adjacent first storage structures projected on the first plane are C1 and C2 respectively; among a plurality of first storage structures electrically connected with a second row of active columns adjacent to the first row of active columns, the first storage structure with the smallest sum of distances between the first storage structure and C1 and C2 is projected at the geometric center of the first plane to be C3, and connecting lines of the C1, C2 and C3 are equilateral triangles;

and/or the number of the groups of groups,

17. The method of claim 13, wherein the first bit line and the second bit line each extend along the third direction;

18. The method of manufacturing of claim 12, further comprising: a gate oxide layer is formed surrounding the first active pillars and the second active pillars, and the word line surrounds the gate oxide layer.

19. The method of claim 12, wherein,

forming a second bit line and a first memory structure, comprising:

forming a second bit line on a first side of the active pillar array;

forming a first memory structure on the second bit line;

forming a first bit line and a second memory structure, comprising:

forming a first bit line on a second side of the active pillar array;

a second memory structure is formed on the first bit line.

20. The method of manufacturing of claim 12, further comprising: