CN115955845A

CN115955845A - Semiconductor structure, manufacturing method thereof and memory system

Info

Publication number: CN115955845A
Application number: CN202211583865.6A
Authority: CN
Inventors: 华文宇
Original assignee: ICLeague Technology Co Ltd
Current assignee: ICLeague Technology Co Ltd
Priority date: 2022-12-09
Filing date: 2022-12-09
Publication date: 2023-04-11

Abstract

The embodiment of the present disclosure discloses a semiconductor structure including: a plurality of memory cell array blocks stacked in a first direction, each memory cell array block comprising: the active column array comprises a first active column and a second active column which are arranged in an array, wherein the first active column and the second active column respectively comprise a channel region, a first active region and a second active region which are respectively positioned at two opposite ends of the channel region along a first direction, and the channel region extends along the first direction; the first storage structure is positioned on the first side of the active column array and is electrically connected with the first active area of the first active column; a second memory structure on a second side of the array of active pillars and electrically connected to a second active region of a second active pillar; the first side and the second side are two sides of the active column array opposite to each other along the first direction; the first bit line is positioned on the second side of the active column array and is connected with the second active area of the first active column; and the second bit line is positioned at the first side of the active column array and is connected with the first active area of the second active column.

Description

Semiconductor structure, manufacturing method thereof and memory system

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor structure, a method for manufacturing the same, and a memory system.

Background

A Memory array architecture of a Dynamic Random Access Memory (DRAM) is an array of Memory cells (i.e., memory cells of 1T 1C) including one transistor and one capacitor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor.

As the size of the dram continues to shrink, the size of the transistors continues to shrink. How to form a dram with a large storage capacity, a small size, and a high performance is a problem to be solved.

BRIEF SUMMARY OF THE PRESENT DISCLOSURE

The embodiment of the disclosure provides a semiconductor structure, a manufacturing method thereof and a memory system.

According to an aspect of the present disclosure, there is provided a semiconductor structure including: a plurality of memory cell array blocks stacked in a first direction, each memory cell array block comprising:

the active column array comprises a first active column and a second active column which are arranged in an array, wherein the first active column and the second active column respectively comprise a channel region, a first active region and a second active region, the first active region and the second active region are respectively positioned at two opposite ends of the channel region along the first direction, and the channel region extends along the first direction;

a first memory structure on a first side of the array of active pillars, electrically connected to a first active region of the first active pillar;

a second memory structure on a second side of the array of active pillars electrically connected to a second active region of the second active pillar; the first side and the second side are two opposite sides of the active pillar array along the first direction; the first storage structure and the second storage structure each comprise a top electrode, a bottom electrode and a dielectric layer positioned between the top electrode and the bottom electrode, and adjacent memory cell array blocks are electrically connected through the top electrode;

a first bit line on a second side of the array of active pillars, connected to a second active region of the first active pillar;

and the second bit line is positioned on the first side of the active column array and is connected with the first active area of the second active column.

In the above solution, the bottom electrode of the first memory structure is electrically connected to the first active region of the first active pillar, and the bottom electrode of the second memory structure is electrically connected to the second active region of the second active pillar.

In the above aspect, the semiconductor structure further includes a peripheral circuit, the peripheral circuit and the plurality of memory cell array blocks are stacked in the first direction, and the peripheral circuit is electrically connected to the memory cell array block.

In the above scheme, the first active pillars and the second active pillars constitute a plurality of rows of active pillars arranged along a second direction and a plurality of columns of active pillars arranged along a third direction, each row of active pillars includes the first active pillars and the second active pillars alternately arranged, each column of active pillars includes the first active pillars or the second active pillars, and the second direction intersects with the third direction and is perpendicular to the first direction.

In the above scheme, the first bit line and the second bit line both extend along the third direction;

the first bit lines are connected with the second active regions of the first active pillars in the same column arranged along a third direction;

the second bit lines are connected with the first active regions of the second active pillars in the same column arranged along a third direction.

In the above scheme, the first bit line is located between the active pillar array and the second storage structure, and the second bit line is located between the active pillar array and the first storage structure.

In the foregoing solution, the semiconductor structure further includes:

a first contact structure between the array of active pillars and the first storage structure for electrically connecting the first active region of the first active pillar with the first storage structure;

a second contact structure between the array of active pillars and the second storage structure for electrically connecting the second active region of the second active pillar with the second storage structure.

In the above scheme, the semiconductor structure includes a dynamic random access memory, and the first storage structure and the second storage structure each include a storage capacitor.

According to another aspect of the present disclosure, there is provided a memory system including: one or more semiconductor structures as described in any of the previous aspects; and

a memory controller coupled to and controlling the semiconductor structure.

According to yet another aspect of the present disclosure, there is provided a method of fabricating a semiconductor structure, the method comprising:

forming a plurality of memory cell array blocks, the plurality of memory cell array blocks being stacked in a first direction, the forming each of the memory cell array blocks including:

forming an active pillar array, wherein the active pillar array comprises a first active pillar and a second active pillar which are arranged in an array, the first active pillar and the second active pillar respectively comprise a channel region, a first active region and a second active region, the first active region and the second active region are respectively positioned at two opposite ends of the channel region along the first direction, and the channel region extends along the first direction;

forming a second bit line and a first storage structure on a first side of the active pillar array respectively; the second bit line is connected with the first active region of the second active pillar, and the first storage structure is electrically connected with the first active region of the first active pillar;

respectively forming a first bit line and a second storage structure on a second side of the active pillar array; the first bit line is connected with the second active region of the first active pillar, and the second storage structure is electrically connected with the second active region of the second active pillar; the first side and the second side are two sides of the active pillar array opposite to each other along the first direction; the first and second memory structures each include a top electrode, a bottom electrode, and a dielectric layer between the top electrode and the bottom electrode, and adjacent memory cell array blocks are electrically connected through the top electrode.

In the above scheme, the bottom electrode of the first memory structure is electrically connected to the first active region of the first active pillar, and the bottom electrode of the second memory structure is electrically connected to the second active region of the second active pillar.

In the foregoing solution, the method further includes: forming a peripheral circuit; the peripheral circuit and the plurality of memory cell array blocks are stacked in the first direction, and the peripheral circuit is electrically connected to the memory cell array blocks.

In the above scheme, the first active pillars and the second active pillars constitute a plurality of rows of active pillars arranged along the second direction and a plurality of columns of active pillars arranged along the third direction, each row of active pillars includes the first active pillars and the second active pillars arranged alternately, each column of active pillars includes the first active pillars or the second active pillars, and the second direction intersects with the third direction and is perpendicular to the first direction.

the first bit lines are connected with the second active regions of the first active columns in the same column arranged along a third direction;

In the above scheme, forming the second bit line and the first memory structure includes:

forming a second bit line on a first side of the array of active pillars;

forming a first memory structure on the second bit line;

forming a first bit line and a second memory structure, comprising:

forming a first bit line on a second side of the active pillar array;

a second storage structure is formed over the first bit line.

In the above solution, the forming the memory cell array block further includes:

forming a first contact structure on a first side of the array of active pillars before forming the first storage structure; the first contact structure is used for electrically connecting the first active region of the first active pillar with the first storage structure;

forming a second contact structure on a second side of the array of active pillars before forming the second storage structure; the second contact structure is used to electrically connect the second active region of the second active pillar with the second storage structure.

The embodiment of the disclosure provides a semiconductor structure, a manufacturing method thereof and a memory system, wherein the manufacturing method of the semiconductor structure comprises the following steps: forming a plurality of memory cell array blocks, the plurality of memory cell array blocks being stacked in a first direction, the forming each of the memory cell array blocks including: forming an active pillar array, wherein the active pillar array comprises a first active pillar and a second active pillar which are arranged in an array, the first active pillar and the second active pillar respectively comprise a channel region, a first active region and a second active region, the first active region and the second active region are respectively positioned at two opposite ends of the channel region along the first direction, and the channel region extends along the first direction; forming a second bit line and a first storage structure on a first side of the active pillar array respectively; the second bit line is connected with the first active region of the second active pillar, and the first storage structure is electrically connected with the first active region of the first active pillar; respectively forming a first bit line and a second storage structure on a second side of the active pillar array; the first bit line is connected with the second active region of the first active pillar, and the second storage structure is electrically connected with the second active region of the second active pillar; the first side and the second side are two opposite sides of the active pillar array along the first direction; the first and second memory structures each include a top electrode, a bottom electrode, and a dielectric layer between the top and bottom electrodes, and adjacent memory cell array blocks are electrically connected through the top electrode. In the embodiment of the disclosure, the plurality of memory cell array blocks are stacked along the first direction, and the adjacent memory cell array blocks are electrically connected through the top electrode, so that the memory density of the memory is improved, the area of the memory is saved, and the miniaturization of the device is facilitated; in addition, in the embodiment of the disclosure, the first storage structure and the second storage structure are respectively formed on two opposite sides of the active pillar array along the third direction, and the first bit line and the second bit line are respectively formed on two opposite sides of the active pillar array along the third direction; in the second aspect, because the first storage structure and the second storage structure are respectively arranged on two opposite sides along the third direction, the area available for arranging the first storage structure and the second storage structure is increased, and the process difficulty in forming the storage structure with large storage capacity is reduced.

Drawings

FIG. 1a is a schematic diagram of a DRAM memory cell formed by planar transistors in the related art;

FIG. 1b is a schematic diagram of a DRAM memory cell formed using a buried channel transistor in the related art;

fig. 1c is a schematic perspective view of a semiconductor structure according to an embodiment of the disclosure;

FIG. 2a is a schematic circuit diagram of a DRAM transistor provided in an embodiment of the present disclosure;

FIG. 2b is a schematic circuit diagram of a memory cell array according to an embodiment of the present disclosure;

fig. 3 is a schematic flow chart illustrating a method for manufacturing a memory cell array block according to an embodiment of the present disclosure;

fig. 4-22 are schematic cross-sectional views illustrating a manufacturing process of a semiconductor structure according to an embodiment of the present disclosure.

Detailed Description

In order to make the technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the present disclosure will be further elaborated with reference to the drawings and the embodiments. While exemplary implementations of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The present disclosure is more particularly described in the following paragraphs with reference to the accompanying drawings by way of example. Advantages and features of the present disclosure will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present disclosure.

It is understood that the meaning of "on 8230; \8230on," \8230, above "\8230; \8230, above" and "on 8230, above \8230shouldbe read in the broadest manner in this disclosure, such that" on 8230 "; above 8230not only means that it is" on something "with no intervening features or layers therebetween (i.e., directly on something), but also includes the meaning of" on "something with intervening features or layers therebetween.

Moreover, spatially relative terms such as "on 8230; \8230; above", "on 8230; above", "on", "upper", etc., may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In embodiments of the present disclosure, the term "substrate" refers to a material on which subsequent layers of material are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may comprise a variety of semiconductor materials, such as silicon, silicon germanium, arsenic, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

In embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure, or a layer may be between any horizontal pair at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along inclined surfaces. The layer may comprise a plurality of sub-layers. For example, the interconnect layers may include one or more conductors and contact sub-layers (in which interconnect lines and/or via contacts are formed), and one or more dielectric sub-layers.

In the embodiments of the present disclosure, the terms "first", "second", and the like are used for distinguishing similar objects, and are not necessarily used for describing a particular order or sequence.

Embodiments of the present disclosure relate to semiconductor structures that are to be used in subsequent processes to form at least a portion of a final device structure. Here, the final device may include a memory, including but not limited to a dynamic random access memory, which is described below as an example only.

It should be noted that the following description of the embodiment of the dynamic random access memory is only used to illustrate the present disclosure, and is not intended to limit the scope of the present disclosure.

In the related art, transistors of mainstream memories include a Planar Transistor (Planar) and a Buried Channel Transistor (BCAT), but in both the Planar Transistor and the Buried Channel Transistor, a source and a drain are located on both horizontal sides of a gate. FIG. 1a is a schematic perspective view of a semiconductor structure including a planar transistor; fig. 1b is a schematic perspective view of a semiconductor structure including a buried channel transistor. As shown in fig. 1a and 1b, the source S and the drain D of the transistor in the related art are located at both horizontal sides of the gate G, respectively. Under the structure, the source electrode and the drain electrode respectively occupy different positions, so that the area of the transistor is larger in both a planar transistor and a buried channel transistor.

In addition, since a transistor can be manufactured over a silicon substrate, the transistor can be used in various memories, for example, a DRAM. In general, a DRAM is composed of a plurality of memory cells, each memory cell is mainly composed of a Transistor and a Capacitor controlled by the Transistor, that is, the DRAM is a structure of 1 Transistor (T) and 1 Capacitor (C) (1T 1C); the main action principle is to represent whether a binary bit (bit) is l or 0 by the amount of stored charges in the capacitor. As shown in fig. 1a and 1b, the source (or drain) of a transistor in a DRAM memory cell is connected to a bit line and the drain (or source) is connected to a capacitor. For Chips formed by BCAT, chip On Board (COB) packaging is generally used to form the memory. Because the source and the drain of the planar transistor and the buried channel transistor are respectively located at two horizontal sides of the gate, the bit line and the capacitor in the DRAM memory cell are also located at the same side of the gate, and the connection among the bit line, the transistor and the capacitor, the connection between the Word Line (WL) and the transistor, and the like are also required to be realized in the subsequent process, thereby causing the circuit wiring to be complicated and the manufacturing process difficulty to be large in the memory array region of the DRAM memory.

Fig. 1c is a schematic perspective view of a semiconductor structure according to an embodiment of the disclosure; as shown in fig. 1c, the semiconductor structure includes a memory cell array 124, peripheral circuitry 125, and interconnect lines 126 connecting the memory cell array and the peripheral circuitry.

Fig. 2a is a circuit connection diagram of an architecture employing 1T1C provided in the embodiment of the present disclosure; as shown in fig. 2a, a drain of the transistor T is electrically connected to a Bit Line (BL), a source of the transistor T is electrically connected to one of the electrode plates of the capacitor C, the other electrode plate of the capacitor C may be connected to a reference voltage, which may be a ground voltage or another voltage, and a gate of the transistor T is connected to a word Line; the transistor T is controlled to be turned on or off by applying a voltage to the word line WL, and the bit line BL is used to perform a read or write operation on the transistor T when the transistor T is turned on. Fig. 2b is a schematic circuit diagram of a memory cell array provided in the embodiment of the present disclosure, and as shown in fig. 2b, the DRAM is provided with a Row Access Strobe (RAS) line input and a Column Access Strobe (CAS) line input which address a specific memory cell by means of a row address and a column address of the memory cell in order to read and write the cell.

With the development of the memory, the size of the dram is continuously reduced, and the process difficulty for forming the dram with larger storage capacity and higher performance is increasing.

Accordingly, in order to solve the above problems, embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, which can form a dram with a large storage capacity, a small size, and a high performance, and has a relatively small process difficulty.

The embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, the method including:

a plurality of memory cell array blocks are formed, and the plurality of memory cell array blocks are stacked in a first direction. Fig. 3 is a schematic flow chart illustrating a method for manufacturing a memory cell array block according to an embodiment of the present disclosure. As shown in fig. 3, a method for manufacturing a memory cell array block according to an embodiment of the present disclosure includes the following steps:

s100: forming an active column array, wherein the active column array comprises a first active column and a second active column which are arranged in an array, the first active column and the second active column respectively comprise a channel region, a first active region and a second active region, the first active region and the second active region are respectively positioned at two opposite ends of the channel region along the first direction, and the channel region extends along the first direction;

s200: forming a second bit line and a first storage structure on a first side of the active pillar array respectively; the second bit line is connected with the first active region of the second active pillar, and the first storage structure is electrically connected with the first active region of the first active pillar;

s300: respectively forming a first bit line and a second storage structure on a second side of the active pillar array; the first bit line is connected with the second active region of the first active pillar, and the second storage structure is electrically connected with the second active region of the second active pillar; the first side and the second side are two opposite sides of the active pillar array along the first direction; the first and second memory structures each include a top electrode, a bottom electrode, and a dielectric layer between the top and bottom electrodes, and adjacent memory cell array blocks are electrically connected through the top electrode.

It should be understood that the steps shown in fig. 3 are not exclusive, and that other steps may be performed before, after, or between any of the steps in the operations shown; the steps shown in fig. 3 may be sequentially adjusted according to actual requirements. Fig. 4 to fig. 22 are schematic cross-sectional views illustrating a manufacturing process of a semiconductor structure according to an embodiment of the present disclosure. It should be noted that fig. 4 to fig. 22 are schematic diagrams illustrating a complete implementation process of a manufacturing method of a semiconductor structure, and parts not labeled in some of the figures may be shared with each other. The method for fabricating the semiconductor structure according to the embodiment of the present disclosure is described in detail below with reference to fig. 3 and 4 to 22.

In step S100, an active pillar array is mainly formed, where the active pillar array includes first active pillars and second active pillars arranged in an array, and each of the first active pillars and the second active pillars includes a channel region, and first active regions and second active regions respectively located at two opposite ends of the channel region along the first direction.

In some embodiments, the first active pillars and the second active pillars constitute columns of active pillars arranged along a second direction and rows of active pillars arranged along a third direction, each row of active pillars includes the first active pillars and the second active pillars alternately arranged, each column of active pillars includes the first active pillars or the second active pillars, and the second direction intersects with the third direction and is perpendicular to the first direction.

In some specific examples, the method further comprises: word lines are formed on one side of each row of active pillars.

In some specific examples, the row of active pillars includes a first row of active pillars and a second row of active pillars arranged alternately in a third direction; the adjacent first row of active columns and second row of active columns form a row of active column units, and a dielectric layer is arranged between the adjacent row of active column units in the third direction;

the method further comprises the following steps: forming a plurality of first gate structures and a plurality of second gate structures; each first gate structure is located on one side, far away from the dielectric layer, of two sides of the first row of active columns along the third direction, and each second gate structure is located on one side, far away from the dielectric layer, of two sides of the second row of active columns along the third direction.

In some specific examples, forming the word line includes:

forming a first word line on one side of two sides of the first gate structure along the third direction, wherein the side is far away from the first row of active columns;

forming a second word line on one side, far away from the second row of active columns, of two sides of the second gate structure along the third direction; the first word line and the second word line both extend along the second direction.

The process of forming the active pillar array and the first word line, the second word line, the first gate structure, and the second gate structure will be described in detail with reference to fig. 4 to 7.

As shown in fig. 4 and 5, a semiconductor layer is provided, the semiconductor layer has a first surface and a second surface which are opposite to each other in a thickness direction of the semiconductor layer, and a plurality of first grooves are formed by removing a part of a material of the semiconductor layer from the first surface, the first grooves extending in a third direction, and the first grooves divide the semiconductor layer into a plurality of semiconductor strips 101.

Here, fig. 5 shows a cross-sectional view at AA' position of fig. 4, and the first insulating layer 115 is not shown in fig. 4.

In some specific examples, the semiconductor layer may include a substrate, which may include an elemental semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a silicon germanium (SiGe) substrate, etc.), a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. Preferably, the substrate is a silicon substrate.

In some specific examples, after forming the semiconductor strips 101, filling the first grooves with a first insulating layer 115, where the material of the first insulating layer 115 includes, but is not limited to, silicon oxide and silicon nitride.

In some specific examples, the method of filling the first insulating Layer 115 includes, but is not limited to, a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, an Atomic Layer Deposition (ALD) process, and the like.

Next, as shown in fig. 6 and 7, a portion of the first insulating layer 115 and a portion of the semiconductor strips 101 are removed to form a plurality of second grooves extending along the second direction, and the first gate structures 106, the second gate structures 107, the first word lines 110 and the second word lines 111 are formed in the second grooves.

In some specific examples, the first direction may be understood as a Z-axis direction shown in fig. 4 to 22, and it is understood that the first direction is not limited to the Z-axis direction. The second direction may be understood as an X-axis direction shown in fig. 4 to 22, and it is understood that the second direction is not limited to the X-axis direction. The third direction may be understood as a Y-axis direction shown in fig. 4 to 22, and it is understood that the third direction is not limited to the Y-axis direction.

Here, the second direction intersects with the third direction, and it is understood that an angle between the second direction and the third direction is 90 degrees or less. In some specific examples, the second direction is at an angle equal to 90 degrees to the third direction.

In some specific examples, the first gate structure 106 and the second gate structure 107 each include a gate and a gate oxide layer. The material of the gate includes, but is not limited to, polysilicon, conductive metal or conductive alloy, and the conductive metal may include titanium, titanium nitride, molybdenum, tungsten, copper, or the like. The material of the gate oxide layer includes, but is not limited to, silicon oxide. Methods of forming the gate oxide layer include, but are not limited to, PVD, CVD, ALD, and the like.

Next, a portion of the first insulating layer 115 and a portion of the semiconductor strip 101 are removed, and a plurality of third grooves 127 (positions shown in a dashed line frame in fig. 6) are formed, where the plurality of third grooves 127 extend along the second direction, and the second grooves and the third grooves jointly divide the semiconductor strip 101 into a plurality of first active pillars 102 and a plurality of second active pillars 104, and the third grooves are located between two adjacent rows of active pillars.

As shown in fig. 6 and 7, the first active regions 103 of the first active pillars 102 and the second active pillars 104 are both close to the first side, the second active regions 105 of the first active pillars 102 and the second active pillars 104 are both close to the second side, the formed first active pillars 102 and second active pillars 104 form a plurality of columns of active pillars arranged along the second direction and a plurality of rows of active pillars arranged along the third direction, the first active pillars 102 and the second active pillars 104 in each row of active pillars are alternately arranged, and each column of active pillars includes the first active pillars 102 or the second active pillars 104. The row active columns comprise first row active columns 108 and second row active columns 109 which are alternately arranged in the third direction, the adjacent first row active columns 108 and second row active columns 109 form a row active column unit, a dielectric layer is filled in the third groove in the subsequent process, the adjacent row active column units in the third direction can be separated by the dielectric layer, the first gate structure 106 is positioned on one side, far away from the dielectric layer, of two sides of the channel region of the first row active column 108 in the third direction, and the second gate structure 107 is positioned on one side, far away from the dielectric layer, of two sides of the channel region of the second row active column 109 in the third direction. The first word line 110 is formed on one side of two sides of the first gate structure 106 along the third direction, which is far away from the channel regions of the first row of active pillars 108, the second word line 111 is formed on one side of two sides of the second gate structure 107 along the third direction, which is far away from the channel regions of the second row of active pillars 109, and both the first word line 110 and the second word line 111 extend along the second direction.

Here, fig. 7 illustrates a cross-sectional view at AA' of fig. 6, and in order to more clearly show a positional relationship among the first gate structure 106, the second gate structure 107, the first active pillar 102, the second active pillar 104, the first word line 110, and the second word line 111, the top view illustrated in fig. 6 is a perspective view, and the first insulating layer 115 is omitted.

It should be noted that the first active pillars 102 and the second active pillars 104 shown in fig. 6 and fig. 7 are alternately arranged in the second direction, but fig. 6 and fig. 7 only show an example of an arrangement of the first active pillars 102 and the second active pillars 104, and are not used to limit the arrangement of the first active pillars 102 and the second active pillars 104 in the embodiment of the present disclosure.

In some specific examples, the method of forming the first recess, the second recess, and the third recess includes, but is not limited to, a dry plasma etching process.

Next, a dielectric layer is formed in the third recess, and in some specific examples, a cavity is formed in the dielectric layer to isolate adjacent transistors and reduce mutual interference between adjacent transistors. In other embodiments, the dielectric layer may be filled with a metal shielding layer, and a fixed voltage may be applied to the metal shielding layer to reduce mutual interference between adjacent transistors.

In some specific examples, after the first and second

active pillars

102 and 104 are formed, the first and second

active regions

103 and 105 may be formed at both end portions of the first and second

active pillars

102 and 104 in a thickness direction of the semiconductor layer.

In some specific examples, the active pillar between the first active region 103 and the second active region 105 forms a channel region of the transistor, and the gate oxide layer is located between the gate and the channel region for electrically isolating the channel region from the gate and reducing a hot carrier effect of the transistor.

Here, the first active region 103 may be a source or a drain of a transistor, and the second active region 105 may also be a source or a drain of a transistor. For example, the first active region 103 of the first active pillar 102 may be a source, and the second active region 105 of the first active pillar 102 may be a drain; the first active region 103 of the second active pillar 104 may be a drain, and the second active region 105 of the second active pillar 104 may be a source.

In some specific examples, the method of forming the first active region 103 and the second active region 105 includes, but is not limited to, a doping process, a diffusion process, and the like. In some specific examples, the semiconductor structure formed may be an N-type transistor; or may be a P-type transistor.

In the N-type transistor, the doping types of a source electrode and a drain electrode are both N-type doping; in the P-type transistor, the doping types of the source electrode and the drain electrode are both P-type doping. For example, when the doping type is P-type doping, the P-type impurity source may be boron (B), aluminum (Al), or the like, and the P-type impurity source is not limited thereto; when the doping type is N-type doping, the N-type impurity source may be phosphorus (P), arsenic (As), or the like, and is not limited thereto.

In addition, although the above embodiments exemplarily illustrate the formation method of the word line and the gate structure, the formation method of the word line and the gate structure is not limited thereto. In other specific examples, the gate structure surrounds the active pillars, and the word lines surround the gate isolation structures.

In step S200, a first memory structure and a second bit line are mainly formed. The first storage structure includes: a top electrode, a bottom electrode, and a dielectric layer between the top electrode and the bottom electrode.

In some embodiments, the bottom electrode of the first memory structure is electrically connected with the first active region of the first active pillar.

In some embodiments, the second bit lines are connected to the first active regions of the second active pillars of the same column arranged in a third direction along which the second bit lines extend.

In some embodiments, forming the second bit line and the first memory structure includes:

forming a second bit line on a first side of the active pillar array;

a first memory structure is formed over the second bit line.

In some embodiments, the forming the memory cell array block further comprises:

forming a first contact structure on a first side of the array of active pillars before forming the first storage structure; the first contact structure is used to electrically connect the first active region of the first active pillar with the first storage structure.

A detailed process of forming the first memory structure and the second bit line will be described in detail with reference to fig. 8 to 12.

As shown in fig. 8 and 9, the second bit line 113 is formed on the first side of the active pillar array, that is, the first surface of the semiconductor layer, the second bit line 113 extends in the third direction, and the second bit line 113 is connected to the first active region 103 of the second active pillar 104. In some specific examples, the bit lines may be formed by forming metal lines at predetermined bit line locations. The metal line includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof.

It can be understood that the second active pillars 104 in the same column of active pillars share the same second bit line 113, and the first active pillars 102 and the second active pillars 104 are alternately arranged in the second direction, the first bit line 112 of the first active pillar 102 is disposed at the second side of the active pillar array in the subsequent process, the first contact structure 120 is formed between each second bit line 113 in the subsequent process, and the distance between the adjacent second bit lines 113 is larger, so that the parasitic capacitance between the adjacent second bit lines 113 is smaller; similarly, the distance between adjacent first bit lines 112 formed in the subsequent process is larger, so that the parasitic capacitance between the first bit lines 112 is smaller; thereby improving the performance of the memory.

Here, fig. 9 shows a cross-sectional view at AA' position of fig. 8, and in order to more clearly show the positional relationship of the first gate structure 106, the second gate structure 107, the first active pillar 102, the second active pillar 104, the first word line 110, the second word line 111, and the second bit line 113, the top view shown in fig. 8 is a perspective view, and the first insulating layer 115 and the dielectric layer are omitted.

Here, the first side of the active pillar array and, hereinafter, the second side of the active pillar array are two sides of the active pillar array that are oppositely disposed in the first direction.

It will be appreciated that the bit line BL is used to perform a read or write operation on the transistor and the connected memory structure when the transistor is turned on.

Next, as shown in fig. 10, a second insulating layer 116 is formed on the active pillar array, the second bit line 113 is located in the second insulating layer 116, and a first contact structure 120 is formed in the second insulating layer 116, wherein the first contact structure 120 is used to electrically connect the first active region 103 of the first active pillar 102 with a first storage structure 122 formed in a subsequent process.

As used herein, connected and electrically connected is understood to mean that two parts are in physical contact and thus directly connected, and that electrical connection means that two parts are indirectly connected through another part.

In some specific examples, a geometric center of the first contact structure 120 projected on a first plane perpendicular to the first direction overlaps with a geometric center of the first active pillar 102 projected on the first plane.

It should be noted that the overlapping in the embodiments of the present disclosure means that the overlapping is designed in design, and the deviation caused by the process is ignored in the embodiments of the present disclosure.

In some specific examples, the specific process of forming the first contact structure 120 includes: a contact hole is formed in the second insulating layer 116, and a conductive material is filled in the contact hole, thereby forming a first contact structure 120.

In some specific examples, the material of the second insulating layer 116 includes, but is not limited to, silicon nitride and silicon oxide. Methods of forming second insulating layer 116 include, but are not limited to, PVD, CVD, ALD.

Next, as shown in fig. 11 and 12, a third insulating layer 117 is formed on the second insulating layer 116, and a first memory structure 122 is formed in the third insulating layer 117, the first memory structure 122 being electrically connected to the first active region 103 of the first active pillar 102 through the first contact structure 120.

Here, fig. 12 shows a cross-sectional view at AA' position of fig. 11, and in order to more clearly show the positional relationship among the first gate structure 106, the second gate structure 107, the first active pillar 102, the second active pillar 104, the first word line 110, the second word line 111, the second bit line 113, and the first memory structure 122, the top view shown in fig. 11 is a perspective view, and a part of the structure is omitted.

In some specific examples, the material of the third insulating layer 117 includes, but is not limited to, silicon nitride and silicon oxide. Methods of forming the third insulating layer 117 include, but are not limited to, PVD, CVD, ALD.

As shown in fig. 11 and 12, the geometric center of the first active pillar 102 projected on the first plane is offset from the geometric center of the first storage structure 122 projected on the first plane along the second direction.

It should be noted that the offset in the embodiment of the present disclosure refers to an offset designed at the time of design, and the offset due to process factors is not within the protection scope of the embodiment of the present disclosure.

Here, since the geometric center of the first contact structure 120 in the first planar projection overlaps the geometric center of the first active pillar 102 in the first planar projection, the geometric center of the first contact structure 120 in the first planar projection is offset from the geometric center of the first storage structure 122 in the first planar projection along the second direction.

In some specific examples, the first storage structures 122 electrically connected to two first active pillars 102 belonging to the same column of active pillars in the adjacent first and second rows of

active pillars

108 and 109 are offset from a geometric center of the second planar projection; the second plane is perpendicular to the third direction. That is, the offset direction of the first memory structures 122 electrically connected to the first row of active pillars 108 is opposite to the offset direction of the first memory structures 122 electrically connected to the second row of active pillars 109. As shown in fig. 11, electrically connected to the two first memory structures 122 outlined by the dashed box are active pillars of the same row of active pillars, the geometric centers of the first memory structures 122 electrically connected to the first row of active pillars 108 in the first plane projection are both offset along the negative X-axis direction of the geometric centers of the first active pillars in the first plane projection, and the geometric centers of the first memory structures 122 electrically connected to the second row of active pillars 109 in the first plane projection are both offset along the positive X-axis direction of the geometric centers of the first active pillars in the first plane projection.

It can be understood that the offset directions of the first memory structures 122 electrically connected to the first row of active pillars 108 and the first memory structures 122 electrically connected to the second row of active pillars 109 are opposite, so that the distance between the first memory structures 122 electrically connected to the first row of active pillars 108 and the first memory structures 122 electrically connected to the second row of active pillars 109 is relatively large, and when semiconductor structures with the same memory capacity are formed, the size of the semiconductor structures in the third direction is reduced, so that the area of the semiconductor structures can be reduced, and the development of device miniaturization is facilitated.

In some specific examples, as shown in fig. 11, of the plurality of first memory structures 122 electrically connected to the first row of active pillars 108, the geometric centers of two adjacent first memory structures 122 in the first plane projection are C1 and C2; among the plurality of first memory structures 122 electrically connected to the second row of active pillars 109 adjacent to the first row of active pillars 108, the geometric center of the first memory structure 122 with the smallest sum of distances to C1 and C2 in the first plane projection is C3, and the connecting lines of C1, C2 and C3 are equilateral triangles.

It can be understood that when the connecting lines of C1, C2, and C3 are equilateral triangles, the first memory structures are more uniformly distributed, which results in a larger area utilization of the semiconductor structure.

In some specific examples, forming the first storage structure 122 may include the steps of: forming a storage structure hole on the first contact structure 120; a first storage structure 122, such as a storage capacitor, is formed in the storage structure hole.

As shown in fig. 12, the forming of the first memory structure includes: forming a top electrode 129, a bottom electrode 130, and a dielectric layer 131 between the top electrode 129 and the bottom electrode 130; the bottom electrode 130 of the first memory structure 122 is electrically connected to the first active region 103 of the first active pillar 102.

In some specific examples, the storage capacitor may take on a variety of configurations. Illustratively, the storage capacitor may include a CUP capacitor CUP, a cylindrical capacitor CYL, and a pillar capacitor PIL. The CUP capacitor CUP, the cylindrical capacitor CYL and the pillar capacitor PIL each include a bottom electrode, a top electrode and a dielectric layer between the bottom electrode and the top electrode.

In some specific examples, the bottom electrode is electrically connected to the first active region 103 of the first active pillar 102, the top electrode of the CUP capacitor CUP may be connected to 1/2Vcc, and the bottom electrode of the CUP capacitor CUP may be used for storing written data.

When the areas of the bottom electrodes are equal in the CUP capacitor CUP, the cylindrical capacitor CYL, and the pillar-shaped PIL, the area of the top electrode of the cylindrical capacitor CYL is the largest, and the areas of the top electrodes of the CUP capacitor CUP and the pillar-shaped PIL are the second largest. Therefore, in practical application, the cylindrical capacitor CYL can be used as a storage unit of the memory, which is beneficial to improving the integration level of the memory.

It can be understood that the first storage structures 122 are formed on the first side of the active pillar array, the second storage structures 123 are formed on the second side of the active pillar array in the subsequent process, the first storage structures 122 are connected to the first active regions 103 of the first active pillars 102, the second storage structures 123 are connected to the second active regions 105 of the second active pillars 104, and the first active pillars 102 and the second active pillars 104 are alternately arranged in the second direction, and the first active regions 103 of the first active pillars 102 and the second active pillars 104 are located on the same side, and the second active regions 105 of the first active pillars 102 and the second active pillars 104 are located on the same side, so that the area occupied by the first storage structures 122 and the second storage structures 123 on the same side of the memory is unchanged, on one hand, the difficulty in forming the first storage structures 122 and the second storage structures 123 having a larger storage capacity can be reduced, and on the other hand, the first storage structures 122 and the second storage structures 123 having a larger storage capacity can be formed on the same side.

In step S300, a first bit line and a second memory structure are mainly formed. The second storage structure includes: the memory cell array includes a top electrode, a bottom electrode, and a dielectric layer between the top electrode and the bottom electrode, and adjacent memory cell array blocks are electrically connected through the top electrode.

In some embodiments, the bottom electrode of the second memory structure is electrically connected with the second active region of the second active pillar.

In some embodiments, the first bit lines are connected to the second active regions of the first active pillars of the same column arranged in a third direction along which the first bit lines extend.

In some embodiments, forming the first bit line and the second memory structure includes:

forming a first bit line on a second side of the active pillar array;

a second storage structure is formed over the first bit line.

In some embodiments, the method further comprises:

The formation of the first bit line and the second memory structure will be described in detail with reference to fig. 13 to 22.

In some specific examples, as shown in fig. 13, the method further comprises: the carrier layer 114 is bonded to the first side of the first memory structure 122, and the material of the carrier layer 114 includes, but is not limited to, silicon oxide.

It can be understood that, in the subsequent process, a process operation needs to be performed on the second side of the active pillar array, that is, the second side of the semiconductor layer, and the semiconductor layer needs to be turned over, so that the first storage structure 122 is disposed below, and the carrier layer 114 can protect the first storage structure 122, the second bit line 113, and the first contact structure 120, and prevent the first storage structure 122, the second bit line 113, and the first contact structure 120 from being damaged in the subsequent process.

In some specific examples, the carrier layer 114 may be removed after completing the process operation at the second side of the semiconductor layer in a subsequent process.

As shown in fig. 14, the second side of the semiconductor layer is thinned, so that the first active pillars 102 and the second active regions 105 of the second active pillars 104 are exposed.

In some specific examples, the thinning process performed on the second side of the semiconductor layer includes, but is not limited to, a Chemical Mechanical Polishing (CMP) process, and an etching process.

Next, as shown in fig. 15 and fig. 16, a first bit line 112 is formed on the second surface, the first bit line 112 extends along the third direction, and the first bit line 112 is connected to the second active region 105 of the first active pillar 102. Here, fig. 16 shows a cross-sectional view at AA' position of fig. 15, and in order to show the positional relationship of the first gate structure 106, the second gate structure 107, the first active pillar 102, the second active pillar 104, the first word line 110, the second word line 111, the second bit line 113, the first memory structure 122, and the first bit line 112 more clearly, a top view shown in fig. 15 is a perspective view, and a part of the structure is omitted.

Next, as shown in fig. 17, a fourth insulating layer 118 is formed on the second surface, the first bit line 112 is located in the fourth insulating layer 118, and a second contact structure 121 is formed in the fourth insulating layer 118, the second contact structure 121 being used to electrically connect the second active region 105 of the second active pillar 104 with a second storage structure 123 formed in a subsequent process.

In some specific examples, a geometric center of the first planar projection of the second contact structure 121 overlaps a geometric center of the second active pillar 104.

In some specific examples, the material of the fourth insulating layer 118 includes, but is not limited to, silicon nitride and silicon oxide. Methods of forming the fourth insulating layer 118 include, but are not limited to, PVD, CVD, ALD.

Next, as shown in fig. 18 and 19, a fifth insulating layer 119 is formed on the fourth insulating layer 118, and a second memory structure 123 is formed in the fifth insulating layer 119, wherein the second memory structure 123 is electrically connected to the second active region 105 of the second active pillar 104 through the second contact structure 121.

Here, fig. 19 shows a cross-sectional view at AA' position of fig. 18, in order to more clearly show the positional relationship among the first gate structure 106, the second gate structure 107, the first active pillar 102, the second active pillar 104, the first word line 110, the second word line 111, the second bit line 113, the first memory structure 122, the first bit line 112, and the second memory structure 123, a top view shown in fig. 18 is a perspective view, and a part of the structure is omitted.

In some specific examples, the material of the fifth insulating layer 119 includes, but is not limited to, silicon nitride and silicon oxide. Methods of forming the fifth insulating layer 119 include, but are not limited to, PVD, CVD, ALD.

The second memory structure 123 and the first memory structure 122 are similar in structure and manufacturing method, and are not described in detail here.

In some specific examples, as shown in fig. 18 and 19, a geometric center of the second active pillar 104 projected on a first plane is offset from a geometric center of the second storage structure 123 projected on the first plane along the second direction.

Here, since the geometric center of the second contact structure 121 in the first planar projection overlaps the geometric center of the second active pillar 104 in the first planar projection, the geometric center of the second contact structure 121 in the first planar projection is offset from the geometric center of the second storage structure 123 in the first planar projection along the second direction.

In some specific examples, two second storage structures 123 electrically connected to two second active pillars 104 belonging to the same column of active pillars in adjacent first and second rows of

active pillars

108 and 109 are offset at a geometric center of the second planar projection. That is, the offset directions of the second memory structure 123 electrically connected to the first row of active pillars 108 and the second memory structure 123 electrically connected to the second row of active pillars 109 are opposite.

As shown in fig. 18, electrically connected to the two second memory structures 123 outlined by the dashed box are active pillars of the same row of active pillars, the geometric centers of the second memory structures 123 electrically connected to the first row of active pillars 108 in the first plane projection are both offset along the negative X-axis direction of the geometric centers of the second active pillars in the first plane projection, and the geometric centers of the second memory structures 123 electrically connected to the second row of active pillars 109 in the first plane projection are both offset along the positive X-axis direction of the geometric centers of the second active pillars in the first plane projection.

It can be understood that, the offset directions of the second memory structures electrically connected to the first row of active pillars and the second memory structures electrically connected to the second row of active pillars are different, so that the distance between the second memory structures electrically connected to the first row of active pillars and the second memory structures electrically connected to the second row of active pillars is larger, and when semiconductor structures with the same memory capacity are formed, the size of the semiconductor structures in the third direction is reduced, so that the area of the semiconductor structures can be reduced, and the miniaturization development of devices is facilitated.

In some specific examples, the first storage structure 122 overlaps a projection of the second storage structure 123 in the first plane. As shown in fig. 18 and 19, the first memory structures and the second memory structures electrically connected to the same row of active pillars are offset in the same direction, and as exemplarily shown in fig. 18 and 19, the first memory structures 122 and the second memory structures 123 electrically connected to the first row of active pillars 108 are both offset in the negative X-axis direction, such that the first memory structures 122 and the second memory structures 123 partially overlap in projection on the first plane.

In other specific examples, the first storage structure 122 overlaps the second storage structure 123 in the projection of the first plane. As shown in fig. 20 and 21, the first memory structures 122 and the second memory structures 123 electrically connected to the same row of active pillars are offset in opposite directions, and exemplarily as shown in fig. 20 and 21, the first memory structures 122 electrically connected to the first row of active pillars 108 are offset in the negative X-axis direction, and the second memory structures 123 electrically connected to the first row of active pillars 108 are offset in the positive X-axis direction, such that the projections of the first memory structures 122 and the second memory structures 123 on the first plane overlap.

In some specific examples, as shown in fig. 18, of the plurality of second memory structures 123 electrically connected to the first row of active pillars, the geometric centers of two adjacent second memory structures 123 in the first plane projection are C4 and C5; in the plurality of second memory structures 123 electrically connected to the second row of active pillars adjacent to the first row of active pillars, the geometric center of the projection of the second memory structure 123 with the smallest sum of distances to C4 and C5 on the first plane is C6, and the connecting line of C4, C5 and C6 is an equilateral triangle.

It can be understood that when the lines of C4, C5 and C6 are equilateral triangles, the second memory structures are more uniformly distributed, which results in a larger area utilization of the semiconductor structure.

In some specific examples, (pitch of active pillars) 2: (pitch of word line) 2: (pitch of bit line) 2 is 1.

Here, the pitch of the active pillars may be understood as a distance between a geometric center of a first active pillar and a geometric center of a second active pillar adjacent to the first active pillar in the same row of the active pillars. The pitch of a wordline can be understood as half the distance of the geometric centers of two adjacent first wordlines or half the distance of the geometric centers of two adjacent second wordlines. The pitch of the bit lines can be understood as the distance between the geometric centers of adjacent first bit lines or the distance between the geometric centers of adjacent second bit lines.

Note that, in the above embodiment, 2 (pitch of the active pillar): the value of (pitch of wordline:) 2 (pitch of bitline) 2 is exemplary only and is not intended to limit (pitch of active pillar) 2 in this disclosure: (pitch of word line) 2: (pitch of bit line) 2.

In some specific examples, the semiconductor structure includes a dynamic random access memory, and the first storage structure 122 and the second storage structure 123 each include a storage capacitor.

In some embodiments, adjacent memory cell array blocks are electrically connected through the top electrode.

In some specific examples, as shown in fig. 22, after forming the plurality of memory cell array blocks 128, the method further includes: the memory cell array block 128 is bonded, in some specific examples, by a top electrode of the memory cell array block 128, so that a plurality of memory cell array blocks are stacked in the first direction.

In some specific examples, the top electrode of the first storage structure of one memory cell array block 128 may be bonded to the top electrode of the first storage structure of another memory cell array block 128, the top electrode of the second storage structure of one memory cell array block 128 may be bonded to the top electrode of the second storage structure of another memory cell array block 128, and the top electrode of the first storage structure of one memory cell array block 128 may be bonded to the top electrode of the second storage structure of another memory cell array block 128.

It can be understood that, in the embodiments of the present disclosure, the memory cell array blocks are stacked in the first direction, which enables to increase the storage density of the memory, and greatly reduce the area compared with a memory with the same storage capacity, which is beneficial to the miniaturization development of the memory.

It should be noted that fig. 22 only shows an exemplary case where three memory cell array blocks 128 are provided in the semiconductor structure, but the number of the memory cell array blocks 128 in the semiconductor structure in the embodiment of the present disclosure is not limited.

In some embodiments, the method further comprises: forming a peripheral circuit; the peripheral circuit and the plurality of memory cell array blocks are stacked in the first direction, and the peripheral circuit is electrically connected to the memory cell array blocks.

In some specific examples, the peripheral circuit may be formed on another substrate, and then the substrate on which the peripheral circuit is formed and the substrate on which the plurality of memory cell array blocks are formed may be bonded, so that the peripheral circuit and the plurality of memory cell array blocks are stacked in the first direction. In some specific examples, the peripheral circuits and the memory cell array block may be electrically connected through an interconnection layer.

It is understood that, in the embodiments of the present disclosure, the peripheral circuit and the plurality of memory cell array blocks are stacked in the first direction, which may save the area of the memory and facilitate the miniaturization development of the memory.

The embodiment of the disclosure provides a manufacturing method of a semiconductor structure, which includes: forming a plurality of memory cell array blocks, the plurality of memory cell array blocks being stacked in a first direction, the forming each of the memory cell array blocks including: forming an active pillar array, wherein the active pillar array comprises a first active pillar 102 and a second active pillar 104 which are arranged in an array, the first active pillar 102 and the second active pillar 104 both comprise a channel region, and a first active region 103 and a second active region 105 which are respectively located at two opposite ends of the channel region along the first direction, and the channel region extends along the first direction; forming a second bit line 113 and a first memory structure 122 on a first side of the active pillar array, respectively; the second bit line 113 is connected to the first active region 103 of the second active pillar 104, and the first memory structure 122 is electrically connected to the first active region 103 of the first active pillar 102; forming a first bit line 112 and a second memory structure 123 on a second side of the active pillar array, respectively; the first bit line 112 is connected to the second active region 105 of the first active pillar 102, and the second memory structure 123 is electrically connected to the second active region 105 of the second active pillar 104; the first side and the second side are two opposite sides of the active pillar array along the first direction; the first and second memory structures 122 and 123 each include a top electrode, a bottom electrode, and a dielectric layer between the top electrode and the bottom electrode, and adjacent memory cell array blocks are electrically connected through the top electrode. In the embodiment of the disclosure, the plurality of memory cell array blocks are stacked along the first direction, and the adjacent memory cell array blocks are electrically connected through the top electrode, so that the memory density of the memory is improved, the area of the memory is saved, and the miniaturization of the device is facilitated; in addition, in the embodiment of the present disclosure, the first storage structure 122 and the second storage structure 123 are respectively formed on two opposite sides of the active pillar array along the first direction, and the first bit line 112 and the second bit line 113 are respectively formed on two opposite sides of the active pillar array along the first direction, in a first aspect, since the first bit line 112 and the second bit line 113 are respectively disposed on two opposite sides of the active pillar array along the first direction, the number of bit lines on each side is reduced, so that the distance between the adjacent first bit lines 112 and the adjacent second bit lines 113 is increased, the parasitic capacitance between the adjacent first bit lines 112 and the parasitic capacitance between the adjacent second bit lines 113 are both reduced, and thus the performance of the memory is improved; in the second aspect, since the first storage structure 122 and the second storage structure 123 are respectively disposed on two opposite sides along the first direction, the area available for disposing the first storage structure 122 and the second storage structure 123 is increased, and the process difficulty in forming a storage structure with a large storage capacity is reduced.

According to another aspect of the present disclosure, embodiments of the present disclosure further provide a semiconductor structure, including: a plurality of memory cell array blocks stacked in a first direction, each memory cell array block comprising:

the active column array comprises a first active column and a second active column which are arranged in an array, wherein the first active column and the second active column respectively comprise a channel region, a first active region and a second active region which are respectively positioned at two opposite ends of the channel region along the first direction, and the channel region extends along the first direction;

a first memory structure on a first side of the array of active pillars electrically connected to a first active region of the first active pillar;

a second memory structure on a second side of the array of active pillars electrically connected to a second active region of the second active pillar; the first side and the second side are two sides of the active pillar array opposite to each other along the first direction; the first storage structure and the second storage structure each comprise a top electrode, a bottom electrode and a dielectric layer positioned between the top electrode and the bottom electrode, and adjacent memory cell array blocks are electrically connected through the top electrode;

The semiconductor structure provided by the embodiment of the disclosure comprises various types of memories. For example, NAND Flash (Flash), nor Flash, DRAM, static Random Access Memory (SRAM), and Phase-Change Memory (PCM).

In some embodiments, the semiconductor structure comprises a dynamic random access memory, and the first and second storage structures each comprise a storage capacitor.

In the embodiments of the present disclosure, some common memories are listed by way of example, the scope of the present disclosure is not limited thereto, and any memory including the semiconductor structure provided by the embodiments of the present disclosure falls within the scope of the present disclosure.

In some embodiments, the bottom electrode of the first memory structure is electrically connected to the first active region of the first active pillar, and the bottom electrode of the second memory structure is electrically connected to the second active region of the second active pillar.

In some embodiments, the semiconductor structure further includes a peripheral circuit stacked with the plurality of memory cell array blocks in the first direction, and the peripheral circuit is electrically connected with the memory cell array blocks.

In some embodiments, the first bit line and the second bit line both extend in the third direction;

In some embodiments, the first bit line is located between the active pillar array and the second storage structure, and the second bit line is located between the active pillar array and the first storage structure.

In some embodiments, the semiconductor structure further comprises:

In some specific examples, the semiconductor structure further comprises a word line; the word lines are located on one side of each row of active pillars.

In some specific examples, the row of active pillars includes a first row of active pillars and a second row of active pillars arranged alternately in a third direction; the adjacent first row of active columns and the second row of active columns form a row of active column units, and a dielectric layer is arranged between the adjacent row of active column units in the third direction;

the semiconductor structure further includes: a plurality of first gate structures and a plurality of second gate structures; each first gate structure is located on one side, away from the dielectric layer, of the two sides of the first row of active columns in the third direction, and each second gate structure is located on one side, away from the dielectric layer, of the two sides of the second row of active columns in the third direction.

In some specific examples, the word line includes: a first word line and a second word line; the first word line and the second word line both extend in the second direction;

the first word line is positioned on one side, far away from the first row of active columns, of two sides of the first gate structure along the third direction;

the second word line is located on one of two sides of the second gate structure along the third direction, which is far away from the second row of active pillars.

The semiconductor structure provided in the above embodiments has been described in detail on the method side, and will not be described herein again.

According to still another aspect of the present disclosure, an embodiment of the present disclosure further provides a memory system, including:

one or more semiconductor structures as described in the embodiments above; and

a memory controller coupled to and controlling the semiconductor structure.

Embodiments of the present disclosure relate to semiconductor structures that are to be used in subsequent processes to form at least a portion of a final device structure. Here, the final device may include a memory.

In the several embodiments provided in the present disclosure, it should be understood that the disclosed apparatus and method may be implemented in a non-target manner. The above-described device embodiments are merely illustrative, for example, the division of the unit is only one logical function division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. Additionally, the various components shown or discussed are coupled or directly coupled to each other.

The features disclosed in the several method or apparatus embodiments provided in this disclosure may be combined in any combination to arrive at a new method or apparatus embodiment without conflict.

The scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered by the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, comprising: a plurality of memory cell array blocks stacked in a first direction, each memory cell array block comprising:

a second memory structure on a second side of the array of active pillars electrically connected to a second active region of the second active pillar; the first side and the second side are two opposite sides of the active pillar array along the first direction; the first storage structure and the second storage structure respectively comprise a top electrode, a bottom electrode and a dielectric layer positioned between the top electrode and the bottom electrode, and adjacent storage unit array blocks are electrically connected through the top electrode;

and the second bit line is positioned at the first side of the active column array and is connected with the first active area of the second active column.

2. The semiconductor structure of claim 1, wherein the bottom electrode of the first memory structure is electrically connected to the first active region of the first active pillar and the bottom electrode of the second memory structure is electrically connected to the second active region of the second active pillar.

3. The semiconductor structure of claim 1, further comprising peripheral circuitry stacked with a plurality of the memory cell array blocks along the first direction, the peripheral circuitry being electrically connected with the memory cell array blocks.

4. The semiconductor structure of claim 1, wherein the first active pillars and the second active pillars constitute columns of active pillars arranged in a second direction and rows of active pillars arranged in a third direction, each row of active pillars comprising the first active pillars and the second active pillars arranged alternately, each column of active pillars comprising either the first active pillars or the second active pillars, the second direction intersecting the third direction and being perpendicular to the first direction.

5. The semiconductor structure of claim 4, wherein the first bit line and the second bit line both extend in the third direction;

6. The semiconductor structure of claim 1, wherein the first bit line is located between the active pillar array and the second storage structure, and wherein the second bit line is located between the active pillar array and the first storage structure.

7. The semiconductor structure of claim 1, further comprising:

8. The semiconductor structure of claim 1, wherein the semiconductor structure comprises a dynamic random access memory, and wherein the first and second memory structures each comprise a storage capacitor.

9. A memory system, comprising:

one or more semiconductor structures as recited in any one of claims 1-8; and

a memory controller coupled to and controlling the semiconductor structure.

10. A method of fabricating a semiconductor structure, the method comprising:

forming an active column array, wherein the active column array comprises a first active column and a second active column which are arranged in an array, the first active column and the second active column respectively comprise a channel region, a first active region and a second active region, the first active region and the second active region are respectively positioned at two opposite ends of the channel region along the first direction, and the channel region extends along the first direction;

respectively forming a first bit line and a second storage structure on a second side of the active pillar array; the first bit line is connected with the second active region of the first active pillar, and the second storage structure is electrically connected with the second active region of the second active pillar; the first side and the second side are two opposite sides of the active pillar array along the first direction; the first and second memory structures each include a top electrode, a bottom electrode, and a dielectric layer between the top and bottom electrodes, and adjacent memory cell array blocks are electrically connected through the top electrode.

11. The method of claim 10, wherein the bottom electrode of the first memory structure is electrically connected to the first active region of the first active pillar, and wherein the bottom electrode of the second memory structure is electrically connected to the second active region of the second active pillar.

12. The method of manufacturing of claim 10, further comprising: forming a peripheral circuit; the peripheral circuit and the plurality of memory cell array blocks are stacked in the first direction, and the peripheral circuit is electrically connected to the memory cell array blocks.

13. The method of claim 10, wherein the first active pillars and the second active pillars constitute columns of active pillars arranged along a second direction and rows of active pillars arranged along a third direction, each row of active pillars comprises the first active pillars and the second active pillars alternately arranged, each column of active pillars comprises the first active pillars or the second active pillars, and the second direction intersects the third direction and is perpendicular to the first direction.

14. The method of claim 13, wherein the first bit line and the second bit line both extend along the third direction;

15. The method of manufacturing according to claim 10,

forming a second bit line and a first memory structure, comprising:

forming a second bit line on a first side of the array of active pillars;

forming a first storage structure on the second bit line;

forming a first bit line and a second memory structure, comprising:

forming a first bit line on a second side of the array of active pillars;

a second storage structure is formed over the first bit line.

16. The method of manufacturing according to claim 10, wherein the forming of the memory cell array block further comprises: