CN116568030A - Memory unit, preparation method thereof and memory - Google Patents

Memory unit, preparation method thereof and memory Download PDF

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Publication number
CN116568030A
CN116568030A CN202310611086.0A CN202310611086A CN116568030A CN 116568030 A CN116568030 A CN 116568030A CN 202310611086 A CN202310611086 A CN 202310611086A CN 116568030 A CN116568030 A CN 116568030A
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China
Prior art keywords
transistor
dielectric layer
gate
electrode
layer
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CN202310611086.0A
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Chinese (zh)
Inventor
徐汉东
金宰佑
薛兴坤
顾婷婷
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN202310611086.0A priority Critical patent/CN116568030A/en
Publication of CN116568030A publication Critical patent/CN116568030A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Semiconductor Memories (AREA)

Abstract

The disclosure provides a memory cell, a preparation method thereof and a memory, relates to the technical field of semiconductors, and is used for solving the technical problem of large occupied area of the memory cell, wherein the memory cell comprises a substrate, a first transistor and a dielectric layer; the first transistor is arranged on the substrate; the dielectric layer is arranged on the first transistor; the second transistor is arranged on the dielectric layer, and a second grid electrode of the second transistor is opposite to the first grid electrode of the first transistor and is respectively positioned at two sides of the dielectric layer in the thickness direction; the second grid electrode of the second transistor is connected with one of the first source electrode and the first drain electrode of the first transistor through a conductive plug. The memory device can reduce the occupied volume of the memory unit and improve the integration level of the memory.

Description

Memory unit, preparation method thereof and memory
Technical Field
The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a memory cell, a preparation method thereof and a memory.
Background
A dynamic random access memory (dynamic random access memory, abbreviated as DRAM) is a semiconductor memory that randomly writes and reads data at high speed, and is widely used in data storage devices or apparatuses. Dynamic random access memories are comprised of a plurality of repeating memory cells, each memory cell typically including a capacitor that stores data information and a transistor that controls the reading of the data information in a capacitive structure.
In order to increase the integration level of the memory cell, the memory cell is easily developed in the integration direction, and in the related art, the memory cell is improved, for example, the memory cell generally includes a first transistor and a second transistor connected to each other, and one of the first transistor and the second transistor is used as a memory element.
However, such a structure cannot meet the demand for a large storage capacity of the semiconductor memory, and has a drawback of limited use.
Disclosure of Invention
In view of the above problems, embodiments of the present disclosure provide a memory unit, a method for manufacturing the same, and a memory, which are used for reducing the occupied volume of the memory unit and improving the storage capacity of the memory.
A first aspect of an embodiment of the present disclosure provides a memory cell, comprising:
a substrate;
a first transistor disposed on the substrate;
the dielectric layer is arranged on the first transistor;
the second transistor is arranged on the dielectric layer, and a second grid electrode of the second transistor is opposite to the first grid electrode of the first transistor and is respectively positioned at two sides of the dielectric layer in the thickness direction; wherein the second gate of the second transistor is connected to one of the first source and the first drain of the first transistor through a conductive plug.
In some embodiments, the first transistor and the second transistor are both metal oxide thin film transistors, and the materials of the first channel layer of the first transistor and the second channel layer of the second transistor both comprise indium gallium zinc oxide.
In some embodiments, the orthographic projection of the second gate onto the substrate covers the orthographic projection of the first gate onto the substrate.
In some embodiments, the second transistor further comprises a second gate dielectric layer, a second channel layer, a second source, and a second drain;
the second gate dielectric layer is arranged on the top surface of the second gate, which is away from the first transistor, and covers the side surface of the second gate of the second transistor;
the second channel layer is arranged on one side of the second gate dielectric layer, which is away from the second gate electrode;
the second source electrode and the second drain electrode are respectively arranged at two sides of the second channel layer and cover the second gate dielectric layer at the side face of the second gate electrode; the second source electrode and the second drain electrode are also respectively connected with the top surface of the dielectric layer.
In some embodiments, a thickness of the second gate dielectric layer on the top surface of the second gate is greater than a thickness of the second gate dielectric layer on the side surface of the second gate.
In some embodiments, the second source includes a first segment and a second segment connected to the first segment, and a first preset included angle is formed between the first segment and the second segment;
the first section is arranged on the top surface of the second gate dielectric layer and is connected with the second channel layer; the second section is arranged on the dielectric layer and covers the side surface of the second gate dielectric layer;
the second drain electrode comprises a third section and a fourth section connected with the third section, and a second preset included angle is formed between the third section and the fourth section;
the third section is arranged on the top surface of the second gate dielectric layer and is connected with the second channel layer; the fourth section is arranged on the dielectric layer and covers the side face of the second gate dielectric layer.
In some embodiments, the first transistor further comprises a first gate dielectric layer and a first channel layer;
the first channel layer is arranged on the substrate, the first source electrode and the first drain electrode are respectively positioned on two sides of the first channel layer, and the top surface of the first source electrode and the top surface of the first drain electrode are flush with the top surface of the first channel layer;
the first gate dielectric layer is arranged on the first channel layer and covers the first source electrode and the first drain electrode.
A second aspect of an embodiment of the present disclosure provides a method for manufacturing a memory cell, including the steps of:
providing a substrate;
forming a first transistor on the substrate and forming a dielectric layer covering the first transistor;
forming a conductive plug in the dielectric layer;
forming a second transistor on the dielectric layer, wherein a second grid electrode of the second transistor is positioned on the surface of the dielectric layer, which is away from the first grid electrode of the first transistor, and is opposite to the first grid electrode; wherein the second gate of the second transistor is connected to one of the first source and the first drain of the first transistor through the conductive plug.
In some embodiments, the step of forming the first transistor on the substrate comprises:
forming a first channel layer on the substrate, wherein the material of the first channel layer comprises indium gallium zinc oxide;
forming a first source electrode and a first drain electrode on two sides of the first channel layer respectively, wherein the top surface of the first source electrode and the top surface of the first drain electrode are flush with the top surface of the first channel layer;
forming a first gate dielectric layer, wherein the first gate dielectric layer covers the first channel layer, the first source electrode and the first drain electrode;
And forming a first grid electrode on the first grid dielectric layer, wherein the projection of the first grid electrode on the substrate at least covers the projection of the first channel layer on the substrate.
In some embodiments, the step of forming a first source electrode and a first drain electrode on both sides of the first channel layer, respectively, includes:
forming a conductive material layer on the substrate, wherein the conductive material layer covers the first channel layer;
and removing part of the conductive material layer, wherein the conductive material layer reserved on one side of the first channel layer forms the first source electrode, and the conductive material layer reserved on the other side of the first channel layer forms the first drain electrode.
In some embodiments, the step of forming the conductive plug within the dielectric layer includes:
patterning the dielectric layer to form a filling hole in the dielectric layer; the filling hole also penetrates through the first gate dielectric layer and exposes the top surface of the first source electrode or the first drain electrode;
and forming a conductive plug in the filling hole.
In some embodiments, the conductive plugs taper in diameter from the dielectric layer toward the substrate.
In some embodiments, the step of forming the second transistor on the dielectric layer includes:
forming a second grid electrode on the dielectric layer, wherein the orthographic projection of the second grid electrode on the substrate covers the orthographic projection of the first grid electrode on the substrate;
forming a second gate dielectric layer wrapping the second gate;
forming a second channel layer on the second gate dielectric layer, wherein the second channel layer is opposite to the second gate electrode, and the projection area of the second channel layer on the second gate dielectric layer is smaller than the projection area of the second gate electrode on the second gate dielectric layer;
and forming a second source electrode and a second drain electrode on the dielectric layer, wherein the second source electrode and the second drain electrode are respectively positioned at two sides of the second channel layer and are connected with the exposed second gate dielectric layer.
A third aspect of embodiments of the present disclosure provides a memory comprising a substrate and a plurality of memory cells according to the first aspect; the memory units are arranged on the substrate in a plurality of rows and columns; the memory further comprises a first data line, a second data line, a third data line and a fourth data line, wherein the first data line is connected with first grid electrodes of a plurality of memory cells positioned on the same row, the second data line is connected with first source electrodes or first drain electrodes of a plurality of memory cells positioned on the same column, and the connection end of the second data line and the memory cells is different from the connection end of the conductive plug and the first transistor;
The third data line is connected with one of the second source electrodes and the first drain electrodes of the memory cells positioned on the same column, and the fourth data line is connected with the second grid electrodes of the memory cells positioned on the same row.
In the memory cell, the preparation method thereof and the memory provided by the embodiment of the disclosure, a capacitor-free 2T0C structure is provided, and the second transistor (i.e., the read transistor) is arranged above the first transistor (i.e., the write transistor), so that the first transistor and the second transistor are arranged in a stacked manner, and the first transistor and the second transistor are used as a memory cell, so that the first transistor and the second transistor are stacked along the vertical direction (Z axis), the volume occupied by the memory cell can be reduced, and the integration level and the memory capacity of the memory are further improved.
In addition, the second grid electrode of the second transistor is a top grid electrode, the first grid electrode of the first transistor is a bottom grid electrode, the first grid electrode and the bottom grid electrode are oppositely arranged and are respectively positioned on two sides of the dielectric layer in the thickness direction, so that the distance between the first grid electrode and the second grid electrode can be shortened, and when the second grid electrode is connected with one of the first source electrode and the first drain electrode of the first transistor through the conductive plug, the length of the conductive plug can be shortened, on one hand, the signal transmission between the first transistor and the second transistor is quickened, and on the other hand, the preparation of the conductive plug can be facilitated.
In addition to the technical problems, technical features constituting the technical solutions, and beneficial effects caused by the technical features of the technical solutions described above, the storage unit and the preparation method thereof, other technical problems that can be solved by the storage, other technical features included in the technical solutions, and beneficial effects caused by the technical features provided by the embodiments of the present disclosure will be described in further detail in the detailed description.
Drawings
In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, a brief description will be given below of the drawings required for the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a memory cell according to an embodiment of the disclosure;
FIG. 2 is a perspective view of a memory cell provided in an embodiment of the present disclosure;
FIG. 3 is a process flow diagram of a method for manufacturing a memory cell according to an embodiment of the disclosure;
Fig. 4 is a schematic diagram illustrating formation of a first channel layer in a method for manufacturing a memory cell according to an embodiment of the disclosure;
fig. 5 is a schematic diagram of forming a conductive material layer in a method for manufacturing a memory cell according to an embodiment of the disclosure;
fig. 6 is a schematic diagram illustrating formation of a first source and a first drain in a method for manufacturing a memory cell according to an embodiment of the disclosure;
fig. 7 is a schematic diagram of forming a first gate dielectric layer and a first gate material layer in a method for manufacturing a memory cell according to an embodiment of the disclosure;
fig. 8 is a schematic diagram illustrating formation of a first gate in a method for manufacturing a memory cell according to an embodiment of the disclosure;
fig. 9 is a schematic diagram of forming a dielectric layer in a method for manufacturing a memory cell according to an embodiment of the disclosure;
fig. 10 is a schematic diagram of forming a filling hole in a method for manufacturing a memory cell according to an embodiment of the disclosure;
FIG. 11 is a schematic diagram illustrating formation of a conductive plug in a method for fabricating a memory cell according to an embodiment of the disclosure;
fig. 12 is a schematic diagram illustrating formation of a second gate material layer in a method for manufacturing a memory cell according to an embodiment of the disclosure;
FIG. 13 is a schematic diagram illustrating formation of a second gate in a method for manufacturing a memory cell according to an embodiment of the disclosure;
Fig. 14 is a schematic diagram of forming a second gate dielectric material layer in a method for manufacturing a memory cell according to an embodiment of the disclosure;
fig. 15 is a schematic diagram of forming a second gate dielectric layer in a method for manufacturing a memory cell according to an embodiment of the present disclosure;
fig. 16 is a schematic diagram illustrating formation of a second channel material layer in a method for manufacturing a memory cell according to an embodiment of the present disclosure;
FIG. 17 is a schematic diagram illustrating formation of a second channel layer in a method for fabricating a memory cell according to an embodiment of the present disclosure;
FIG. 18 is a perspective view of a memory provided by an embodiment of the present disclosure;
fig. 19 is a circuit diagram of a memory provided by an embodiment of the present disclosure.
Reference numerals:
1000: a memory;
100: a storage unit;
110: a substrate;
120: a first transistor; 121: a first channel layer; 122: a first source electrode; 123: a first drain electrode; 124: a first gate dielectric layer; 125: a first gate; 126: a conductive material layer; 127: a first gate material layer;
130: a dielectric layer; 131: filling the hole;
140: a second transistor; 141: a second gate; 142: a second source electrode; 143: a second drain electrode; 144: a second channel layer; 145: a second gate dielectric layer; 146: a second gate material layer; 147: a second gate dielectric material layer; 148: a second channel material layer;
150: a conductive plug;
200: a first data line; 300: a second data line; 400: a third data line; 500: and a fourth data line.
Detailed Description
As described in the background art, the memory cell of the related art has a problem of large volume, and the inventor has found that the problem arises because the first transistor and the second transistor are typically arranged on the substrate in sequence in the horizontal direction, which results in a memory cell having a large volume. When a plurality of memory cells are arranged according to a certain rule to form a memory, the memory is oversized and is difficult to develop in the integration direction.
Aiming at the technical problems, the embodiment of the disclosure provides a memory cell, a preparation method thereof and a memory, wherein a second transistor is arranged above a first transistor, so that the first transistor and the second transistor are arranged in a stacked manner, and the second transistor is formed into a memory cell.
In addition, the second grid electrode of the second transistor is a top grid electrode, the first grid electrode of the first transistor is a bottom grid electrode, the first grid electrode and the bottom grid electrode are oppositely arranged and are respectively positioned on two sides of the dielectric layer in the thickness direction, so that the distance between the first grid electrode and the second grid electrode can be shortened, and when the second grid electrode is connected with one of the first source electrode and the first drain electrode of the first transistor through the conductive plug, the length of the conductive plug can be shortened, on one hand, the signal transmission between the first transistor and the second transistor is quickened, and on the other hand, the preparation of the conductive plug can be facilitated.
In order to make the above objects, features and advantages of the embodiments of the present disclosure more comprehensible, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present disclosure. Based on the embodiments in this disclosure, all other embodiments that a person of ordinary skill in the art would obtain without making any inventive effort are within the scope of the present disclosure.
Example 1
Referring to fig. 1 and 2, the disclosed embodiment provides a memory cell 100 including a substrate 110, the substrate 110 serving as a supporting member of the memory cell 100 for supporting a member disposed thereon. The substrate 110 may be a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (GeSi) substrate, a silicon carbide (SiC) substrate, a silicon-on-insulator (Silicon on Insulator, SOI) substrate, a germanium-on-insulator (Germanium on Insulator, GOI) substrate, or the like.
The memory cell 100 further includes a first transistor 120, the first transistor 120 being disposed on the substrate 110. The first transistor 120 is a metal oxide thin film transistor, which can enable the memory cell to have a higher retention time to improve the performance of the memory formed later.
The first transistor 120 includes a first channel layer 121, a first source electrode 122, a first drain electrode 123, a first gate dielectric layer 124, and a first gate electrode 125. The first channel layer 121 is disposed on the substrate 110. The material of the first channel layer 121 may include indium gallium zinc oxide, which has a high carrier mobility, so that the signal transmission speed of the first transistor 120 may be greatly increased, the power consumption of the memory cell 100 may be reduced, and the performance of the memory may be further improved. The first transistor 120 functions as a writing transistor, and electrons are transferred from the first drain 123 to the second gate 141 of the second transistor 140 after the first gate 125 is opened.
The first source electrode 122 and the first drain electrode 123 are disposed on the substrate 110 and are respectively located at both sides of the first channel layer 121. In this embodiment, the top surface of the first channel layer 121, the top surface of the first source electrode 122 and the top surface of the first drain electrode 123 are flush, so that the first gate dielectric layer 124 is disposed, and the difficulty in manufacturing the first transistor 120 is reduced.
The first gate dielectric layer 124 is disposed on the first channel layer 121 and covers the first source electrode 122 and the first drain electrode 123. The first gate dielectric layer 124 has a higher dielectric constant, which can effectively prevent electrons from directly tunneling through the first gate dielectric layer 124 to generate gate leakage current, thereby being beneficial to reducing the thickness of the first gate dielectric layer 124, meeting the requirement of reducing the process size, and providing guarantee for the development of the memory cell 100 in the integration direction. The material of the first gate dielectric layer 124 includes hafnium silicon oxide (HfSiO 2), aluminum oxide (Al 2O 3), hafnium oxide (HfO 2), hafnium oxynitride (HfON), zirconium oxide (ZrO 2), tantalum oxide (Ta 2O 5), titanium oxide (TiO 2), or strontium titanium oxide (SrTiO 3).
A first gate electrode 125 is disposed on the first gate dielectric layer 124. The material of the first gate electrode 125 may include one of titanium nitride, tantalum nitride, aluminum, and tungsten. For convenience of description of the positional relationship between the first gate electrode 125 and the first channel layer 121, the first channel layer 121 and the first source electrode 122 and the first drain electrode 123 located at both sides of the first channel layer 121 may be collectively referred to as a first active layer. The projection of the first gate electrode 125 on the first active layer covers at least the first channel layer 121. That is, in an example, the first gate electrode 125 projected on the first active layer may cover only the first channel layer 121. In another example, the first gate electrode 125 is projected on the first active layer, covering the first channel layer 121 and a portion of the first source electrode 122 and a portion of the first drain electrode 123.
The memory cell 100 further includes a dielectric layer 130, where the dielectric layer 130 is disposed on the first transistor 120 and covers at least the top surface and the side surface of the first gate 125, for achieving an insulating arrangement between the first transistor 120 and other semiconductor devices. The material of the dielectric layer 130 may include silicon oxide, silicon nitride, or other insulating materials.
The memory cell 100 further includes a second transistor 140, where the second transistor 140 is disposed on the dielectric layer 130, and a second gate 141 of the second transistor 140 is disposed opposite to the first gate 125 of the first transistor 120 and is located on two sides of the dielectric layer 130 in the thickness direction. That is, the second gate 141 is disposed on a surface of the dielectric layer 130 facing away from the first transistor 120. The second transistor 140 is used as a reading transistor, the second gate 141 is connected to the first drain 123 through the conductive plug 150, and electrons are transmitted to the second gate 141 of the reading transistor through the first drain 123, so that the second gate 141 is controlled to be switched, and corresponding data can be read from the reading transistor.
The second transistor 140 is a metal oxide thin film transistor, which can improve the performance of the memory formed later. And the second channel layer 144 material of the second transistor 140 may include indium gallium zinc oxide, which has a higher carrier mobility, so that the sensitivity of the second transistor 140 can be greatly improved, the power consumption of the memory cell 100 is reduced, and the performance of the memory is further improved.
In this embodiment, the second transistor is disposed above the first transistor, so that the first transistor and the second transistor are stacked along a vertical direction (Z axis), which can avoid the problem that the occupation area is large when the first transistor and the second transistor are sequentially arranged in a horizontal direction, and reduce the storage integration density.
The second gate 141 of the second transistor 140 is connected to one of the first source 122 and the first drain 123 of the first transistor 120 through the conductive plug 150 such that the first transistor 120 functions as a write transistor and the second transistor 140 functions as a read transistor.
In this embodiment, the second gate 141 of the second transistor 140 is disposed opposite to the first gate 125 of the first transistor 120 and is located on two sides of the dielectric layer 130 in the thickness direction, so that the vertical distance between the first gate 125 and the second gate 141 can be shortened, and thus, the length of the conductive plug 150 can be shortened, on one hand, the signal transmission between the first transistor 120 and the second transistor 140 can be accelerated, and on the other hand, the preparation of the conductive plug 150 can be facilitated.
In one possible implementation, please continue to refer to fig. 1, the orthographic projection of the second gate 141 on the substrate 110 covers the orthographic projection of the first gate 125 on the substrate 110, and further, for example, may cover at least a portion of the orthographic projection of the first source 122 and/or the first drain 123 on the substrate 110. That is, the second gate electrode 141 projects on the first active layer to cover the first gate electrode 125, a portion of the first source electrode 122, and/or a portion of the first drain electrode 123. By this arrangement, the connection between the second gate 141 and the first source 122 or the first drain 123 can be facilitated, so that the conductive plug 150 extends along the direction perpendicular to the substrate 110 as much as possible, and the difficulty in preparing the conductive plug 150 is reduced.
In one possible implementation, with continued reference to fig. 1 and 2, the second transistor 140 further includes a second gate dielectric layer 145, a second channel layer 144, a second source 142, and a second drain 143.
The second gate dielectric layer 145 is disposed on the top surface of the second gate 141 facing away from the first transistor 120 and covers the side surface of the second gate 141 of the second transistor 140; thus, the gate electrode, the source electrode and the drain electrode, and the gate electrode and the channel are isolated, and are prevented from being electrically connected, so that the yield of the memory cell 100 is improved. The second gate dielectric layer 145 may also have a larger dielectric constant, and the advantage thereof may be referred to the description of the first gate dielectric layer 124, which is not repeated here in this embodiment.
In this embodiment, the thicknesses of the second gate dielectric layers 145 may be equal everywhere, or may be unequal. Illustratively, the thickness of the second gate dielectric layer 145 on the top surface of the second gate 141 is greater than the thickness of the second gate dielectric layer 145 on the sides of the second gate 141.
The thickness of the second gate dielectric layer 145 between the top surface of the second gate 141 and the second channel layer 144 is larger, so that the gate leakage current generated by electrons directly tunneling through the first gate dielectric layer 124 can be effectively avoided, and the yield of the memory cell 100 is improved. Accordingly, the thickness of the second gate dielectric layer 145 between the side surface of the second gate electrode 141 and the second source electrode 142, and the thickness of the second gate dielectric layer 145 between the side surface of the second gate electrode 141 and the second drain electrode 143 are smaller, so that the area of the second source electrode 142 and the area of the second drain electrode 143 can be increased on the premise of ensuring the insulation performance between the second gate electrode 141 and the second source electrode 142, and between the second gate electrode 141 and the second drain electrode 143, thereby facilitating the connection of the conductive plug 150 and the second source electrode 142 or the second drain electrode 143, and reducing the manufacturing difficulty of the memory cell 100.
The second channel layer 144 is disposed on a side of the second gate dielectric layer 145 facing away from the second gate electrode 141; the second source electrode 142 and the second drain electrode 143 are respectively disposed at two sides of the second channel layer 144, cover the second gate dielectric layer 145 at the side of the second gate electrode 141, and are connected to the top surface of the dielectric layer 130.
In an example, the second source 142 includes a first segment 1421 and a second segment 1422. The second section 1422 is connected to the first section 1421, and a first preset included angle is formed between the first section 1421 and the second section 1422; the first predetermined angle is 90 degrees, so that the second source 142 forms an L-shaped structure.
The first segment 1421 is disposed on the top surface of the second gate dielectric layer 145 and is connected to the second channel layer 144, that is, the first segment 1421 covers the side surface of the second channel layer 144. The second segment 1422 is disposed over the dielectric layer 130 and covers the sides of the second gate dielectric layer 145.
The second drain electrode 143 includes a third segment 1431 and a fourth segment 1432, the third segment 1431 is connected with the fourth segment 1432, and a second preset included angle is formed between the third segment 1431 and the fourth segment 1432; the second preset included angle is 90 degrees, so that the second drain electrode 143 forms an L-shaped structure.
The third segment 1431 is disposed on the top surface of the second gate dielectric layer 145 and is connected to the second channel layer 144, that is, the third segment 1431 covers the side surface of the second channel layer 144. The fourth segment 1432 is disposed on the dielectric layer 130 and overlies a side of the second gate dielectric layer 145.
In this embodiment, the shapes of the second source 142 and the second drain 143 are L-shaped, so that the lengths of the second source 142 and the second drain 143 in the direction perpendicular to the substrate 110 can be extended, the vertical distance between the second source 142 or the second drain 143 and the first gate 125 of the first transistor 120 is facilitated, the preparation of the conductive plug 150 is facilitated, and the preparation difficulty of the memory cell 100 is reduced.
Example two
Referring to fig. 3, an embodiment of the disclosure further provides a method for manufacturing a memory cell, including the following steps:
step 100: a substrate is provided.
The substrate 110 serves as a supporting member of the memory cell 100 for supporting the components disposed thereon. The substrate 110 may be a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (GeSi) substrate, a silicon carbide (SiC) substrate, a silicon-on-insulator (Silicon on Insulator, SOI) substrate, a germanium-on-insulator (Germanium on Insulator, GOI) substrate, or the like.
Step S200: a first transistor is formed on a substrate, and a dielectric layer is formed overlying the first transistor.
Referring to fig. 4, step S210: forming a first channel layer 121 on a substrate 110, the material of the first channel layer 121 including indium gallium zinc oxide; illustratively, a first channel material layer is formed on the substrate 110 using a deposition process, after which the first channel material layer is patterned, a portion of the first channel material layer is removed, and the remaining first channel material layer constitutes the first channel layer 121. Among them, the deposition process includes chemical vapor deposition (Chemical Vapor Deposition, CVD for short), physical vapor deposition (Physical Vapor Deposition, PVD for short), or atomic layer deposition (Atomic Layer Deposition, ALD for short).
Step S220: and forming a first source electrode and a first drain electrode on two sides of the first channel layer respectively, wherein the top surface of the first source electrode and the top surface of the first drain electrode are flush with the top surface of the first channel layer.
For example, referring to fig. 5, a conductive material layer 126 is formed on the substrate 110, and the conductive material layer 126 is covered on the first channel layer 121.
Thereafter, referring to fig. 6, a portion of the thickness of the conductive material layer 126 is removed by an etching process or a chemical mechanical polishing process (Chemical Mechanical Polishing, CMP for short), i.e., the conductive material layer 126 on the top surface of the first channel layer 121 is removed.
The conductive material layer 126 remaining on one side of the first channel layer 121 constitutes the first source electrode 122, and the conductive material layer 126 remaining on the other side of the first channel layer 121 constitutes the first drain electrode 123.
Step S230: a first gate dielectric layer is formed, and the first gate dielectric layer covers the first channel layer, the first source electrode and the first drain electrode, and the structure of the first gate dielectric layer can be referred to as fig. 7.
Step S240: and forming a first grid electrode on the first grid dielectric layer, wherein the projection of the first grid electrode on the substrate at least covers the projection of the first channel layer on the substrate.
For example, referring to fig. 7 and 8, a first gate material layer 127 is formed to cover the first gate dielectric layer 124, then the first gate material layer 127 is patterned, a portion of the first gate material layer 127 is removed, and the remaining first gate material layer 127 forms the first gate 125.
The projection of the first gate 125 onto the substrate 110 covers at least the projection of the first channel layer 121 onto the substrate 110. That is, the projection of the first gate electrode 125 onto the substrate 110 also covers the portion of the projection of the first source electrode 122 and/or the first drain electrode 123 onto the substrate 110.
After the first transistor 120 is formed, referring to fig. 9, a dielectric layer 130 is formed on the exposed first gate dielectric layer 124 by using a deposition process, the dielectric layer 130 is further wrapped around the side and top surfaces of the first gate 125 of the first transistor 120, and the top surface of the dielectric layer 130 is higher than the top surface of the first gate 125.
Step S300: and forming a conductive plug in the dielectric layer.
Referring to fig. 10, the dielectric layer 130 is patterned to form a filling hole 131 in the dielectric layer 130. In an example, the filling hole 131 penetrates through the dielectric layer 130 opposite to the first source electrode 122 or the first drain electrode 123 and then penetrates through the first gate dielectric layer 124, so that the filling hole 131 exposes the surface of the first source electrode 122 or the first drain electrode 123.
Then, referring to fig. 11, a material layer is formed in the filling hole 131 by using a deposition process, and the material layer extends to the filling hole 131 and covers the dielectric layer 130. Then, the material layer on the top surface of the dielectric layer 130 is removed by an etching process or a chemical mechanical polishing process, and the material layer remaining in the filling hole 131 constitutes the conductive plug 150.
The diameters of the conductive plugs 150 may be the same throughout, or may be different. Illustratively, the diameter of the conductive plugs 150 is gradually reduced from the dielectric layer 130 toward the substrate 110 such that the conductive plugs 150 are inverted trapezoidal in shape.
Step S400: forming a second transistor on the dielectric layer, wherein a second grid electrode of the second transistor is positioned on the surface of the dielectric layer, which is away from the first grid electrode of the first transistor, and is opposite to the first grid electrode; the second grid electrode of the second transistor is connected with one of the first source electrode and the first drain electrode of the first transistor through a conductive plug.
In the memory cell 100 manufactured by the above method for manufacturing a memory cell, the second transistor 140 is disposed above the first transistor 120, so that the first transistor 120 and the second transistor 140 are stacked, and the first transistor 120 is used as a memory element, so that the volume occupied by the memory cell 100 can be reduced, and the integration level of the memory can be further improved.
In addition, the second gate 141 of the second transistor 140 is disposed opposite to the first gate 125 of the first transistor 120 and is located at two sides of the dielectric layer 130 in the thickness direction, so that the distance between the first gate 125 and the second gate 141 can be shortened, and when the second gate 141 is connected to one of the first source 122 and the first drain 123 of the first transistor 120 through the conductive plug 150, the length of the conductive plug 150 can be shortened, so that signal transmission between the first transistor 120 and the second transistor 140 can be accelerated, and the preparation of the conductive plug 150 can be facilitated.
In one possible implementation, the step of forming the second transistor on the dielectric layer includes:
referring to fig. 12 and 13, a second gate 141 is formed on the dielectric layer 130 using a deposition process. Illustratively, a second gate material layer 146 is formed on the dielectric layer 130, after which the second gate material layer 146 is patterned, portions of the second gate material layer 146 are removed, and the remaining second gate material layer 146 forms the second gate 141.
An orthographic projection of the second gate 141 onto the substrate 110, covering an orthographic projection of the first gate 125 onto the substrate 110, and covering at least a portion of the orthographic projection of the first source 122 and/or the first drain 123 onto the substrate 110; that is, the area of the second gate 141 is larger than that of the first gate 125, so that there is an overlapping area between the second gate 141 and the first source 122 and/or the first drain 123, and it is convenient for one end of the conductive plug 150 to be connected to the second gate 141, and the other end of the conductive plug 150 to be connected to the first source 122 and/or the first drain 123.
Referring to fig. 14 and 15, a second gate dielectric material layer 147 is formed on the dielectric layer 130 by using a deposition process, and the second gate dielectric material layer 147 wraps the second gate electrode 141. Then, portions of the second gate dielectric material layer 147 located at both sides of the second gate electrode 141 are removed, and the remaining second gate dielectric material layer 147 constitutes the second gate dielectric layer 145. The second gate dielectric layer 145 wraps around the second gate electrode 141.
Referring to fig. 16 and 17, a second channel layer 144 is formed on the second gate dielectric layer 145, the second channel layer 144 is disposed opposite to the second gate electrode 141, and a projection area of the second channel layer 144 on the second gate dielectric layer 145 is smaller than a projection area of the second gate electrode 141 on the second gate dielectric layer 145.
For example, referring to fig. 16, a second channel material layer 148 is formed to cover the second gate dielectric layer 145, and then the second channel material layer 148 on the side surface of the second gate dielectric layer 145 and a portion of the second channel material layer 148 on the top surface of the second gate dielectric layer 145 are removed, and the remaining second channel material layer 148 forms the second channel layer 144. The area of the second channel layer 144 is smaller than the area of the second gate 141 and larger than the area of the first gate 125.
Then, referring to fig. 1, a second source 142 and a second drain 143 are formed on the dielectric layer 130, where the second source 142 and the second drain 143 are respectively located at two sides of the second channel layer 144 and are connected to the exposed second gate dielectric layer 145.
Example III
The disclosed embodiment also provides a memory, please refer to fig. 18, wherein the memory 1000 includes a substrate (not shown) and a plurality of memory cells 100 as described in one embodiment. The plurality of memory cells 100 are arranged in a multi-row multi-column array on a substrate.
The memory 1000 further includes a first data line 200, a second data line 300, a third data line 400, and a fourth data line 500.
The first data line 200 extends in the row direction, that is, the first data line 200 extends in the X direction of fig. 18, and the first data line 200 is used to connect the first gates 125 of the plurality of memory cells 100 located on the same row.
The second data line 300 (extending in the column direction, i.e., the second data line 300 extends in the Y direction of fig. 18. The second data line 300 is used to connect the first sources 122 of the plurality of memory cells 100 located on the same column.
The connection terminal of the second data line 300 and the memory cell 100 is not the same as the connection terminal of the conductive plug 150 and the first transistor 120. For example, the connection terminal of the second data line 300 and the memory cell 100 is the first source 122 of the first transistor 120, and correspondingly, the connection terminal of the conductive plug 150 and the first transistor 120 is the first drain 123.
The third data line 400 extends in the column direction. The third data line 400 is used to connect the second sources 142 of the memory cells 100 located on the same column.
The fourth data line 500 extends in the row direction. The fourth data line 500 is used to connect the second gates 141 of the plurality of memory cells 100 located on the same row.
In this embodiment, the first transistor 120 and the second transistor 140 in each memory cell 100 are stacked along the direction perpendicular to the substrate, so that the occupied volume of each memory cell 100 can be reduced, the volume of the memory 1000 can be further reduced, and the integration level of the memory 1000 can be improved.
In addition, the arrangement of the first data line 200, the second data line 300, the third data line 400 and the fourth data line 500 can facilitate connection with the memory cells 100 in the same row or column, and reduce the manufacturing difficulty of the memory 1000.
Referring to fig. 18 and 19, the data writing and reading process will be described using the second transistor 140 as a reading transistor, the first transistor 120 as a writing transistor, the first data line 200 as a writing word line, the second data line 300 as a writing bit line, the third data line 400 as a reading bit line, and the fourth data line 500 as a reading word line as an example:
the first gate 125 of the first transistor 120 is connected to a write word line; the first source 122 of the first transistor 120 is connected to the write bit line; the first drain 123 of the first transistor 120 is connected to the second gate 141 of the second transistor 140 to take the first drain 123 of the first transistor 120 as a data storage terminal.
The second source 142 of the second transistor 140 is connected to the read bit line, and the second gate 141 of the second transistor 140 is connected to the write word line.
When a high level is applied to the write word line, the high level may control the first gate of the first transistor 120 to be turned on, and the first source and the first drain of the first transistor 120 are turned on; the write bit line is charged by applying a voltage, and data "1" or "0" is stored in the first transistor 120, thereby realizing a data writing function.
If the data in the first transistor 120 needs to be read, a voltage is applied to the second gate of the second transistor 140 through the read word line, so that the second transistor 140 is turned on or off, and the read current is read through the read bit line, so as to correspondingly read out the written data "1" or "0", thereby realizing the data reading function.
In this specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on a difference from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.
In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure.
In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present disclosure, and not for limiting the same; although the present disclosure has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present disclosure.

Claims (11)

1. A memory cell, comprising:
a substrate;
a first transistor disposed on the substrate;
the dielectric layer is arranged on the first transistor;
the second transistor is arranged on the dielectric layer, and a second grid electrode of the second transistor is opposite to the first grid electrode of the first transistor and is respectively positioned at two sides of the dielectric layer in the thickness direction; the second grid electrode of the second transistor is connected with one of the first source electrode and the first drain electrode of the first transistor through a conductive plug.
2. The memory cell of claim 1, wherein the first transistor and the second transistor are each metal oxide thin film transistors, and wherein materials of the first channel layer of the first transistor and the second channel layer of the second transistor each comprise indium gallium zinc oxide.
3. The memory cell of claim 1, wherein the orthographic projection of the second gate electrode onto the substrate covers the orthographic projection of the first gate electrode onto the substrate.
4. The memory cell of claim 3, wherein the second transistor further comprises a second gate dielectric layer, a second channel layer, a second source, and a second drain;
the second gate dielectric layer is arranged on the top surface of the second gate, which is away from the first transistor, and covers the side surface of the second gate of the second transistor;
the second channel layer is arranged on one side of the second gate dielectric layer, which is away from the second gate electrode;
the second source electrode and the second drain electrode are respectively arranged at two sides of the second channel layer and cover the second gate dielectric layer at the side face of the second gate electrode; the second source electrode and the second drain electrode are also respectively connected with the top surface of the dielectric layer.
5. The memory cell of claim 4, wherein the second source comprises a first segment and a second segment connected to the first segment, the first segment and the second segment having a first predetermined angle therebetween;
the first section is arranged on the top surface of the second gate dielectric layer and is connected with the second channel layer; the second section is arranged on the dielectric layer and covers the side surface of the second gate dielectric layer;
the second drain electrode comprises a third section and a fourth section connected with the third section, and a second preset included angle is formed between the third section and the fourth section;
the third section is arranged on the top surface of the second gate dielectric layer and is connected with the second channel layer; the fourth section is arranged on the dielectric layer and covers the side face of the second gate dielectric layer.
6. The memory cell of any of claims 1-5, wherein the first transistor further comprises a first gate dielectric layer and a first channel layer;
the first channel layer is arranged on the substrate, the first source electrode and the first drain electrode are respectively positioned on two sides of the first channel layer, and the top surface of the first source electrode and the top surface of the first drain electrode are flush with the top surface of the first channel layer;
The first gate dielectric layer is arranged on the first channel layer and covers the first source electrode and the first drain electrode.
7. The preparation method of the memory unit is characterized by comprising the following steps of;
providing a substrate;
forming a first transistor on the substrate and forming a dielectric layer covering the first transistor;
forming a conductive plug in the dielectric layer;
forming a second transistor on the dielectric layer, wherein a second grid electrode of the second transistor is positioned on the surface of the dielectric layer, which is away from the first grid electrode of the first transistor, and is opposite to the first grid electrode; wherein the second gate of the second transistor is connected to one of the first source and the first drain of the first transistor through the conductive plug.
8. The method of manufacturing a memory cell according to claim 7, wherein the step of forming the first transistor over the substrate comprises:
forming a first channel layer on the substrate, wherein the material of the first channel layer comprises indium gallium zinc oxide;
forming a conductive material layer on the substrate, wherein the conductive material layer covers the first channel layer;
Removing a part of the conductive material layer, wherein the conductive material layer reserved on one side of the first channel layer forms the first source electrode, the conductive material layer reserved on the other side of the first channel layer forms the first drain electrode, and the top surface of the first source electrode and the top surface of the first drain electrode are flush with the top surface of the first channel layer;
forming a first gate dielectric layer, wherein the first gate dielectric layer covers the first channel layer, the first source electrode and the first drain electrode;
and forming a first grid electrode on the first grid dielectric layer, wherein the projection of the first grid electrode on the substrate at least covers the projection of the first channel layer on the substrate.
9. The method of claim 8, wherein forming the conductive plug in the dielectric layer comprises:
patterning the dielectric layer to form a filling hole in the dielectric layer; the filling hole also penetrates through the first gate dielectric layer and exposes the top surface of the first source electrode or the first drain electrode;
and forming a conductive plug in the filling hole.
10. The method of manufacturing a memory cell according to claim 9, wherein the step of forming the second transistor on the dielectric layer comprises:
Forming a second grid electrode on the dielectric layer, wherein the orthographic projection of the second grid electrode on the substrate covers the orthographic projection of the first grid electrode on the substrate;
forming a second gate dielectric layer wrapping the second gate;
forming a second channel layer on the second gate dielectric layer, wherein the second channel layer is opposite to the second gate electrode, and the projection area of the second channel layer on the second gate dielectric layer is smaller than the projection area of the second gate electrode on the second gate dielectric layer;
and forming a second source electrode and a second drain electrode on the dielectric layer, wherein the second source electrode and the second drain electrode are respectively positioned at two sides of the second channel layer and are connected with the exposed second gate dielectric layer.
11. A memory comprising a substrate and a plurality of memory cells according to any one of claims 1-7, a plurality of the memory cells being arranged in a plurality of rows and columns on the substrate; the memory further comprises a first data line, a second data line, a third data line and a fourth data line, wherein the first data line is connected with first grid electrodes of a plurality of memory cells positioned on the same row, the second data line is connected with first source electrodes or first drain electrodes of a plurality of memory cells positioned on the same column, and the connection end of the second data line and the memory cells is different from the connection end of the conductive plug and the first transistor;
The third data line is connected with one of a second source electrode and a second drain electrode of a plurality of memory cells positioned on the same column, and the fourth data line is connected with a second grid electrode of a plurality of memory cells positioned on the same row.
CN202310611086.0A 2023-05-24 2023-05-24 Memory unit, preparation method thereof and memory Pending CN116568030A (en)

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