RU2784405C1 - Method for manufacturing a mos transistor on a silicon-on-insulator structure - Google Patents

Abstract

FIELD: electronics.

SUBSTANCE: invention relates to the field of microelectronics, namely, to manufacturing semiconductor devices with a high value of breakdown voltage of the gate dielectric and a lower value of tunnelling current through said dielectric. A transistor well is created on an SOI plate; a silicon nitride region corresponding to the design standard of the transistor is formed. Low-alloyed source and drain region are then formed with a layer of silicon oxide thereon, the silicon nitride is removed. A silicon oxide layer is deposited, wall regions are formed by means of reactive ion etching. The gate silicon oxide is formed next, then the transistor gate is formed by depositing and mask etching polycrystalline silicon, followed by mask-free etching silicon oxide and forming the high-alloyed source and drain regions.

EFFECT: higher value of breakdown voltage of the gate dielectric of a submicron MOS transistor on the SOI structure, higher reliability of integrated circuits on such transistors.

1 cl, 9 dwg, 1 tbl

Description

The invention relates to the field of microelectronics, namely the manufacture of semiconductor devices with an increased value of the breakdown voltage of the gate dielectric and a lower value of the tunnel current through this dielectric, can be used to create highly reliable integrated circuits (ICs).

In the patent RU 2024107 C1 publ. 11/30/1994 a method for manufacturing a MOS transistor was proposed. This method involves the formation of a local protective oxide on the surface of a silicon substrate with the formed structure "silicon dioxide - silicon nitride, polycrystalline silicon, silicon nitride, silicon dioxide", in which a groove is formed, corresponding in shape to the gate electrode, and in depth equal to its thickness. The polysilicon walls of the groove are thermally oxidized, then layers of silicon nitride and silicon dioxide are removed from the bottom of the groove and a gate oxide is formed in their place, after which a layer of polycrystalline silicon is applied, equal in thickness to the gate electrode, the layer of polycrystalline silicon is planarized along the level of the upper edge of the groove, the surface of the polycrystalline The silicon in the groove is thermally oxidized, then the layers outside the gate electrode are sequentially removed to the silicon layer.

The disadvantage of this method is that the process of etching the silicon dioxide layer in the groove is isotropic (liquid method), which will lead to underetching of the spencers from the inside, and after deposition of the polysilicon layer, to the formation of voids.

Also, the formation of spacers through oxidation will also lead to the formation of a thin oxide on the silicon nitride layer, which can lead to underremoval of the silicon nitride layer.

In the article “Field-effect transistor with a submicron T-shaped gate”, obtained using a near-wall dielectric by the authors M.V. Stepanenko, B.C. Arykov, A.M. Yushchenko, A.Yu. Plotnikova, S. V. Ishutkin described a method for manufacturing a transistor formed on GaAs, where, by using a near-wall dielectric, a T-shaped gate is formed, thereby reducing the length of the rope.

The disadvantage of this solution is that when this technology is applied to a silicon-on-insulator (SOI) structure or bulk silicon, as is widely used in microelectronics, it will lead to undesirable damage to the surface of the silicon layer (channel region), since when a gap is formed in the silicon nitride layer during reactive ion etching, the semiconductor wafer will inevitably be affected. It should be taken into account that the operation of reactive ion etching is carried out with a slight overetch to the target value, that is, the effect on the semiconductor layer will be quite large, which will lead to the formation of defects in the channel and deterioration of the transistor characteristics.

The prototype of this invention is patent RU 2245589 C2 publ. 01/27/2005 bul. No. 3 "MOSFET device and method of its manufacture" by Snyder D.P. A device with a short channel for regulating electric current contains a semiconductor substrate in which a channel is formed. The gate, source, and drain electrodes are made on a semiconductor substrate so that the channel length is less than or equal to 100 nm. In the proposed design, lightly doped source and drain regions are excluded due to a decrease in the length of the transistor channel (100 nm or less), it is shown that for such design standards in such a design, it is possible to select the optimal values of impurity doses so that the transistor has the desired characteristics.

The disadvantage of this design is the low breakdown voltage of the gate dielectric.

The technical result of the proposed technical solution is to increase the value of the breakdown voltage of the gate dielectric of a submicron MOS transistor on the SOI structure, to increase the reliability of the IC on such transistors.

The technical result is achieved by the fact that in the method of manufacturing a MOS transistor based on the silicon-on-insulator (SOI) structure, including the formation of drain, source, gate, gate dielectric regions, a pocket of the transistor is created on the silicon-on-insulator plate by doping the silicon layer, further, a layer of silicon nitride is deposited on the wafer, and by means of reactive etching on the mask, a silicon nitride region is formed corresponding to the design norm of the transistor. Then, lightly doped source and drain regions are formed by ion implantation. Further, by the method of deposition of silicon oxide from the gas phase and successive planarization, silicon oxide regions are formed on the lightly doped regions of the drain, source, then the silicon nitride layer is removed by liquid etching. A layer of silicon oxide is deposited by means of low-temperature deposition from the gas phase, by means of reactive ion etching of silicon oxide, near-wall regions of silicon oxide are formed, the width of which is determined by the etching time of silicon oxide. Further, after chemical cleaning of the surface, gate silicon oxide is formed on the doped silicon layer by high-temperature oxidation. Then the gate of the transistor is formed by deposition of polycrystalline silicon and etching it on a mask, then maskless etching of silicon oxide is carried out, the formation of heavily doped source and drain regions by ion implantation and high-temperature annealing, so that the diffusion of impurities in the source and drain regions comes under the gate region at a distance equal to the width of the near-wall regions of silicon oxide.

The invention is illustrated by the following figures.

In FIG. 1-7 shows the main steps of the proposed method for manufacturing a transistor.

In FIG. 8 shows the distribution of the electric field strength in the gate dielectric of transistors: curve a - for a transistor made without near-wall regions at the gate; curve b - for a transistor with a T-shaped gate, made with near-wall regions of silicon oxide at the gate.

In FIG. Figure 9 shows the current-voltage characteristics of transistors with different widths of near-wall silicon oxide, namely: curve c - for a transistor with a near-wall dielectric width of 0.1 μm, curve d - for a transistor with a near-wall dielectric width of 0 μm (or without a near-wall dielectric) , curve e - for a transistor with a near-wall dielectric width equal to 0.05 μm.

In FIG. 1-7, the following designations are adopted:

1 - silicon substrate of the SOI structure;

2 - layer of silicon oxide (buried) of the SOI structure;

3 - silicon layer (working) of the SOI structure (pocket or channel of the transistor);

4 - layer of silicon nitride;

5 - lightly doped source region;

6 - lightly alloyed drain area;

7 - silicon oxide layer;

8 - near-wall regions of silicon oxide;

9 - layer of gate silicon oxide;

10 - polysilicon gate;

11 - region of heavily doped silicon (source);

12 - region of heavily doped silicon (stock).

The invention is carried out as follows.

Silicon layer 3 is doped on the SOI wafer, creating a transistor pocket. Next, a layer of silicon nitride 4 is deposited on the wafer and, by means of reactive etching, it is etched over a mask corresponding to the design standard (Fig. 1).

Then, by means of ion implantation, a lightly doped source silicon region 5 and a lightly doped drain region 6 are formed (Fig. 2).

Next, silicon oxide regions 7 are formed above regions 5 and 6 (Fig. 3) by the deposition of silicon oxide from the gas phase and successive planarization:

Then, the silicon nitride layer 4 is removed by wet etching, and the silicon oxide layer is deposited by low-temperature vapor deposition. By means of reactive ion etching of silicon oxide, near-wall regions 8 are formed from silicon oxide (Fig. 4), the width of which is determined by the etching time of silicon oxide and corresponds to the diffusion length under the transistor gate of the impurity in the pocket during the formation of heavily doped source and drain regions.

Further, after chemical cleaning of the surface, gate silicon oxide 9 is formed by high-temperature oxidation (Fig. 5).

The gate of the transistor 10 is then formed by depositing polycrystalline silicon and etching it on the mask (FIG. 6).

Next, maskless etching of silicon oxide 7 is carried out. The formation of heavily doped silicon regions - source 11 and drain 12 by means of ion implantation and high-temperature annealing (Fig. 7).

The figure 8 shows the distribution curves of the electric field strength in the gate dielectric. Thus, the electric field strength in the transistor of the proposed structure (curve 6 of Fig. 9) is 4 times lower than in a similar transistor without the formation of near-wall regions from silicon oxide (curve a of Fig. 10).

By means of numerical simulation, the electrophysical parameters of the structure of n-channel transistors with near-wall regions of silicon oxide of different thicknesses, with a concentration of heavily phosphorus-doped source and drain regions of 10 ²⁰ cm ^-3 , and a boron concentration in the pocket region of 10 ¹⁸ cm ^-3 , were obtained. When the impurity was activated by annealing at a temperature of 1050°C for 15 seconds in a nitrogen atmosphere, the heavily doped source and drain regions expanded by phosphorus diffusion (K. Pierce, A. Adams et al., VLSI Technology: In 2 kN, Kn. 1. Translated from English / Under the editorship of S.Zi - M.: Mir, 1986. - 404 pp., ill.) and went under the gate of the transistor by 0.05 μm each parallel to the silicon surface - gate dielectric.

Table 1 shows the characteristics of transistors with different widths of silicon oxide near-wall regions.

A transistor with a silicon oxide wall region width of 0 µm is a transistor without a silicon oxide wall region.

At a wall silicon oxide width of 0.05 μm, equal to the width of a part of the heavily doped source or drain region that has entered under the gate region due to the diffusion of phosphorus impurities during temperature exposure (activation), the minimum value of the electric field strength in the gate dielectric and the maximum value of the steepness of the input characteristic ( Fig. 9).

Thus, the use of the proposed method for manufacturing transistors makes it possible to increase the breakdown voltage of the gate silicon oxide, to reduce the leakage current through this dielectric, thereby increasing the reliability of ICs manufactured on such transistors.

Claims (1)

A method for manufacturing a MOS transistor based on a silicon-on-insulator structure, including the formation of drain, source, gate, and gate dielectric regions, characterized in that a transistor pocket is created on the silicon-on-insulator wafer by doping a silicon layer, then a nitride layer is deposited on the wafer silicon and by means of reactive mask etching, a silicon nitride region is formed corresponding to the design norm of the transistor, then, by means of ion implantation, lightly doped source and drain regions are formed, then silicon oxide regions are formed on lightly doped regions of the drain, source, then the silicon nitride layer is removed by liquid etching, the silicon oxide layer is deposited by low-temperature vapor deposition, silicon oxide near-wall regions are formed by reactive ion etching of silicon oxide, the width of which is determined by the etching time of approx. silicon oxide, then after chemical cleaning of the surface, gate silicon oxide is formed on the layer of doped silicon by high-temperature oxidation, then the transistor gate is formed by deposition of polycrystalline silicon and etching it on a mask, then maskless etching of silicon oxide is carried out, the formation of heavily doped source and drain regions by means of ionic implantation and high-temperature annealing, so that the diffusion of impurities in the source and drain regions goes under the gate region at a distance equal to the width of the near-wall regions of silicon oxide.

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