JP2000196074A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JP2000196074A JP2000196074A JP10371307A JP37130798A JP2000196074A JP 2000196074 A JP2000196074 A JP 2000196074A JP 10371307 A JP10371307 A JP 10371307A JP 37130798 A JP37130798 A JP 37130798A JP 2000196074 A JP2000196074 A JP 2000196074A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- semiconductor device
- film
- trench
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 150000004767 nitrides Chemical class 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000002955 isolation Methods 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 9
- 239000010410 layer Substances 0.000 description 16
- 229910052814 silicon oxide Inorganic materials 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 239000002585 base Substances 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 239000005360 phosphosilicate glass Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000006837 decompression Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- -1 etc. Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、素子分離用溝部を
有する半導体装置およびその製造方法に係わり、特に、
低電圧駆動縦型ＭＯＳ−ＦＥＴにおいて三層のゲート絶
縁膜を有するトレンチゲート型半導体装置およびその製
造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a trench for element isolation and a method of manufacturing the same.
The present invention relates to a trench gate type semiconductor device having a three-layer gate insulating film in a low voltage driven vertical MOS-FET and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】トランジスタなどの半導体装置を、微細
加工技術により高密度に集積させた高集積回路におい
て、さらなる高集積化および高い駆動能力が求められて
いる。2. Description of the Related Art In a highly integrated circuit in which semiconductor devices such as transistors are integrated at a high density by a fine processing technique, higher integration and higher driving capability are required.
【０００３】近年、中でも注目されているのがトレンチ
（溝）を有する半導体装置である。ゲートをトレンチ構
造にすると、基板上のゲート部分の占有面積を狭くする
ことができ、その結果電流値の大きな、性能の良い高集
積化回路が実現される。In recent years, a semiconductor device having a trench (groove) has attracted particular attention. When the gate has a trench structure, the area occupied by the gate on the substrate can be reduced, and as a result, a highly integrated circuit with a large current value and high performance can be realized.
【０００４】特に１００Ｖ以下の低耐圧デバイスにはオ
ン抵抗を改善するためにトレンチ構造のパワーＭＯＳＦ
ＥＴが用いられている。このような低電圧駆動型ＭＯＳ
−ＦＥＴのトレンチゲート絶縁膜の構造は、シリコン酸
化膜、シリコン窒化膜−シリコン酸化膜、シリコン酸化
膜−シリコン窒化膜−シリコン酸化膜、シリコン酸化膜
−ポリシリコン酸化膜等である。In particular, for a low breakdown voltage device of 100 V or less, a power MOSF having a trench structure is used to improve the on-resistance.
ET is used. Such a low voltage drive type MOS
-The structure of the trench gate insulating film of the FET is a silicon oxide film, a silicon nitride film-a silicon oxide film, a silicon oxide film-a silicon nitride film-a silicon oxide film, a silicon oxide film-a polysilicon oxide film, and the like.
【０００５】こうしたトレンチゲートにおけるゲートの
信頼性を表わすパラメータとして、ＢＴ（Bias Tempera
ture）ストレスおよびＴＤＤＢ寿命がある。As a parameter representing the reliability of such a trench gate, BT (Bias Tempera
ture) There is stress and TDDB life.
【０００６】ＢＴストレスとは、正に帯電したアルカリ
イオンを定量化するために、２００℃から３００℃で加
熱し、１０6 Ｖ／ｃｍ程度の電界を印加することであ
る。これによるＣＶ（容量−電圧）特性の平行移動、す
なわち、ΔＶFBからその定量ができる。ＭＯＳトランジ
スタでは分極性ヒステリシスを起こす。図１０に１５０
℃で１６８時間電界を印加したときのヒステリシスの一
例を示す。[0006] BT stress refers to heating at 200 ° C to 300 ° C and applying an electric field of about 10 6 V / cm to quantify positively charged alkali ions. As a result, the CV (capacitance-voltage) characteristic can be determined from the parallel shift, that is, ΔV FB . A MOS transistor causes polarization hysteresis. 150 in FIG.
4 shows an example of hysteresis when an electric field is applied at 168 ° C. for 168 hours.
【０００７】また、ＴＤＤＢ寿命とは、トランジスタの
製品寿命であり、詳しくは１０Ｖで一年経た時の不良率
である。図９にＴＤＤＢの一例を示す。[0007] The TDDB life is the product life of the transistor, and more specifically, the failure rate when one year has passed at 10 V. FIG. 9 shows an example of the TDDB.
【０００８】ゲート絶縁膜が、シリコン酸化膜−シリコ
ン窒化膜−シリコン酸化膜の三層構造からなる場合、長
いＴＤＤＢ寿命を得るためには窒化膜を厚くすればよい
が、−ＢＴ時の変動が大きくなる。これは窒化膜自体に
蓄積されている電荷に起因している。また、逆に窒化膜
が薄いと、窒化膜のピンホール等に起因してゲート電極
からプラスの可動イオンが窒化膜を突き抜けて、これが
ゲート絶縁膜中にトラップされることでＢＴ変動が生じ
てしまう。When the gate insulating film has a three-layer structure of a silicon oxide film-silicon nitride film-silicon oxide film, the nitride film may be made thick to obtain a long TDDB life. growing. This is due to the charge stored in the nitride film itself. Conversely, if the nitride film is thin, positive movable ions penetrate through the nitride film from the gate electrode due to a pinhole or the like in the nitride film and are trapped in the gate insulating film, thereby causing BT fluctuation. I will.
【０００９】[0009]
【発明が解決しようとする課題】以上のように、ＢＴ変
動のない、ＴＤＤＢ寿命の長いゲート絶縁膜を有するト
レンチ構造の半導体装置およびその製造方法が必要とさ
れていた。As described above, there is a need for a semiconductor device having a trench structure having a gate insulating film having a long TDDB life and having no BT fluctuation, and a method of manufacturing the same.
【００１０】従って、本発明は、ＢＴ変動のない、ＴＤ
ＤＢ寿命の長いゲート絶縁膜を有する信頼性の高いトレ
ンチ構造の半導体装置およびその製造方法を提供するこ
とを目的とする。[0010] Therefore, the present invention provides a TD having no BT fluctuation.
It is an object of the present invention to provide a highly reliable trench-structured semiconductor device having a gate insulating film with a long DB life and a method of manufacturing the same.
【００１１】[0011]
【課題を解決するための手段】本発明の半導体装置は、
素子分離用溝部を備えた半導体基板と、前記溝部上に形
成された、前記溝部側から第１の酸化膜、窒化膜および
第２の酸化膜の順に三層構造を有するゲート絶縁膜と、
前記溝部に埋め込まれたゲート電極とを少なくとも具備
し、前記三層構造のゲート絶縁膜の酸化膜換算の厚さが
２５から３５ｎｍであることを特徴としている。According to the present invention, there is provided a semiconductor device comprising:
A semiconductor substrate having an element isolation groove, a gate insulating film formed on the groove, and having a three-layer structure in the order of a first oxide film, a nitride film, and a second oxide film from the groove side;
A gate electrode buried in the trench, wherein a thickness of the three-layered gate insulating film in terms of an oxide film is 25 to 35 nm.
【００１２】本発明の半導体装置は、低電圧駆動型ＭＯ
Ｓ−ＦＥＴとして有用である。The semiconductor device according to the present invention is a low voltage drive type MO.
Useful as an S-FET.
【００１３】本発明の半導体装置の製造方法は、半導体
基板上に素子分離用溝部を形成する工程と、前記溝部上
に、第１の酸化膜、窒化膜および第２の酸化膜からなる
三層構造のゲート絶縁膜を酸化膜換算の厚さが２５から
３５ｎｍとなるように形成する工程と、前記ゲート絶縁
膜の形成された前記溝部にゲート電極を埋め込む工程と
を少なくとも具備することを特徴としている。According to the method of manufacturing a semiconductor device of the present invention, there is provided a step of forming a groove for element isolation on a semiconductor substrate, and forming a three-layer structure comprising a first oxide film, a nitride film and a second oxide film on the groove. Forming at least a step of forming a gate insulating film having a structure with an oxide film equivalent thickness of 25 to 35 nm, and embedding a gate electrode in the trench in which the gate insulating film is formed. I have.
【００１４】より具体的には、本発明の半導体装置の製
造方法は、半導体基板上にエピタキシャル層およびベー
ス層を堆積する工程と、コンタクト領域となる不純物拡
散領域そしてソース領域を形成する工程と、素子分離用
溝部であるトレンチをＲＩＥ（Reactive Ion Etching）
によりエッチングする工程と、トレンチに第１の酸化
膜、窒化膜および第２の酸化膜からなる三層構造のゲー
ト絶縁膜を、それぞれ所定の温度にて、熱酸化、減圧Ｃ
ＶＤ（Chemical Vapor Deposition ）法、熱酸化により
形成する工程と、ゲート絶縁膜の形成されたトレンチに
ゲート電極を埋め込み、平坦化し、ＣＤＥ（Chemical D
ry Etching）によりエッチバックする工程と、少なくと
もゲート電極を覆うように層間絶縁膜を形成する工程
と、層間絶縁膜の上にバリアメタル層を堆積する工程
と、バリアメタル層の上にソース電極を形成する工程と
を具備している。More specifically, a method of manufacturing a semiconductor device according to the present invention includes a step of depositing an epitaxial layer and a base layer on a semiconductor substrate, a step of forming an impurity diffusion region and a source region serving as a contact region, RIE (Reactive Ion Etching) for trench, which is a trench for element isolation
A gate insulating film having a three-layer structure consisting of a first oxide film, a nitride film and a second oxide film in a trench at predetermined temperatures by thermal oxidation and decompression, respectively.
A step of forming by VD (Chemical Vapor Deposition) method and thermal oxidation, and embedding a gate electrode in a trench in which a gate insulating film is formed, flattening, and forming a CDE (Chemical D
ry Etching), forming an interlayer insulating film to cover at least the gate electrode, depositing a barrier metal layer on the interlayer insulating film, and forming a source electrode on the barrier metal layer. Forming step.
【００１５】本発明の半導体装置およびその製造方法に
おいて、前記第１の酸化膜の厚さは１５から２５ｎｍ、
窒化膜の厚さは８から１６ｎｍ、前記第２の酸化膜の厚
さは６から１０ｎｍである。In the semiconductor device and the method of manufacturing the same according to the present invention, the first oxide film has a thickness of 15 to 25 nm,
The thickness of the nitride film is 8 to 16 nm, and the thickness of the second oxide film is 6 to 10 nm.
【００１６】本発明の半導体装置およびその製造方法に
おいて、前記第１の酸化膜の形成温度は９００から９５
０℃、前記窒化膜の形成温度は７００から８００℃であ
る。In the semiconductor device and the method of manufacturing the same according to the present invention, the temperature for forming the first oxide film is 900 to 95.
0 ° C., and the temperature for forming the nitride film is 700 to 800 ° C.
【００１７】本発明において、ゲート絶縁膜は、基板側
から第１の酸化膜、窒化膜、第２の窒化膜からなる三層
構造とした。三層構造にすると、トレンチ開口部の角部
における応力を緩和したり、欠陥をカバーしたり、機能
を分担させるのに効果的である。ゲート絶縁膜は厚くす
れば破壊耐圧を増大させることができるが、単純に厚く
すればよい、というわけではない。というのは、第１の
酸化膜と窒化膜の厚みにより半導体素子の動作特性が決
まるためである。In the present invention, the gate insulating film has a three-layer structure including a first oxide film, a nitride film, and a second nitride film from the substrate side. The three-layer structure is effective in relieving stress at the corner of the trench opening, covering defects, and sharing functions. Although the breakdown voltage can be increased by increasing the thickness of the gate insulating film, it is not always sufficient to simply increase the thickness. This is because the operating characteristics of the semiconductor element are determined by the thicknesses of the first oxide film and the nitride film.
【００１８】ゲート絶縁膜が三層構造からなる場合、上
述したように、長いＴＤＤＢ寿命を得るためには窒化膜
を厚くすればよいが、窒化膜を２０ｎｍ程度まで厚くす
ると、窒化膜自体に蓄積されている電荷が原因で−ＢＴ
時の変動が大きくなる。また、逆に窒化膜を、８ｎｍ未
満の薄さにすると、窒化膜のピンホール等に起因してゲ
ート電極からプラスの可動イオンが窒化膜を突き抜け
て、これがゲート絶縁膜中にトラップされてＢＴ変動が
生じる。When the gate insulating film has a three-layer structure, as described above, a long TDDB life can be obtained by increasing the thickness of the nitride film. -BT due to the charge
Fluctuation of time becomes large. Conversely, if the nitride film is made thinner than 8 nm, positive mobile ions penetrate the gate electrode from the gate electrode due to pinholes in the nitride film and the like, and are trapped in the gate insulating film, thereby causing BT. Fluctuations occur.
【００１９】窒化膜の厚さとＴＤＤＢ寿命の関係につい
て図６に示す。製品寿命としては少なくとも１０6 時間
は必要とされる。この製品寿命を得るには窒化膜の厚さ
は８ｎｍ必要である。また、窒化膜とＢＴ変動の関係に
ついて図７および８に示す。＋ＢＴ時のΔＶFBは窒化膜
厚が０ｎｍ、８０ｎｍおよび２０ｎｍのいずれの場合も
十分低いが、−ＢＴ時のΔＶFBは窒化膜厚が０ｎｍおよ
び２０ｎｍの場合に許容できないレベルとなってしま
う。FIG. 6 shows the relationship between the thickness of the nitride film and the TDDB life. A product life of at least 10 6 hours is required. To obtain this product life, the thickness of the nitride film is required to be 8 nm. 7 and 8 show the relationship between the nitride film and the BT fluctuation. While ΔV FB at + BT is sufficiently low in any of the nitride film thicknesses of 0 nm, 80 nm and 20 nm, ΔV FB at −BT becomes an unacceptable level when the nitride film thickness is 0 nm and 20 nm.
【００２０】従って、本発明においては、ＢＴ変動なら
びにＴＤＤＢ寿命を考慮して、窒化膜厚を８から１６ｎ
ｍを最適値として定めた。この値は、実際にＢＴ変動お
よびＴＤＤＢ寿命を測定してはじめて得られたものであ
る。Therefore, in the present invention, the nitride film thickness is set to 8 to 16 n in consideration of BT fluctuation and TDDB life.
m was determined as the optimum value. This value is obtained only after actually measuring the BT fluctuation and the TDDB life.
【００２１】また、本発明において、最も基板側の第１
の酸化膜の厚さを１５から２５ｎｍとすることで絶縁性
に優れ、信頼性が向上する。Also, in the present invention, the first substrate side
By setting the thickness of the oxide film to 15 to 25 nm, insulation properties are excellent and reliability is improved.
【００２２】このように、本発明においては、所定の形
成温度を用いて所定の厚さの第１の酸化膜および窒化膜
を形成することで、ＢＴ変動のない、ＴＤＤＢ寿命の長
いゲート絶縁膜が実現される。As described above, in the present invention, by forming the first oxide film and the nitride film having a predetermined thickness at a predetermined formation temperature, a gate insulating film having a long TDDB life without BT fluctuation is formed. Is realized.
【００２３】本発明の半導体装置において用いる材料は
特に限定されるものではないが、例えば、半導体基板と
しては、シリコン、ＧａＡｓ等、ゲート電極としては、
ポリシリコン、ＢＰＳＧ（Boron Phospharus Silicate
Glass ）、ＰＳＧ（PhosphoSilicate Glass）等、層間
絶縁膜としては、ＳｉＯ2 、ＰＳＧ、Ｓｉ3 Ｎ4 等、バ
リアメタルとしてはＴｉ、ＴｉＷ等、ソース電極および
ドレイン電極としては、Ａｌ、Ｃｕ、Ａｕ等である。Although the material used in the semiconductor device of the present invention is not particularly limited, for example, the semiconductor substrate is silicon, GaAs, etc., and the gate electrode is
Polysilicon, BPSG (Boron Phospharus Silicate)
Glass), PSG (PhosphoSilicate Glass), etc., interlayer insulating film such as SiO 2 , PSG, Si 3 N 4 , barrier metal such as Ti, TiW, etc., source and drain electrodes such as Al, Cu, Au etc. It is.
【００２４】また、本発明は、ＭＯＳ−ＦＥＴばかりで
なく、半導体基板の裏面全面にｐ型層を形成したｎ型半
導体基板を用いればＩＧＢＴ（絶縁ゲート型バイポーラ
トランジスタ）にも適用することができる。The present invention can be applied not only to a MOS-FET but also to an IGBT (insulated gate bipolar transistor) if an n-type semiconductor substrate having a p-type layer formed on the entire back surface of the semiconductor substrate is used. .
【００２５】[0025]
【発明の実施の形態】本発明の半導体装置について図１
〜５を用いて説明する。FIG. 1 shows a semiconductor device according to the present invention.
This will be described with reference to FIGS.
【００２６】図１は本発明の半導体装置の断面図であ
る。FIG. 1 is a sectional view of a semiconductor device according to the present invention.
【００２７】Ｎ型シリコン基板１の一主面側に堆積され
たＰ型ベース層３に、トレンチが形成されており、トレ
ンチには厚さ２０ｎｍの第１の酸化膜、その上に厚さ１
２ｎｍの窒化膜、そしてその上に厚さ８ｎｍの第２の酸
化膜からなるゲート絶縁膜７が形成されている。このゲ
ート絶縁膜の酸化膜換算の総厚さは３０ｎｍである。ト
レンチにはゲート電極８が埋め込まれている。トレンチ
−トレンチ間領域には、Ｐ＋不純物拡散領域４とＮ＋ソ
ース領域５が形成されている。さらに、ゲート電極８を
覆うようにＳｉ3 Ｎ4 ＣＶＤ膜９が堆積され、Ｔｉから
なるバリアメタルを介してソース電極であるアルミニウ
ム１２が堆積している。また、シリコン基板１の他主面
側にはドレイン電極となるメタル１３が堆積されてい
る。A trench is formed in the P-type base layer 3 deposited on one main surface side of the N-type silicon substrate 1, and a first oxide film having a thickness of 20 nm is formed on the trench.
A gate insulating film 7 made of a 2 nm nitride film and an 8 nm thick second oxide film is formed thereon. The total thickness of this gate insulating film in terms of an oxide film is 30 nm. The gate electrode 8 is buried in the trench. In the region between the trenches, a P + impurity diffusion region 4 and an N + source region 5 are formed. Further, a Si 3 N 4 CVD film 9 is deposited so as to cover the gate electrode 8, and aluminum 12 as a source electrode is deposited via a barrier metal made of Ti. On the other main surface side of the silicon substrate 1, a metal 13 serving as a drain electrode is deposited.
【００２８】本発明の一実施例による半導体装置の製造
工程を図２〜５を用いて説明する。A manufacturing process of a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS.
【００２９】まず、図２（ａ）に示す通り、Ｎ型シリコ
ン基板１の一主面側にＰ型ベース層２を、例えばＣＶＤ
法により堆積させて、その上にマスクを介してホウ素等
のイオンを注入して所定の位置にＰ＋不純物拡散領域を
形成する。さらに、Ｐ＋不純物拡散領域の間に砒素、ア
ンチモン、りん等のイオンをで注入してＮ＋ソース領域
を形成する。さらに、熱シリコン酸化膜３を堆積する。First, as shown in FIG. 2A, a P-type base layer 2 is formed on one main surface of an N-type silicon substrate 1 by, for example, CVD.
Then, ions such as boron are implanted through a mask through a mask to form P + impurity diffusion regions at predetermined positions. Further, ions of arsenic, antimony, phosphorus and the like are implanted between the P + impurity diffusion regions to form an N + source region. Further, a thermal silicon oxide film 3 is deposited.
【００３０】次に、熱シリコン酸化膜３の上にさらに、
ＣＶＤ法によりＣＶＣ酸化膜４を堆積する（図２
（ｂ））。Next, on the thermal silicon oxide film 3,
A CVC oxide film 4 is deposited by a CVD method (FIG. 2)
(B)).
【００３１】トレンチエッチングする部位以外にレジス
ト５を塗布し（図２（ｃ））、エッチングする（図２
（ｄ））。A resist 5 is applied to a portion other than the portion to be etched by the trench (FIG. 2C) and etched (FIG. 2C).
(D)).
【００３２】レジスト５を除去したら（図３（ｅ））、
Ｎ＋ソース領域５を貫くようにしてトレンチ６を反応性
イオンエッチング（ＲＩＥ）により形成する。トレンチ
６の幅は約１μｍ、深さは約３μｍとする（図３
（ｆ））。トレンチ６にＣＤＥ（Chemical Dry Etchin
g）によりダメージ処理を施す（図３（ｇ））。熱シリ
コン酸化膜３およびＣＶＤ酸化膜４を除去する（図３
（ｈ））。After removing the resist 5 (FIG. 3E),
A trench 6 is formed through the N + source region 5 by reactive ion etching (RIE). The width of the trench 6 is about 1 μm and the depth is about 3 μm (FIG.
(F)). CDE (Chemical Dry Etchin) in trench 6
g) to perform a damage process (FIG. 3 (g)). The thermal silicon oxide film 3 and the CVD oxide film 4 are removed (FIG. 3
(H)).
【００３３】さらに、図４（ｉ）に示すように、トレン
チ６に厚さ２０ｎｍの第１の酸化膜、その上に厚さ１２
ｎｍの窒化膜、そしてその上に厚さ８ｎｍの第２の酸化
膜からなるゲート絶縁膜７を堆積する。第１の酸化膜の
形成条件は、酸素と水素の混合雰囲気内で９３０℃、窒
化膜の形成条件は、減圧ＣＶＤで７５０℃、第２の酸化
膜の形成条件は、酸素と水素の混合雰囲気内とする。Further, as shown in FIG. 4I, a first oxide film having a thickness of 20 nm is formed in the trench 6, and a first oxide film having a thickness of 12
A gate insulating film 7 made of a nitride film having a thickness of 10 nm and a second oxide film having a thickness of 8 nm is deposited thereon. The conditions for forming the first oxide film are 930 ° C. in a mixed atmosphere of oxygen and hydrogen, the conditions for forming the nitride film are 750 ° C. by low pressure CVD, and the conditions for forming the second oxide film are a mixed atmosphere of oxygen and hydrogen. Inside.
【００３４】ゲート絶縁膜７の形成されたトレンチ６に
ゲート電極８を埋め込む（図４（ｊ））。このゲート電
極８に平坦化処理を施し、エッチバックする（図４
（ｋ））。層間絶縁膜としてＳｉ3 Ｎ4 からなるＣＶＤ
膜９を全面に堆積する（図４（ｌ））。The gate electrode 8 is buried in the trench 6 where the gate insulating film 7 is formed (FIG. 4 (j)). The gate electrode 8 is subjected to a flattening process and etched back (FIG.
(K)). CVD made of Si 3 N 4 as interlayer insulating film
A film 9 is deposited on the entire surface (FIG. 4 (l)).
【００３５】Ｓｉ3 Ｎ4 からなるＣＶＤ膜９をエッチン
グするために、レジスト１０を塗布して（図５
（ｍ））、ＲＩＥにより加工した後（図５（ｎ））、Ｔ
ｉからなるバリアメタル１１を介してソース電極である
アルミニウム１２を全面に堆積させて（図５（ｏ））、
ドレイン電極をシリコン基板１の他主面側に堆積させて
（図示せず）半導体装置とする。In order to etch the CVD film 9 made of Si 3 N 4 , a resist 10 is applied (FIG. 5).
(M)), after processing by RIE (FIG. 5 (n)),
Aluminum 12 as a source electrode is deposited on the entire surface via a barrier metal 11 made of i (FIG. 5 (o)).
A semiconductor device is formed by depositing a drain electrode on the other main surface side of the silicon substrate 1 (not shown).
【００３６】以上、Ｎチャネル型について説明してきた
が、言うまでもなく、Ｐチャネル型についても同様に作
成できる。The N-channel type has been described above. Needless to say, the P-channel type can be similarly created.
【００３７】[0037]
【発明の効果】本発明によれば、ＢＴ変動のない、ＴＤ
ＤＢ寿命の長いゲート絶縁膜を有するトレンチ構造の半
導体装置およびその製造方法が提供される。According to the present invention, TD fluctuation free TD
Provided are a semiconductor device having a trench structure having a gate insulating film having a long DB life and a method for manufacturing the same.
【図１】本発明の半導体装置の拡大断面図。FIG. 1 is an enlarged cross-sectional view of a semiconductor device of the present invention.
【図２】本発明の半導体装置の製造工程を示す図。FIG. 2 is a diagram showing a manufacturing process of the semiconductor device of the present invention.
【図３】本発明の半導体装置の製造工程を示す図。FIG. 3 is a view showing a manufacturing process of the semiconductor device of the present invention.
【図４】本発明の半導体装置の製造工程を示す図。FIG. 4 is a view showing a manufacturing process of the semiconductor device of the present invention.
【図５】本発明の半導体装置の製造工程を示す図。FIG. 5 is a view showing a manufacturing process of the semiconductor device of the present invention.
【図６】ライフタイムと窒化膜厚の関係を示すグラフ。FIG. 6 is a graph showing a relationship between a lifetime and a nitride film thickness.
【図７】＋ＢＴ時の電圧特性と窒化膜厚の関係を示すグ
ラフ。FIG. 7 is a graph showing a relationship between a voltage characteristic at + BT and a nitride film thickness.
【図８】−ＢＴ時の電圧特性と窒化膜厚の関係を示すグ
ラフ。FIG. 8 is a graph showing a relationship between a voltage characteristic at the time of −BT and a nitride film thickness.
【図９】ＴＤＤＢ寿命を示すグラフ。FIG. 9 is a graph showing TDDB life.
【図１０】ＢＴ変動を示すグラフ。FIG. 10 is a graph showing BT fluctuation.
１…基板 ２…ベース層 ３…熱シリコン酸化膜 ４…ＣＶＤ酸化膜 ５…レジスト ６…トレンチ ７…ゲート絶縁膜（第１の酸化膜、窒化膜、第２の酸化
膜） ８…ゲート電極 ９…ＣＶＤ膜 １０…レジスト １１…バリアメタル １２…アルミニウムDESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Base layer 3 ... Thermal silicon oxide film 4 ... CVD oxide film 5 ... Resist 6 ... Trench 7 ... Gate insulating film (1st oxide film, nitride film, 2nd oxide film) 8 ... Gate electrode 9 ... CVD film 10 ... resist 11 ... barrier metal 12 ... aluminum
Claims (7)
前記溝部上に形成された、前記溝部側から第１の酸化
膜、窒化膜および第２の酸化膜の順に三層構造を有する
ゲート絶縁膜と、前記溝部に埋め込まれたゲート電極と
を少なくとも具備する半導体装置であって、 前記三層構造のゲート絶縁膜の酸化膜換算の厚さが２５
から３５ｎｍであることを特徴とする半導体装置。A semiconductor substrate having an element isolation groove;
At least a gate insulating film formed on the groove and having a three-layer structure in the order of a first oxide film, a nitride film, and a second oxide film from the groove side, and a gate electrode embedded in the groove A three-layered gate insulating film having a thickness equivalent to an oxide film of 25.
A semiconductor device having a thickness of from 35 to 35 nm.
ｎｍであり、前記窒化膜の厚さが８から１６ｎｍ、前記
第２の酸化膜の厚さが６から１０ｎｍであることを特徴
とする請求項１記載の半導体装置。2. The method according to claim 1, wherein said first oxide film has a thickness of 15 to 25.
2. The semiconductor device according to claim 1, wherein the thickness of the nitride film is 8 to 16 nm, and the thickness of the second oxide film is 6 to 10 nm.
ら９５０℃であり、前記窒化膜の形成温度が７００から
８００℃であることを特徴とする請求項１記載の半導体
装置。3. The semiconductor device according to claim 1, wherein a temperature at which said first oxide film is formed is 900 to 950 ° C., and a temperature at which said nitride film is formed is 700 to 800 ° C.
−ＦＥＴであることを特徴とする請求項１記載の半導体
装置。4. The semiconductor device according to claim 1, wherein said semiconductor device is a low voltage drive type MOS.
2. The semiconductor device according to claim 1, wherein the semiconductor device is an FET.
る工程と、前記溝部上に、第１の酸化膜、窒化膜および
第２の酸化膜からなる三層構造のゲート絶縁膜を酸化膜
換算の厚さが２５から３５ｎｍとなるように形成する工
程と、前記ゲート絶縁膜の形成された前記溝部にゲート
電極を埋め込む工程とを少なくとも具備することを特徴
とする半導体装置の製造方法。5. A step of forming a trench for element isolation on a semiconductor substrate, and forming an oxide film on the trench with a three-layered structure including a first oxide film, a nitride film and a second oxide film. A method for manufacturing a semiconductor device, comprising: at least a step of forming a converted thickness to be 25 to 35 nm, and a step of burying a gate electrode in the trench in which the gate insulating film is formed.
ｎｍであり、前記窒化膜の厚さが８から１６ｎｍ、前記
第２の酸化膜の厚さが６から１０ｎｍであることを特徴
とする請求項５記載の半導体装置の製造方法。6. The thickness of the first oxide film is 15 to 25.
6. The method according to claim 5, wherein the thickness of the nitride film is 8 to 16 nm, and the thickness of the second oxide film is 6 to 10 nm.
ら９５０℃であり、前記窒化膜の形成温度が７００から
８００℃であることを特徴とする請求項５記載の半導体
装置の製造方法。7. The method according to claim 5, wherein a temperature of forming the first oxide film is 900 to 950 ° C., and a temperature of forming the nitride film is 700 to 800 ° C. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10371307A JP2000196074A (en) | 1998-12-25 | 1998-12-25 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10371307A JP2000196074A (en) | 1998-12-25 | 1998-12-25 | Semiconductor device and its manufacture |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000196074A true JP2000196074A (en) | 2000-07-14 |
| JP2000196074A5 JP2000196074A5 (en) | 2004-11-11 |
Family
ID=18498487
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10371307A Abandoned JP2000196074A (en) | 1998-12-25 | 1998-12-25 | Semiconductor device and its manufacture |
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| Country | Link |
|---|---|
| JP (1) | JP2000196074A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6974996B2 (en) | 2003-01-23 | 2005-12-13 | Denso Corporation | Semiconductor device and method of manufacturing the same |
| US7622768B2 (en) | 2004-04-21 | 2009-11-24 | Denso Corporation | Semiconductor device and method of manufacturing thereof |
| CN101840931B (en) * | 2009-03-18 | 2014-03-12 | 联发科技股份有限公司 | High-voltage metal-dielectric-semiconductor device |
| CN107978641A (en) * | 2017-11-23 | 2018-05-01 | 中航（重庆）微电子有限公司 | A kind of power MOS (Metal Oxide Semiconductor) device manufacture method of new gate structure |
| CN108962993A (en) * | 2017-05-24 | 2018-12-07 | 株式会社东芝 | Semiconductor device and its manufacturing method |
| CN110047919A (en) * | 2014-05-12 | 2019-07-23 | 英飞凌科技股份有限公司 | Semiconductor devices and it is formed in semiconductor mesa source region insulated gate bipolar transistor |
-
1998
- 1998-12-25 JP JP10371307A patent/JP2000196074A/en not_active Abandoned
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6974996B2 (en) | 2003-01-23 | 2005-12-13 | Denso Corporation | Semiconductor device and method of manufacturing the same |
| US7622768B2 (en) | 2004-04-21 | 2009-11-24 | Denso Corporation | Semiconductor device and method of manufacturing thereof |
| CN101840931B (en) * | 2009-03-18 | 2014-03-12 | 联发科技股份有限公司 | High-voltage metal-dielectric-semiconductor device |
| CN110047919A (en) * | 2014-05-12 | 2019-07-23 | 英飞凌科技股份有限公司 | Semiconductor devices and it is formed in semiconductor mesa source region insulated gate bipolar transistor |
| CN108962993A (en) * | 2017-05-24 | 2018-12-07 | 株式会社东芝 | Semiconductor device and its manufacturing method |
| JP2018198267A (en) * | 2017-05-24 | 2018-12-13 | 株式会社東芝 | Semiconductor device and manufacturing method for the same |
| CN108962993B (en) * | 2017-05-24 | 2021-09-24 | 株式会社东芝 | Semiconductor device and method for manufacturing the same |
| CN107978641A (en) * | 2017-11-23 | 2018-05-01 | 中航（重庆）微电子有限公司 | A kind of power MOS (Metal Oxide Semiconductor) device manufacture method of new gate structure |
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