RU2762529C1 - Variable frequency divider - Google Patents

Abstract

FIELD: automation and computer technology.

SUBSTANCE: invention relates to automation and computer technology, as well as to automatic control systems and can be used in numerical control systems, in measuring and computing devices, devices for processing audio and video signals, as well as in the primary processing of signals from phased antenna arrays of radars. The device contains an OR element with n inputs, a shift register for 2 ⁿ – 1 bits, synchronization inputs, setting to the initial state, division permissions, which are the corresponding register inputs, n logical three-input AND elements, n–1 OR elements for two, four, ..., 2 ^{n –1} inputs, OR-NOT element for 2 ⁿ –1 inputs.

EFFECT: increasing the performance of the device with its circuitry simplification.

1 cl, 2 dwg

Description

The invention relates to automation and computer technology, as well as to automatic control systems and can be used in numerical control systems, in measuring and computing devices, devices for processing audio and video signals, as well as in the development of elements of impulse neural networks, in particular prototypes of impulse neurons.

The known device [RU Patent No. 2015539, publ. 06/30/94] for frequency division with a variable division ratio, containing an n-bit binary counter, synchronization inputs, count enable, initialization and division enable, which are the corresponding counter inputs, the overflow output, which is the corresponding counter output, n-bit bus control, the information output of the frequency divider, n logical elements with the AND function, the first inputs of which are connected respectively to the direct bit outputs of the n-bit counter, and the second inputs of these elements are connected to the n-bits of the control bus in reverse order, and the frequency divider also contains a two-input the AND-NOT element, and the logical elements with the AND function at two inputs also implement the 2OR function, at the outputs - the NOT function, thus making up the 2OR-AND-NOT function, in addition, the first input of the AND-NOT element is connected to the output of the first logical element , making up the function 2 OR-AND-NOT, and the second input - with the inverse output of synchronization of the binary count tchik, while the output of the AND-NOT element is the information output of the frequency divider, the expansion output of which is connected to the output of the first logical element 2OR-AND-NOT, the third inputs of all logical elements 2OR-AND-NOT are connected, respectively, to the inverse bit outputs of the n-bit binary counter, the fourth input of the i-th element 2 OR-AND-NOT (i = 1, n – 1) is connected to the output of the (i + 1) -th element 2 OR-AND-NOT, the fourth input of the n-th element 2 OR-AND-NOT is the input of the expansion of the frequency divider, and the first and second inputs of all logical elements 2OR-AND-NOT refer to the first OR element, and the third and fourth inputs to the second OR element.

The device performs division due to the sequential transformation of potential (with respect to the signal at the synchronization input) control signals from the control bus and from the counter bits on the 2OR-AND-NOT elements connected in series, with the separation of the output information signal from the potential (with respect to the signal on synchronization input) of the signal at the extension output of the divider. The signal at the extension output is obtained by sequential conversion using the 2OR-AND-NOT elements of the signals from the direct and inverse outputs of the counter discharge, the signal from the control bus and the signal from the output of the subsequent 2OR-AND-NOT element. Elements 2OR-AND-NOT form an iterative (sequential) chain, in which at each element at the first stage in the first pair, the signal from the output of each subsequent element is converted with the signal from the inverse output of the counter, in the second pair, the signal from the control bus is converted with the signal from the direct counter output, and the odd 2OR-AND-NOT element receives an inverse control signal from the control bus, and the even one receives a direct signal from the control bus, then at the second stage the signals of both pairs are converted into an output signal of the 2OR-AND-NOT element.

The average frequency F _{y of the} pulse flow at the output of the AND-NOT element, that is, at the output of the device, is determined by the expression

where N is the code coming over the n-bit control bus,

F ₀ - frequency supplied to the synchronization input.

The disadvantage of this device is the long conversion time associated with serial signal processing.

Of the analogs, the closest in technical essence is a frequency divider with a variable division ratio [RU Patent No. 2273043, publ. 03/27/2006], which was chosen as a prototype. In the prototype, the operating speed of the device is increased while simplifying the switching of the information signal generator.

A frequency divider with a variable division ratio, containing an OR element with n inputs, a sequential trigger structure, synchronization inputs, counting enable, setting to the initial state, division enable, which are the corresponding inputs of a sequential trigger structure, n logical three-input AND elements, the first inputs of which are connected to the corresponding bits of the control bus, and the outputs of the AND elements are connected to the corresponding inputs of the OR element, the output of which is the information output of the frequency divider.

In addition, the device contains a second sequential trigger structure, which, like the first, is made in the form of an n-bit binary counter with combined inputs for enabling counting, setting to an initial state and enabling division, which are the corresponding inputs in the counters, the overflow output of the device, which is the corresponding the output of the first counter, and the synchronization input of the second counter is connected to the inverse output of the clock frequency of the first counter, in which the direct bit outputs are connected, respectively, to the second inputs of the AND elements, the third inputs of these AND elements are connected to the corresponding inverse bit outputs of the second counter, and the third inputs of these elements And they are connected to the control bus bits in reverse order.

The prototype works as follows.

устанавливаются в ноль, а выходы

- в единицу.A pulse stream (clock sequence) with a frequency F ₀ arrives at the counter synchronization input. Enabling signals are sent to the inputs for counting and division. The reset signal is used to reset the counters: outputs

are set to zero, and the outputs

- per unit.

_{When the clock frequency F 0} pulses appear at the synchronization input, the counters begin to work simultaneously, and their state differs by half a cycle. During these half cycles, the discharge is allocated, in which the state changes from zero to one, and a single pulse is formed. This pulse is passed to the output by the enable signal, which, in the presence of a unit on the corresponding bit of the bus, controls the passage of pulses to the output. The control of the passage of pulses to the output is carried out by the signals of the control bus in the reverse order.

The logical expression for the output F _y is:

,

,

, a i – номер разряда шины управления (от 1 до n).where the function L in the general case

, ai - bit number of the control bus (from 1 to n).

достигается при одновременном равенстве единице

, и

. Такая ситуация возникает для каждого единичного состояния

в течение времени длительности импульса тактовой частоты τ только при начале этого единичного состояния. Это связано с тем, что переход состояния

из единицы в ноль сдвинут на время (относительно перехода

из нуля в единицу), и обеспечено тактированием второго счетчика инверсным выходом синхронизации первого счетчика, то есть сигналом

. На выходе любого логического элемента L_i будет формироваться импульсная последовательность с частотойObviously, for any i, the equality to one

is attained with the simultaneous equality to one

, and

... This situation occurs for each single state

during the time of the clock pulse duration τ only at the beginning of this single state. This is because the state transition

shifted from one to zero by time (relative to the transition

from zero to one), and is provided by clocking the second counter with the inverse synchronization output of the first counter, that is, the signal

... At the output of any logical element L _i , a pulse sequence with a frequency

,

,

- логическое состояние i-x разрядов кодов управления N.where

- logical state of ix bits of control codes N.

The pulses in these sequences are spaced in time, therefore, at the output of the OR gate, which is the output of the device as a whole, a total frequency is formed, the average value of which, like the analog, has the form

.

...

The disadvantage of the prototype is the long conversion time associated with the operation of two counters built on two-stage static controlled triggers.

The task to be solved by the claimed invention is to increase the speed of the device through the use of fast shift register operations with weighted formation of the output pulse stream

The technical result is a high speed of operation of the device with its circuitry simplification.

регистра, у четырёхвходового элемента ИЛИ₂ - выходы разрядов

регистра и так далее до

-входового элемента ИЛИ_n-1- выходы разрядов

соответственно регистра, причём выход

регистра подсоединён к второму входу первого элемента И₁, а на вторые входы остальных элементов И - второго И₂, третьего И₃ и так далее до n-го элемента И_n подключены выходы элементов ИЛИ соответственно первого ИЛИ₁, второго ИЛИ₂ и так далее до (n–1)-го элемента ИЛИ_n–1, при этом третьи входы элементов И объединены с входом синхронизации устройства.The problem is solved by the fact that in a frequency divider with a variable division ratio, containing an OR element with n inputs, a sequential trigger structure, synchronization inputs, setting to the initial state, division permissions, which are the corresponding inputs of a sequential trigger structure, n logical three-input AND elements, the first whose inputs are connected to the corresponding bits of the control bus, and the outputs of the AND elements are connected to the corresponding inputs of the OR element, the output of which is the information output of the frequency divider, n – 1 OR elements are introduced into two, four, ..., 2 ^{n – 1} inputs, the OR element is NOT for 2 ⁿ –1 inputs, but the sequential trigger structure is made in the form of a shift register for 2 ⁿ –1 bits, the information D-input of which is connected to the output of the OR-NOT element connected by inputs to the corresponding outputs of the register bits, which are also combined with inputs of OR elements in the following order: for a two-input OR element ₁ - in discharge outputs

register, for a four-input element OR ₂ - bit outputs

register and so on until

-input element OR _n-1 - bit outputs

respectively register, and the output

the register is connected to the second input of the first AND ₁ element, and to the second inputs of the remaining AND elements - the second AND ₂ , the third AND _3, and so on, up to the n-th element AND _n , the outputs of the OR elements, respectively, of the first OR ₁ , the second OR _2, and so on to the (n – 1) th element OR _{n – 1} , while the third inputs of the AND elements are combined with the synchronization input of the device.

The essence of the proposed invention consists in creating a frequency divider with a variable division ratio by organizing a cyclic shift mode of pulse passage with weighting of frequency sequences, from which, depending on the control code, an output pulse sequence is formed.

The essence of the invention is illustrated by drawings, where Fig. 1 shows a functional diagram of the proposed frequency divider, FIG. 2 - time diagrams of the processes occurring in the device for N = 3 (011) and for N = 7 (111).

A frequency divider with a variable division ratio, contains an OR element 1 with n inputs, a sequential trigger structure 2, synchronization inputs 3, setting to the initial state 4, division resolution 5, which are the corresponding inputs of a sequential trigger structure 2, n logical three-input elements I6, the first inputs which are connected to the corresponding bits of the control bus 7, and the outputs of the elements And 6 are connected to the corresponding inputs of the OR element 1, the output of which is the information output 8 of the frequency divider.

регистра 2, у четырёхвходового элемента ИЛИ 9₂ – выходы разрядов

регистра 2 и так далее до

-входового элемента ИЛИ 9_n-1 – выходы разрядов

регистра 2, причём выход

регистра 2 подсоединён к второму входу первого элемента И6₁, а на вторые входы остальных элементов И 6– второго И 6₂, третьего И 6₃ и так далее до n-го элемента И6_n подключены выходы элементов ИЛИ 9 соответственно первого ИЛИ 9_1, второго ИЛИ 9₂ и так далее до (n–1)-го элемента ИЛИ 9_n–1, при этом третьи входы элементов И 6 объединены с входом синхронизации 3 устройства.In addition, the device contains n – 1 elements OR 9 for two, four, ..., 2 ^{n – 1} inputs, an element OR NOT 10 for 2 ⁿ –1 inputs, and the sequential trigger structure is made in the form of a shift register 2 by 2 ⁿ - 1 bit, the information D-input of which is connected to the output of the OR-NOT element 10, connected at the inputs to the corresponding outputs of the register bits, which are also combined with the inputs of the OR elements 9 in the following order: for a two-input OR element 9 ₁ - bit outputs

register 2, for a four-input element OR 9 ₂ - bit outputs

register 2 and so on until

-input element OR 9 _n-1 - bit outputs

register 2, and the output

register 2 is connected to the second input of the first element I6 ₁ , and the outputs of the elements OR 9 are connected to the second inputs of the remaining elements I 6 - the second AND 6 ₂ , the third AND 6 _3, and so on up to the n-th element I6 _{n, respectively, of the first OR 9 1,} the second OR 9 ₂ and so on up to the (n – 1) th element OR 9 _{n – 1} , while the third inputs of the AND 6 elements are combined with the synchronization input 3 of the device.

The device works as follows.

A pulse (clock) sequence with a frequency of F _{0 is} supplied to the synchronization input C3 of the device. By applying a signal to input R4 of the device, register 2 is set to zero. An enable signal is applied to the ED5 input of the device. After the completion of signals at inputs 4 (axis 1, Fig. 2) and input 5 of the device, the appearance at input 3 of the first pulse of clock frequency F ₀ ensures the appearance of "1" at the outputs Q _{1 of} register 2 and P ₃ of OR 9 ₂ (axis 2 - 3, fig. 2). The pulse from the output P ₃ is fed to the input of the element I 6 ₃ . Depending on the value of the corresponding high-order bit T _n of the control bus code N 7, this pulse can appear at the output L ₃ and then through the OR element 1 at the output F _y 8 of the device.

For example:

when "1" in the senior third digit N = 111, pulses appear in the first clock cycle (axes 2 - 3, L ₃ , F _y , Fig. 2);

at "0" in the most significant third bit N = 011 in the first cycle, there are no pulses (axes 2 - 3, L ₃ , F _y , Fig. 2).

On the next clock cycle, a shift will occur and a single pulse will be generated at the outputs Q _{2 of} register 2 and P ₂ of the OR element 9 ₁ (axes 4 - 5, Fig. 2). Depending on the value of the corresponding bit T ₂ of the control bus code N 7, this pulse can appear at the output L ₂ and then through the OR element 1 at the output F _y 8 of the device.

For example:

when "1" in the second digit N = 111, pulses appear in the second clock cycle (axes 4 - 5, L ₂ , F _y , Fig. 2);

when "1" in the second digit N = 011 in the second clock cycle, pulses appear (axes 4–5, L ₂ , F _y , Fig. 2).

On the third clock cycle, another shift will occur and a single pulse will be generated at the outputs Q _{3 of} register 2 and P ₃ of OR 9 ₂ (axes 6–7, Fig. 2). Depending on the value of the corresponding bit T ₃ of the control bus code N 7, this pulse can appear at the output L ₃ and then through the OR element 1 at the output F _y 8 of the device.

For example:

when "1" in the third digit N = 111, pulses appear in the third cycle (axes 6–7, L ₃ , F _y , Fig. 2);

at "0" in the third digit N = 011 in the third cycle, no pulses appear (axes 6–7, L ₃ , F _y , Fig. 2).

On the fourth clock, a shift will occur again and a single pulse is formed at the output of Q _{4 of} register 2 and in the form of P ₁ is fed directly to the input of element I 6 ₁ (axes 8 - 9, L ₁ , F _y , Fig. 2). Depending on the value of the corresponding bit T ₁ of the control bus code N 7, this pulse can appear at the output L ₁ and then through the OR element 1 at the output F _y 8 of the device.

For example:

when "1" in the first least significant bit N = 111, pulses appear in the fourth clock cycle (axes 8-9, L ₁ , F _y , Fig. 2);

at "0" in the first least significant bit N = 011 in the fourth cycle, the pulses reappear (axes 8-9, L ₁ , F _y , Fig. 2).

On the fifth clock cycle, another shift will occur, and a single pulse will be generated at the outputs Q _{5 of} register 2 and P ₃ of the OR element 9 ₂ (axes 10 - 11, L ₃ , F _y , Fig. 2). Depending on the value of the corresponding bit T ₃ of the control bus code N 7, this pulse can appear at the output L ₃ and then through the OR element 1 at the output F _y 8 of the device.

For example:

when "1" in the third digit N = 111 in the fifth cycle, pulses appear (axes 10 - 11, L ₃ , F _y , Fig. 2);

at "0" in the third bit N = 011 in the fifth cycle, the pulses do not appear (axes 10 - 11, L ₃ , F _y , Fig. 2).

On the sixth clock, a shift will occur again and a single pulse will be generated at the outputs Q _{6 of} register 2 and P ₂ of OR 9 ₂ (axes 12-13, L ₂ , F _y , Fig. 2). Depending on the value of the corresponding bit T ₂ of the control bus code N 7, this pulse can appear at the output L ₂ and then through the OR element 1 at the output F _y 8 of the device.

For example:

when "1" in the second digit N = 111, pulses appear in the sixth cycle (axes 12–13, L ₂ , F _y , Fig. 2);

when "1" in the second discharge N = 011 in the sixth clock pulses reappear (12- axis 13, L _2, F _y, FIG. 2).

On the seventh clock, a shift will occur and a single pulse will be generated at the outputs Q _{7 of} register 2 and P ₃ of OR 9 ₂ (axes 14 –15, L ₃ , F _y , Fig. 2). Depending on the value of the corresponding bit T ₂ of the control bus code N 7, this pulse can appear at the output L ₂ and then through the OR element 1 at the output F _y 8 of the device.

For example:

when "1" in the third digit N = 111, pulses appear in the seventh cycle (axes 14–15, L ₃ , F _y , Fig. 2);

at "0" in the third digit N = 011 in the seventh cycle, no pulses appear (axes 14–15, L ₃ , F _y , Fig. 2).

. Далее с помощью элемента ИЛИ-НЕ 10 фиксируется завершение процесса сдвига по всем разрядам и формируется сигнал «1», поступающий на информационный вход D регистра 2 для организации нового цикла, то есть процесс повторяется.On the next clock cycle, a single pulse is shifted again and a frequency signal F _{y is} formed at the output 8 in a similar way to the processes described above up to

... Further, with the help of the OR-NOT element 10, the completion of the shift process in all digits is recorded and a signal "1" is generated, which is fed to the information input D of register 2 to organize a new cycle, that is, the process is repeated.

For the example described above, a three-bit structure:

n = 3;

On the eighth clock, a pulse is formed using the OR-NOT element 10 and register 2, and no pulses appear at the output of register 2 (axes 16-17, OR-NOT, Fig. 2).

A new cycle of operation of the device begins with the next clock pulse, according to which "1" appears at the output Q _{1 of} register 2 (axes 18-19, Fig. 2). Then the whole process is repeated cyclically.

регистра, подсоединенного непосредственно ко второму входу первого элемента И 6₁. На первые входы элементов И 6 поступают сигналы с соответствующих разрядов шины управления N 7. На третьи входы элементов И 6 поступают сигналы синхронизации со входа F₀. На выходах элементов И 6 создаются опорные импульсные последовательности, которые в зависимости от значения разряда шины управления N 7 поступают на вход элемента ИЛИ 1. В результате, на выходе элемента ИЛИ 1 формируется выходной частотный информационный сигнал F_y.As a result, single pulses are formed, which are weightedly distributed among the inputs of the OR elements 9. Thus, the reference frequencies are formed, arriving at the second inputs of the AND elements 6 from the outputs of the OR elements 9 and the output

register connected directly to the second input of the first element AND 6 ₁ . The first inputs of the elements And 6 receive signals from the corresponding bits of the control bus N 7. The third inputs of the elements And 6 receive synchronization signals from the input F ₀ . At the outputs of the elements AND 6, reference pulse sequences are created, which, depending on the bit value of the control bus N 7, are fed to the input of the OR element 1. As a result, the output frequency information signal F _y is generated at the output of the OR element 1.

The operation of a frequency divider with a variable division ratio is based on the principle of a weighted single-stage distribution of pulses from the outputs of the shift register along the reference frequency sequences and automatic start of cyclic operation with the permission of signals passing to the output of the device in the presence of a unit on the corresponding bit of the control bus.

The logical expression for the output of device 8 is as follows:

Function L in the general case for each i-th input of the OR element 1 is formed on the corresponding elements AND 6:

L _i = T _i ⋅P _i ⋅F ₀ ,

–логическое состояние i-го разряда кода управления;where

–The logical state of the i-th bit of the control code;

- взвешенно распределенный выход i-го множества разрядов Q регистра 2;

- weighted distributed output of the i-th set of bits Q of register 2;

– логическое состояние тактового импульса.

- logical state of the clock pulse.

включает в себя один элемент Qс основанием

и номером

:First set

includes one element Q with a base

and number

:

формируется из двух элементов Qс основанием

и номерами

и

:Second set

formed from two elements Q with a base

and numbers

and

:

образуется из четырех элементов Qс основанием

и номерами

и

:Third set

formed from four elements Q with a base

and numbers

and

:

In the next set, the number of elements Q is doubled, the exponent of the base is reduced by one more, and the numbers are also assigned with the corresponding multiplication of the numbers of the odd series.

содержит

элементов Qс основанием

равным единице и номерами нечетного ряда до

The last set

contains

elements Q with base

equal to one and odd numbers up to

повторением.As a result, in the sequences L ₁ , L ₂ , ..., L _n , pulses are formed that are spaced in time, therefore, at the output of the OR 1 gate, the formation of a total frequency with a cyclic

repetition.

The values of the frequencies at the outputs L ₁ , L ₂ , L ₃ , ..., L _n are described by the expressions:

определяется следующим образом:The sum of the output frequency of the device

is defined as follows:

.

...

In this expression, the sum of the products of the value of the current bit of the code T _i and the bit weight of the n-bit control bus 7 is a binary code N.

Thus, the average frequency F _{y of the} pulse stream at the output 8 of the device can be written as follows:

that is, the transfer function of the claimed variable frequency divider corresponds to the transfer function of the prototype.

The speed of the frequency divider is determined by the response time λ:

- время срабатывания сдвигового регистра;where

- response time of the shift register;

- время срабатывания логического элемента с функцией ИЛИ;

- response time of the logical element with the OR function;

- время срабатывания логического элемента с функцией И;

- response time of a logical element with an AND function;

- время срабатывания логического элемента с функцией ИЛИ.

- the response time of the logical element with the OR function.

срабатывания логических элементов в первом приближении можно считать одинаковыми и равными

Time

actuation of logic elements in the first approximation can be considered the same and equal

обычно не превышает

Shift register response time

usually does not exceed

Thus, the response time for the claimed frequency divider is:

определяется выражением:The prototype has a delay when the frequency value changes

defined by the expression:

- время срабатывания счетчика;where

- counter response time;

- время срабатывания логического элемента с функцией И;

- response time of a logical element with an AND function;

- время срабатывания логического элемента с функцией ИЛИ.

- the response time of the logical element with the OR function.

обычно не превышает

Counter response time

usually does not exceed

Thus, the response time for the prototype is:

прототипа. То есть, быстродействие работы заявляемого устройства по сравнению с прототипом увеличено.Therefore, the delay λ when changing the frequency value in the claimed device in the first approximation is 2 times less than the delay

prototype. That is, the operating speed of the proposed device is increased in comparison with the prototype.

In addition, the circuitry simplification of the device is provided.

Claims (1)

A frequency divider with a variable division ratio, containing an OR element with n inputs, a sequential trigger structure, synchronization inputs, setting to the initial state, division permissions, which are the corresponding inputs of a sequential trigger structure, n logical three-input AND elements, the first inputs of which are connected to the corresponding bus bits control, and the outputs of the AND elements are connected to the corresponding inputs of the OR element, the output of which is the information output of the frequency divider, characterized in that n –1 OR elements are introduced into the device into two, four, ..., 2 ^{n –1} inputs, the OR-NOT element for 2 ⁿ –1 inputs, and the sequential trigger structure is made in the form of a shift register for 2 ⁿ –1 bits, the information D- input of which is connected to the output of the OR-NOT element, connected by inputs to the corresponding outputs of the register bits, which are also combined with the inputs elements OR in order: for a two-input element OR ₁ - outputs bit ov

register, for a four-input element OR ₂ - bit outputs

,

,

register and so on until

-input element OR _{n -1} - outputs of digits Q ₁ , Q ₃ , Q ₅ , Q ₇ , Q ₉ , Q ₁₁ , ...,

respectively register, and the output

the register is connected to the second input of the first AND ₁ element, and to the second inputs of the remaining AND elements - the second AND ₂ , the third AND _3, and so on, up to the n -th element AND _n , the outputs of the OR elements, respectively, of the first OR ₁ , the second OR _2, and so on up to the ( n –1) th element OR _{n –1} , while the third inputs of the AND elements are combined with the synchronization input of the device.

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