RU2698285C1 - Method and device for asynchronous serial communication interface and modification thereof - Google Patents

Abstract

FIELD: data processing.

SUBSTANCE: invention relates to digital engineering in the field of information exchange. Asynchronous serial interface of exchange (IE) is intended for information exchange between controller and terminal device. Information is exchanged with 32-bit words divided into bytes and supplemented with start and stop bits. Initiator of exchange is always a controller, which issues command word (CW) for terminal device (TD). CW transmits an operation code (OC), an address of the TD and a number of words for exchange. After CW receiving, TD compares the address in the CW with its own address, after which executes it (the address coincides) or ignores it (the foreign address). If the OC contains the receiving operation, the TD receives the number of data words (DW) specified in the CW, if the dispensing operation, the TD issues the specified number of the DW.

EFFECT: creation of reliable asynchronous interface and controller and TD required for its operation, which will provide for exchange of 32-bit words with high speed of information transfer with minimum quantity of signals between devices.

5 cl, 10 dwg

Description

The invention relates to digital technology in the field of information exchange and can be used in space, aviation, shipbuilding and other industries as an interface for the exchange of information between the controller and the terminal device (OS).

Asynchronous serial communication interface (IO) is intended for the exchange of information between the controller and one terminal device (radial) or several terminal devices (trunk with galvanic isolation). Information is exchanged in 32-bit words, divided into bytes and supplemented with start and stop bits. The initiator of the exchange is always the controller, which issues a control word (CS) for the op-amp. The operation code (CPC), the address of the op-amp, and the number of words to exchange are transmitted to the COP. Having received the KS, the OU compares the address in the KS with its own address, after which it executes it (the address matches) or ignores it (someone else's address). If the receive operation is embedded in the CPC, then the op-amp receives the number of data words indicated in the CS (SD), if the issuing operation, then the op-amp gives the indicated number of SD.

The closest analogues of the method are the radial interface RS232 and the trunk interface RS485 (A. Lapin, Interfaces. Selection and implementation - M .: Technosphere, 2005, pp. 46-53). These interfaces are universal, have a set of standard exchange rates, when using galvanic isolation (RS485) it is possible to transmit information at a distance of up to 1200 m. The disadvantages of these interfaces are the low exchange rate at a standard number of frequencies, as well as the use of a standard number of frequencies not multiple of 1 kHz, which significantly complicates the synchronization process with a processor clock frequency that is a multiple of 1 MHz.

The prototype of the controller and the terminal device is a controller for transmitting and receiving information via a serial asynchronous interface, presented in the manual for the courses "Microprocessor technology" and "Automated systems for scientific research" Ershova N.Yu., Ivashenkov ON, Kurskov S.Yu. . “Microprocessors” (http://dfe.petrsu.ru/koi/posob/microcpu/index.html) in Fig. 3.8 and 3.9. The disadvantages of analogues is the inability to transmit information with a minimum number of signals between devices.

The objective of the invention is the creation of a reliable asynchronous interface and the controller and op-amp necessary for its operation, which will ensure the exchange of 32-bit words with a high information transfer rate with a minimum number of signals between devices.

To solve the problem, a method and devices were developed (controller and op-amp) designed to exchange information without galvanic isolation and located at a distance of up to 1.5 meters. It is possible to introduce galvanic isolation, which increases the distance to 10 meters.

The asynchronous serial exchange interface establishes the following rules for the interaction of the controller and the op-amp: the exchange is always carried out in 32-bit words, divided by bytes, each byte is accompanied by one start and one stop bits and is issued in the sequential code with the least significant bits forward, starting with the most significant byte.

Information is transmitted at a frequency of 4 MHz. The transmission speed of one information, start or stop bit is 0.25 μs. Baud Rate 4 Mbps. The start bit is always transmitted low, the stop bit - high. Lack of data (pause) is transmitted in a high level.

When using galvanic isolation, the EUT works as a trunk, i.e. up to 16 op-amps can be connected to one controller. Connection of two controllers to one trunk is not allowed, and each OS is assigned a personal address in the trunk. The maximum number of words in one premise is 1023.

The figure 1 presents the sequence diagram of one DM in the AI.

The controller performs the following main functions:

- implements interface subscribers with the information transmission line (LPI);

- manages the exchange of information using the COP;

- exercises control over the information received. Shelter performs the following main functions:

- implements interface subscribers with LPI;

- exercises control over the information received;

- executes commands addressed to it by the controller.

The controller is always the initiator of the exchange. After the controller is initialized for information exchange, first the controller issues the SC, then without pauses it gives the LED (issuing operation), or it rises in expectation of the LED from the OS (receiving operation). The waiting time for LEDs from the OS is <16 μs. The absence of LEDs of more than 16 μs is regarded by the controller as the absence of a response from the op-amp, in this case the controller ends the exchange with an error sign. The cop consists of one 32-bit word. If the controller or the OS when receiving information detects a violation of the start (low level), stop (high level) conditions, then such an exchange is marked with an error sign, but continues until the information is completely received.

The format of the COP is presented in figure 2, where:

0-3 digits - the code of the operation (CPC). "1010" is the issue, "1100" is the reception.

4-7 digits - the personal address of the op-amp in the trunk to which the controller refers.

8-21 bits - backup, can be used for specific tasks, in accordance with the software protocol. "0" - the absence of a sign, "1" - the presence of a sign.

22-31 digits - word counter (SS). The number of 32-bit words to be exchanged (maximum 1023).

The figure 3 presents a timing diagram of the operations of receiving and issuing information.

At the time of receiving information, the output information signals of the controller and the op-amp are set to the third state. This makes it possible to simplify the connection scheme of one op-amp with a controller. The scheme of such a docking is presented in figure 4. The scheme of docking of an IO with galvanic isolation depends on the type of transceiver.

Since the known devices are not suitable for working on the IO, a controller was developed, the circuit of which is presented in figure 5 and includes the following elements:

1 - control unit (UPR);

2 - exchange counter (SChob);

3 - word counter (SChsl);

4-shift register issuance (SRV);

5 - block multiplexing exchange (MO);

6 - output information block with the inclusion of the 3rd state (PER);

7 - block receiving information (PFP);

8 - block multiplexing and analysis of the reception of information (MOiA);

9 - shift reception register (SRP);

10 - register of the received word (RSp);

11 - pause counter pending data words (SCPau).

Elements of the structural diagram of the controller have the following relationships:

The controller receives: a signal of the beginning of input-output (NVV), a 32-bit signal for the issuance of information (ШДв0-31), reception information (И_П). The controller output includes: a 32-bit signal of received information (ШДп0-31), output information (И_В), a sign of an error in the exchange format (OShf) (start-stop) when receiving LEDs from an op-amp, an indication of an error in waiting (OShp) SD Opamp (> 16 μs).

The 32-bit signal ШДв0-31 arrives at SRv (4), its 0-3 bits additionally arrive at the control unit (1), and discharges 22-31 go to the SChsl (3).

The HBV signal arrives at the control unit (1) and SChsl (3). When SChsl (3) becomes equal to zero, the signal generated by the word counter is zero (CC0), which is fed to the control (1).

From UPR (1) the following signals are generated: loading a word (ZS), which is fed to SRv (4); exchange (OBM), which is received at SChob (2), SChsl (3), SRv (4), SRp (9), RSp (10); reception (PFP), which is received at the PER (6), PFP (7), SRP (9), RSp (10), SChpau (11); loading the word register (ZRS), which is fed to the RSp (10).

SChob (2) is connected: by 4-bit signal bytes (BT1-4) with SRV (4) and SRp (9); 3-digit signal of markers (MK1-3) with SChsl (3), MO (5) and MOiA (8), which generates an OShf signal and is connected by a 4-bit signal of a serial reception code (PKp1-4) with SRP (9 ), which is connected by a 32-bit signal of the parallel code PK0-31 with RSp (10), from which a 32-bit signal ШДп0-31 is sent to the output of the circuit.

CPv (4) is connected with a 4-bit signal of a serial issuing code (PKv1-4) with MO (5), connected by a signal of information for issuing (INFV) with PER (6), which generates the output signal I_V.

The I_P signal is fed to the PfP (7), which generates a reception information signal (IFP), which is supplied to the control unit (1), MO&A (8) and SChpau (11), from which the output signal of the open loop signal is also generated, which also goes to the control unit (1) .

The principle of operation of the controller:

The figure 6 presents a block diagram of the controller. All controller units operate at a frequency of 4 MHz, except for the PFP unit (7), which operates at a frequency of 16 MHz, which is why it does not lose the received information.

Issue operation for the controller:

Based on the NVB signal, the controller is initialized to work and the operation code (0-3 bits of ШДв) is loaded into the control unit (1). If these bits are equal to "1010", then the control unit (1) is configured for the operation of information output. Also, according to the NVB signal, the number of words for exchange (22-31 bits of ШДв) is loaded into the SCL (3), and another word (CS) is added to the number of words.

Next, the UPR (1) generates an OBM signal - a sign of the beginning of the exchange, according to which the SChob counter (2) begins to count, and the reset is removed from SRv (4) and SChsl (3). Also, from the UPR (1), an ES signal is generated, according to which the shift register SRv (4) is loaded in parallel.

After parallel loading of СРв (4), the counter СЧоб (2) starts to read bytes of information - BT1-4 signals, which are fed to the shift register СРв (4). Signals BT1-4 alternately rise to a high level at the time of issuing the desired byte of information and alternately push information from CPv (4). Switching BT1-4 signals among themselves are separated by pauses of 2 bits (for start-stop format). Thus, at the output of CPv (4) we have 4 signals PCv1-4 on which byte, in a sequential code, the least significant bits advance information (CS).

Also from SCHob (2) 3 control signals MK1-3 are generated, which are fed to the MO multiplexer (5). These signals in the MO (5) multiplex PCv1-4 signals and add the start (low level) and table (high level) bits. At the output of MO (5), the information is obtained in a sequential code in accordance with figure 1 and 3.

Through the PER block (6), in the issuing operations, the information passes unchanged and leaves the circuit by the signal AND.

At the end of the issuance of the SC, the unit is subtracted from the SChsl (3) by the control signals MK1-3. If SChsl (3) is not equal to zero, after subtraction of one, then the issuance of the first CD begins similarly to issuing KS and so on until SChsl (3) counts to zero.

When SChsl (3) becomes equal to zero, the MTR signal is generated, which is fed to the control (1). After processing this signal, the UPR (1) removes the OBM signal and ceases to generate the ES signal. SCHob (2), SRv (4), SChsl (3) when the OBM signal is removed, are reset and set to the initial state. The issuance of information is completed.

Receive operation for the controller:

The issuance of the COP in exchange transactions is similar to the issuance of the COP in issuing operations. The code when loading ШДв0-3 in control unit (1) should be “1100”

After the issuance of the COP, the unit is subtracted from the SCN (3) similarly to the issuing operation. Further, if SChl (3) is equal to zero, then the exchange ends similarly to the issuing operation.

If SChsl (3) is not equal to zero, then after issuing the SC, the circuit proceeds to perform the receive operation. UPR (1) generates a PFP signal, by which PER (6) sets the output signal I_V to the 3rd state. Block PFP (7) by the corresponding signal PFP opens to receive the signal And_P. The reset is also removed from SRP (9), RSp (10) and starts counting the pause counter SCCHpau (11). The OBM signal is also taken and the counting counter SchCO (2) ceases to be read.

The information on the signal I_P in the PFP block (7) is overwritten with a frequency of 16 MHz and goes to the signal INFP. If SChpau (11) counted 16 microseconds, and the low level (start bit) did not appear on the INFP signal, then SChpau (11) generates a reception error signal (there is no response from the subscriber) OSP, which goes to the output of the circuit and in control (1) . The control unit (1) is reset by the signal of the open loop and is set in anticipation of a new initialization by the signal of the NVB. The PFP signal is removed, the exchange is completed.

If the information from the op-amp arrives earlier than 16 μs, then the midrange (11) is reset by the INFP signal, and the control unit (1) generates an OBM signal, by which it starts to count the middle frequency counter (2) and generate BT1-4 and MK1-3 signals (similar to the operation issuance). The INFP signal also arrives at MOiA (8), in which, using the MK1-3 control signals, the parallel code from the INF signal is multiplexed into 4 signals in a serial code, one byte each (PKp1-4). Using signals MK1-3 in MO&A (8), the presence of a low level at the start and high levels at the stop bits is also analyzed. If the format is start (low level), stop (high) is not respected, then MO&A (8) generates an error of the error code format, which goes to the output of the circuit.

Regardless of whether the start-stop format is violated, reception continues until the requested number of words is fully received.

The four received MO&A (8) bytes, in the parallel code PKp1-4, are loaded into the CPP (9) using BT1-4 signals. To save the received LED, while receiving the next one, the information in the parallel code (signal PK0-31) is rewritten in RSp (10) by the signal of the ZRS. From RSp (10), the signal ШДп0-31 leaves the circuit.

After receiving the SD, the unit is subtracted from the SChsl (3) according to the control signals MK1-3. If the SChsl (3) is not equal to zero, after subtraction of one, then the reception of the next SD continues, and so on until the time Schsl (3) counts to zero.

When SChsl (3) becomes equal to zero, the signal CC0 is generated, which is fed to the control (1). After processing this signal, the UPR (1) removes the OBM signal and ceases to generate a ZRS signal. SCHob (2), SRp (4), SChsl (3) when the OBM signal is removed, are reset and set to the initial state. Reception of information is completed.

To increase the distance from the controller to the op-amp, the input / output coding scheme according to the Manchester-2 code is introduced into the IO (Lapin A. Interfaces. Choice and implementation - M .: Technosphere, 2005, pp. 101-107). The figure 7 presents a structural diagram of a controller with encoding information for Manchester-2. For UO, with good noise immunity and guaranteed operation of the main IO to a distance of 50 m with galvanic isolation, the operating frequency is reduced from 4 MHz to 1 MHz (the duration of one bit is 1 μs) and the construction scheme of galvanic isolation is applied, in accordance with the main interface according to GOST R 52070-2003.

The block diagram of the controller with the code "Manchester-2" is shown in FIG. 7 and has the following differences:

1. Instead of PER (6), a CD encoder (12) was introduced to encode output information using the Manchester-2 code.

2. Instead of PFP (7), a decoder DK (13) was introduced to decode input information using the Manchester-2 code.

3. The PFP signal does not arrive at the CD (12).

4. The signal output information I_V is replaced by two signals INF0_V, INF_1 B encoded in the Manchester-2 code and received from the CD (12) to the output of the circuit.

5. The I_P reception information signal has been replaced by two signals INF0_P, INF1_P encoded by the Manchester-2 code and transmitted to the recreation center (13).

6. An encoding error signal (OShk) has been introduced, which is generated by the DC (13) in receive operations when encoding is violated according to Manchester-2 and which leaves the circuit.

7. To increase the pause pause for LEDs from the op-amp by more than 16 μs, a pause duration signal (Тп1-5) is introduced into the circuit, which is fed to the midrange (11). Depending on the code specified in this signal, the waiting time is hardware or software adjustable and can be 16, 32, 64, 128 μs or more.

The terminal device to work on the exchange interface.

In FIG. 8 is a structural diagram of an op-amp for operating on IO including the following elements:

14 - control unit (UPR);

15 - exchange counter (SCHob);

16 - word counter (SChsl);

17 - shift register issuance (SRV);

18 - block multiplexing exchange (MO);

19 - block output information with the inclusion of the 3rd state (PER);

20 - block receiving information (PFP);

21 - block multiplexing and analysis of the reception of information (MOiA);

22 - shift reception register (SRP);

23 - the register of the adopted word (RSp);

24 - address comparison unit (AD);

25 - counter pause pending data words from other terminal devices (SChpau).

Elements of the structural diagram of the OS have the following relationships:

The following signals are fed to the op-amp circuit: a 32-bit signal for issuing information (ШДв0-31), reception information from the controller - (И_П) and a signal of its own address (ADR1-4). The following signals come out of the op-amp circuit: a 32-bit signal of received information (ШДп0-31), output information (И_В), a sign of an error in the exchange format (start-stop) when receiving information (Ошф), and the signal is the correct address (VA).

The 32-bit signal ШДв0-31 arrives at SRv (17).

UPR (14) generates signals: loading a word (ZS), which is fed to SRv (17); exchange (OBM), which is received at SChob (15), SChsl (16), SRv (17), SRp (22), RSp (23), blood pressure (24); reception (PFP), which is received at PER (19), PFP (20), SRP (22), RSp (23); loading the word register (ZRS), which is fed to the RSp (23); loading the command word (ZKS), which is supplied to the SChsl (16) and HELL (24); a foreign address (CH) that arrives at SChpau (25), a reception error (OShp) signal associated with the control (14).

SChob (15) produces: 4-bit byte signal (BT1-4), which is fed to SRv (17) and SRp (22); 3-digit marker signal (MK1-3), which is fed to the SChSl (16), MO (18) and MOiA (21).

From SCHsl (16) a signal is generated; the word counter is equal to zero (CC0), which is fed to the control (14).

СРв (17) generates a 4-bit signal of a sequential issuing code (PCv1-4), which arrives at the MO (18), which is connected by the information-to-issuance (INFV) signal with the PER (19), which generates an I_V signal, which is output from op amp circuits.

The signal I_P arrives at the PFP (20), which generates a signal information for reception (INF) received at the control unit (14) and MO&A (21).

MOiA (21) produces signals: 4-bit signal of the serial reception code (PKp1-4), arriving at the SRP (22); OShf, coming out of the circuit.

SRP (22) generates a 32-bit parallel code signal (PK0-31), from which bits 0-3 go to the control gear (14), bits 4-7 go to the BP (24), and bits 22-31 go to the SCH (16), while all 32 bits are fed to the RSp (23), which generates a 32-bit signal ШДп0-31, which is output from the circuit.

The signal of its own address (ADR1-4) is fed to the AD (24), which generates a signal VA, which is fed to the control unit (14) and is output from the circuit.

The principle of operation of the OS:

The figure 9 presents a block diagram of the op-amp.

All op-amp blocks, similar to controller blocks, operate at a frequency of 4 MHz, except for the PFP unit (20), which operates at a frequency of 16 MHz, which is why it does not lose received information.

The op-amp is always waiting for the COP from the controller. Therefore, in the initial state, the signal of the sign of reception of PFP information is at a high level, which means that the signal AND from the PER unit (19) is in the 3rd state, and the PFP (20) is open for receiving information.

When information appears on the I_P signal in the PFP block (20), it is rewritten with a frequency of 16 MHz and goes to the INFP signal. At a low level (a sign of the start bit) on the INFF signal, the UPR block (14) generates an OBM signal that triggers the SCHob (15) and BT1-4 and MK1-3 signals are generated. The INFP signal is also fed to MOiA (21), in which, using the MK1-3 control signals, the parallel code with the INF signal is multiplexed into 4 signals, one byte each (PKp1-4). Using signals MK1-3 in MO&A (21), the presence of a low level at the start and high levels at the stop bits is also analyzed. If the format is start (low level), stop (high) is not respected, then MO&A (21) generates an error of the error code format, which goes to the output of the circuit.

Subject to the format, the four received MO&A (21) bytes, in the parallel code PKp1-4, are loaded into the CPp (22) using BT1-4 signals. Thus, the received CS is stored on the output signal PK0-31 of the SRp block (22). 0-3 bits of the CS are loaded into the control unit (14). Using the ZKS signal, 22-31 bits (the number of words to exchange) are loaded into the SChSl (16), and 4-7 bits are loaded into the blood pressure (24).

In AD (24), the address received by the CS is compared with the OA own address, which is set by the signal ADR1-4. If the address does not coincide during reception operations, then the VA signal remains low and the control (14) will not generate a ZRS signal, information will be received, but will not be copied to the RSp (23).

The signal (VA) is a sign of the beginning of the reception of information when comparing the own address of the OS with that received by the SC. The absence of a high level on the VA signal issued from the circuit indicates that the exchange is made with another op-amp.

If the address matches, then the op-amp device proceeds to the execution of the received CS.

If the SCHl (16) loaded on the SC is equal to zero, then the signal CC0 is generated and the control (14) is set to the initial state and removes the OBM signal, according to which the SchW (15), SChs (16), and SRp (22) are also set to the initial state and the circuit of the op-amp becomes in anticipation of the next COP.

Receive operation for op-amp:

0-3 bits of the CS equal to "1010", mean the operation of receiving LED for the OS.

If SChsl (16), loaded on KS is not equal to zero, then the OBM signal is not removed and the reception of LEDs from the controller begins. The difference in the reception of the LED from the reception of the CS is that each received LED from the signal PK0-31 is copied to the RSp (23), and the SCHsl (16) and the blood pressure (24) are no longer loaded.

After receiving each LED by the control signals MK1-3, the unit is subtracted from SChsl (16). If SChsl (16) is not equal to zero, after subtraction of one, then the reception of the next SD continues. When the SChsl (16) becomes equal to zero, the signal CC0 is generated, which is fed to the control (14). After processing this signal, the UPR (14) removes the OBM signal. Units SChob (15), SChsl (16), SRp (22), RSp (23) and HELL (24) are set to the initial state by the absence of the OBM signal and the op amp circuit awaits the next CS. Reception of information is completed.

If during reception a violation of the start-stop format was detected, then the MO&A unit (21) generates an OShf signal. Even if a violation of the format has been recorded, the reception of information continues until the op-amp has finished receiving all the LEDs.

Issuance operation for the op-amp:

Reception of the COP during the issuing operation is similar to the reception of the COP during the receiving operations.

0-3 bits of the CS equal to "1100" mean the operation of issuing LED for the OS.

Similar to the receive operation, the address from the CS is compared with its own address. If the address is not compared, then the UPR (14) does not remove the PFP signal and stands in anticipation of receiving the LED from the OS, to which the CS was addressed. UPR (14) also generates a signal of the frequency response, which starts the pause counter SCCHau (25).

SChpau (25) starts a pause count of 16 μs. If the LED from the other op-amp does not arrive in 16 μs, then the SChpau (25) generates an OShp signal, according to which the UPR (14) removes the OBM signal, the circuit is reset, and the op-amp is waiting for the next CS. If the LED from another op-amp arrives earlier than 16 µs, then the op-amp fulfills the reception of the LED similar to the receive operation for a foreign address.

If the address from the COP is compared with its own address, then the op-amp proceeds with the issuing operation.

If SChsl (16) loaded on KS is not equal to zero, then the OBM signal is not removed and the issuing of LEDs for the controller begins. The UPR block (14) removes the PFP signal, which closes the reception of information in the PFP (20), the SRP (22) and RSp (23) are reset, and the PER block (19) generates a high level signal (instead of the 3rd state). Also, the UPR (14) generates an ES signal, through which parallel loading of information from the input signal ШДв0-31 into the shift register СРв (17) takes place.

After the parallel loading of SRV (17), the SCHob counter (15) starts to generate BT1-4 and MK1-3 signals similarly to the controller circuit. Using signals BT1-4, at the output of SRv (17), 4 signals PKv1-4 are generated, which byte-by-bit, in a sequential code, information (SD) is pushed forward by the lower digits.

Using the MK1-3 signals, in the MO (18), PCv1-4 signals are multiplexed and the start (low level) and table (high level) bits are added. At the exit from the MO (18), the information is obtained in the finished sequential code in accordance with figure 1 and 3.

Through the PER block (19), in the issuing operations, the information passes unchanged and leaves the circuit by the signal AND.

At the end of the first LED, the unit is subtracted from the SChs value (16) by the control signals MK1-3. If the SChsl (16) is not equal to zero, after subtraction of one, then the next CD will be issued, and so on until the SChsl (16) counts to zero.

When the SChsl (16) becomes equal to zero, the signal CC0 is generated, which is fed to the control (14). After processing this signal, the UPR (14) removes the OBM signal and ceases to generate the ES signal. SChob (15), SChsl (16), SRv (17) and HELL (24) when the OBM signal is removed, are reset and set to the initial state. The issuance of information is completed.

To increase the distance from the controller to the OS IO 50 m with galvanic isolation, similar to the controller, the Manchester-2 encoding is introduced into the OS scheme. The structural diagram of the op-amp with coding "Manchester-2" is presented in figure 10 and has the following differences in comparison with FIG. eight:

1. Instead of the PER block (19), a CD encoder (26) was introduced to encode output information using the Manchester-2 code.

2. Instead of the PFP block (20), a decoder DK (27) was introduced to decode input information using the Manchester-2 code.

3. The PFP signal does not arrive at the “CD” (26).

4. The signal output information I_V is replaced by two signals INF0_V, INF1_V encoded in the Manchester-2 code and coming from the CD (26) to the output of the circuit.

5. The reception information signal I_P has been replaced by two signals INF0_P, INF1_P, encoded by the Manchester-2 code and received by the DC (27).

6. An encoding error signal (OShk) has been introduced, which is generated in a recreation center (27) in receiving operations when encoding is violated according to Manchester-2 and enters the circuit.

7. Similarly to the controller circuit, in order to increase the waiting time for LEDs from other op amps, a pause signal (Tn1-5) is input to the opamp circuit and fed to the midrange (25).

The technical result of the invention is:

1. Ensuring IO of the exchange rate of 4 Mbaud with a word length of 32 bits, the distance between the controller and the op-amp is up to 1.5 m, and using galvanic isolation - up to 10 m.

2. The controller and terminal device, ensuring the operation of the EUT.

3. The controller and the terminal device with galvanic isolation, providing work with encoding on the Manchester-2 interface and the distance between the controller and the op-amp is up to 50 m.

Thus declared:

1. Asynchronous serial interface for the exchange of information, according to which the controller initiates the exchange of information and exchanges 32-bit words, divided into bytes; the controller eats out a command word for the terminal device, in which each byte is accompanied by start and stop bits and is issued by a sequential code with the least significant bits forward, starting with the high byte; the command word contains reserve bits about the number of words for exchange, the maximum number of which is 1023, the direction of exchange and the address of the terminal device to which it is addressed; in issuing operations, after issuing a control word, the controller starts issuing data words; in receiving operations, after issuing a control word, the controller stands by waiting for data words from the terminal device; the command word and data words are transmitted without pauses; the start bit is transmitted in a low level, the table bit and the lack of information in a high level; the duration of one bit is 250 ns; the terminal device starts the exchange of information with the controller when its own address matches the one specified in the command word; if there is no data word from the terminal device 16 µs, the controller ends the current exchange.

2. A controller comprising a control unit (1), a shift register (4), a shift register (9), a register of a received word (10), characterized in that the shift register (4) receives 32 bits of a signal for outputting information, the lower 4 digits are additionally fed to the control unit (1), and the highest 10 digits are fed to the word counter (3), which receives an input / output start signal, also fed to the control unit (1), which generates word loading signals, arriving at the shift register of delivery (4), the signal for the word register load entering the received word register (10), the exchange signal arriving at the exchange counter (2), word counter (3), shift output register (4), shift receive register (9) and received word register (10) , which also receives a reception signal, which additionally arrives at the standby pause counter of a data word (11), a shift reception register (9), an information reception unit (7) and an output information block with the inclusion of the 3rd state (6); the exchange counter (2) generates a 4-bit byte signal, which is transmitted to the shift register of output (4) and to the shift register of reception (9) and a 3-bit marker signal, which goes to the exchange multiplexing unit (5), the multiplexing unit and analysis of the received information (8) and a word counter (3) that generates a corresponding signal that is equal to logical zero and is sent to the control unit (1); the shift register of output (4) generates a 4-bit signal of a serial code of output, which is fed to the exchange multiplexing unit (5), which generates a signal for output, which arrives at the output information block with the inclusion of the 3rd state (6), which generates a signal information issuance received at the output of the device; the reception information signal enters the device to the information receiving unit (7), which generates a reception information signal arriving at the control unit (1), a data word wait pause counter (11), and a received information multiplexing and analysis unit (8) that generates a format error signal, which is output from the device, and a 4-bit serial reception code signal, which is transmitted to the shift reception register (9), which generates a 32-bit parallel code signal, received at the received word register (10) that generates a 32-bit signal of the received information coming out of the device, the pause counter for the data word (11) generates a reception error signal, which enters the control unit (1) and leaves the device.

3. The controller device according to claim 2, characterized in that the output information unit with the inclusion of the 3rd state (6) is replaced by an encoder (12), which does not receive a signal and from which two signals are output to the device output information on “Manchester-2” code, and the information reception unit (7) is replaced by a decoder (13), to which two signals are received, information is received by the “Manchester-2” code and an additional signal is generated, the coding error, while the standby pause counter data word (11) comes a 5-bit signal al pause duration.

4. A terminal device for an asynchronous serial information exchange interface, comprising a control unit (14), a shift register (17), a shift register (22), a register of a received word (23), characterized in that the shift register (17) receives 32 discharge signal to issue information; the control unit (14) generates a word load signal arriving at the shift register (17), a word register load signal that goes to the received word register (23), an exchange signal that goes to the exchange counter (15), word counter (16 ), the shift register of the issuance (17), the register of the received word (23), the block comparing the address (24) and the shift register of the reception (22), the receive signal, which is transmitted to the register of the received word (23), the shift register of the reception (22), information receiving unit (20) and output information unit with the inclusion of the 3rd state (19), signal a foreign address that arrives at the pause counter for waiting for data words from other terminal devices (25) and a command word load signal that appears on the word counter (16) and the address comparison unit (24); the exchange counter (15) generates a 4-bit byte signal, which is transmitted to the shift register (17) and to the shift reception register (22) and a 3-bit marker signal, which goes to the word counter (16), the exchange multiplexing unit (18) and a unit for multiplexing and analyzing received information (21); a word counter (16) generates a signal; the word counter is zero, which is fed to the control unit (14); the shift register of delivery (17) generates a 4-bit signal of the serial code of the issuance, which is transmitted to the exchange multiplexing unit (18), which generates a signal for output, which arrives at the output information block with the inclusion of the third state (19), which generates a signal issuing information coming out of the device; the reception information signal is fed to the information reception unit (20), which generates a reception information signal received by the control unit (14) and the received information multiplexing and analysis unit (21), which generates a format error signal, which is output from the device and 4 the x-bit signal of the serial reception code, which is transmitted to the shift reception register (22); the pause counter for waiting for a data word from other terminal devices (25) generates a reception error signal, which is sent to the control unit (14), which generates a 32-bit parallel code signal, which is received on the received word register (23), of which 4 are the least significant bits arrive at the control unit (14), and 10 high-order bits go to the word counter (16), 4 bits go to the address comparison unit (24), and all 32 bits go to the received word register (23), which generates a 32-bit signal received information arriving at output from the device; the device receives a 4-bit signal of its own address and then goes to the address comparison unit (24); From the address comparison unit (24), the signal is the correct address, which enters the control unit (14) and leaves the device.

5. The terminal device according to claim 4, in which the output information block with the inclusion of the 3rd state (19) is replaced by an encoder (26), which does not receive a signal and from which two signals come out information on the code "Manchester-2 »Leaving the device; the information receiving unit (20) is replaced by a decoder (27); two signals of the reception information according to the Manchester-2 code are received into the device and further to the decoder (27), and an additional coding error signal is generated; a 5-bit pause signal arrives at the device, and then into the pause counter for waiting for data words from other terminal devices (25).

Claims (5)

1. Asynchronous serial interface for the exchange of information, according to which the controller initiates the exchange of information and exchanges 32-bit words, divided into bytes; the controller issues a command word for the terminal device, in which each byte is accompanied by start and stop bits and is issued as a sequence of low-order bits in sequence, starting with the most significant byte; the command word contains reserve bits about the number of words for exchange, the maximum number of which is 1023, the direction of exchange and the address of the terminal device to which it is addressed; in issuing operations, after issuing a control word, the controller starts issuing data words; in receiving operations, after issuing a control word, the controller stands by waiting for data words from the terminal device; the command word and data words are transmitted without pauses; the start bit is transmitted in a low level, the stop bit and the lack of information in a high level; the duration of one bit is 250 ns; the terminal device starts the exchange of information with the controller when its own address matches the one specified in the command word; if there is no data word from the terminal device 16 µs, the controller ends the current exchange. 2. A controller comprising a control unit, a shift register for issuing, a shift register for receiving, a register for a received word, characterized in that the shift register for receiving receives 32 bits of a signal for outputting information, while the lower 4 bits are additionally fed to the control unit, and the highest 10 bits enter a word counter, which receives an input signal for input-output beginning, also arriving at a control unit that generates signals, loading a word, arriving at a shift register, a signal loading a word register a, the signal received at the received word register, the exchange signal at the exchange counter, word counter, shift register of reception, the shift register of reception and the register of the received word, which also receives the signal of reception, additionally received at the pause counter of the data word, shift register of reception , an information receiving unit and an output information unit with the inclusion of the 3rd state; the exchange counter generates a 4-bit byte signal, which is transmitted to the shift register of output and to the shift register of reception, and a 3-bit signal of markers, which goes to the block of multiplexing exchange, the block of multiplexing and analysis of received information and the word counter, which generates the corresponding signal, which is equal to logical zero and goes to the control unit; the shift register of generation generates a 4-bit signal of a serial code of issuance, which is transmitted to the exchange multiplexing unit, which generates a signal for information to be supplied to the output information block with the inclusion of the 3rd state, which generates a signal for information to be transmitted to the output of the device; the reception information signal enters the device to the information receiving unit, which generates the reception information signal arriving at the control unit, a data word wait pause counter and the received information multiplexing and analysis unit, which generates a format error signal, coming out of the device and 4-bit a serial reception code signal that arrives at the shift reception register generating a 32-bit parallel code signal that arrives at the received word register, generating 32-bit signal received information coming out of the apparatus, the waiting data word pause error counter generates a reception signal which is supplied to the control unit and exits the apparatus. 3. The controller device according to claim 2, characterized in that the output information unit with the inclusion of the 3rd state is replaced by an encoder, which does not receive a signal and from which two signals are output to the device output according to the "Manchester-2" code, and the information reception unit is replaced by a decoder, to which two signals are received according to the Manchester-2 code and an additional signal is generated, an encoding error, while a 5-bit pause signal arrives at the device for the pause counter for the data word s. 4. A terminal device for an asynchronous serial information exchange interface, comprising a control unit, a shift register for output, a shift register for receive, a register for a received word, characterized in that the shift register for receive receives 32 bits of a signal for outputting information; the control unit generates a word load signal arriving at the shift register of output, a signal load word register that goes to the register of the received word, an exchange signal that goes to the exchange counter, word counter, shift register of output, register of the received word, address comparison unit and shift reception register, reception signal, which is received on the received word register, shift reception register, information reception unit and output information unit with the inclusion of the 3rd state, the signal of the alien address, which is received from a pause timer for waiting for data words from other terminal devices and a command word loading signal that appears on the word counter and address comparison unit; the exchange counter generates a 4-bit byte signal, which is transmitted to the shift register of output and to the shift register of reception, and a 3-bit signal of markers, which goes to the word counter, block of multiplexing exchange and block of multiplexing and analysis of received information; the word counter generates a signal; the word counter is zero, which is fed to the control unit; the shift register of delivery generates a 4-bit signal of a serial code of the issuance, which is transmitted to the exchange multiplexing unit, which generates a signal for output, supplied to the output information block with the inclusion of the 3rd state, which generates a signal for output information, which is output from the device; the reception information signal is supplied to the information reception unit, which generates a reception information signal received by the control unit and the received information multiplexing and analysis unit, which generates a format error signal, which is output from the device and a 4-bit signal of the serial reception code that is received shift register reception; the pause counter for a word of data from other terminal devices generates a reception error signal, which is transmitted to the control unit, which generates a 32-bit parallel code signal, which is transmitted to the received word register, from which the 4 least significant bits are sent to the control unit, and 10 higher bits are received to the word counter, 4 digits go to the address comparison unit, and all 32 digits go to the received word register, which generates a 32-bit signal of received information that is output from the device; the device receives a 4-bit signal of its own address and then goes to the address comparison unit; The signal from the address comparison unit exits the correct address, which enters the control unit and exits the device. 5. The terminal device according to claim 4, in which the output information block with the inclusion of the 3rd state is replaced by an encoder, which does not receive a signal and from which two signals are output information according to the Manchester-2 code, leaving the device; the information receiving unit is replaced by a decoder; two signals of reception information according to the Manchester-2 code are received into the device and further to the decoder, and an additional signal, coding error, is generated; a 5-bit pause signal comes to the device, and then to the pause pause counter for data words from other terminal devices.

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