RU2588257C1 - Method of balance of voltages on capacitors of single-phase three-level converter with locking diodes - Google Patents

Abstract

FIELD: electronic equipment.

SUBSTANCE: invention can be used in designing electromechanical systems, for example, in creating alternating current generating systems. In method of balancing voltages on capacitors of single-phase three-level converter with locking diodes on pulse-width modulation cycle, combination of conditions of switches, responsible for formation of master vector, is selected. Control pulses are generated according to selected combinations conditions of switches. Generated control pulses are transmitted to inputs of transistors of single-phase three-level converter with locking diodes. From selected combinations of conditions of switches are excluded combinations, which do not perform balance of voltages on capacitors.

EFFECT: longer time intervals of combinations conditions of switches, acting on balance of voltages on capacitors, which increases speed of balance of voltages on capacitors of DC link.

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Description

The present invention relates to the field of electrical engineering and can be used to control a single-phase three-level converter with fixing diodes when creating electrical systems, for example, when creating systems for generating alternating current.

There is a method of balancing the voltage across the capacitors of a single-phase three-level converter with fixing diodes (article Wen Sheng Song, XiaoYun Feng, etc. "A neutral point voltage regulation method with SVPWM control for single-phase three-level NPC converters" - Proceedings of the Conference on Vehicle Power and Propulsion, Harbin, September 3-5, 2008, PP. 1-4), in which information is taken from the sensor about alternating current, dq conversion is carried out, the currents of the DC link capacitors are determined taking into account the key state combinations, the middle line current is calculated , calculate the voltage difference of the capacitors, calculate the time to redistribute the duration of the inclusion of combinations of the state of the keys responsible for the voltage balance of the capacitors form control pulses of the corresponding transistors.

In this method, the disadvantage is that each operation is performed with an error, which leads to the accumulation of errors and a decrease in the accuracy of the control method of a single-phase three-level converter with fixing diodes.

In addition, a method is known for balancing the voltage across capacitors of a single-phase three-level converter with fixing diodes (article Zhang Zhi, Xie Yun-xiang, Huang Wei-ping, etc. "A New SVPWM Method for Single-phase Three-level NPC Inverter and the Control Method of Neutral Point Voltage Balance "- Proceedings of the International Conference on Electrical Machines and Systems, Tokyo, November 15-18, 2009, PP. 1-4), which is the prototype of the present invention and consists in the fact that the pulse-width modulation select combinations of key states responsible for the formation of the master vector, form control pulses according to nnym combinations of states of keys generated control pulses are fed to the inputs of a single-phase three-level inverter transistors with clamping diodes.

In this method, the disadvantage is that on the pulse-width modulation cycle there are time intervals corresponding to combinations of key states that are not responsible for the voltage balance on the capacitors of the DC link, which leads to a reduction in the time intervals of combinations of key states affecting the voltage balance of capacitors and , consequently, to a decrease in the speed of the voltage balance on the capacitors of the DC link.

The objective of the invention is to create a method of balancing the voltage on the capacitors of a DC link of a single-phase three-level converter with fixing diodes when implementing vector pulse-width modulation, which eliminates time intervals corresponding to combinations of states of keys that are not responsible for the voltage balance on the capacitors of a DC link, which leads to an increase in the time intervals of combinations of key states affecting the voltage balance of the capacitor in and, therefore, to increase the speed of the voltage balance on the capacitors of the DC link.

The problem is achieved in that in the known method of balancing the voltage on the capacitors of a single-phase three-level converter with fixing diodes on the pulse-width modulation cycle, key state combinations responsible for the formation of the master vector are selected, control pulses are formed according to the selected key state combinations, the generated control pulses are fed to transistor inputs of a single-phase three-level converter with fixing diodes, and from the selected combinations of states lyuchey exclude combinations which do not implement the stress balance of the capacitors.

In FIG. 1 shows a block diagram of a device that implements the proposed method of balancing the voltage across the capacitors of a single-phase three-level converter with fixing diodes. In FIG. 2 is a vector diagram illustrating a balance method.

The device (Fig. 1) contains a single-phase three-level converter with fixing diodes (OTP) - 1. In the DC link of the converter 1, capacitors C1 and C2 are connected in series - 2 and 3. Sensors 4, 5 are connected to these capacitors. Sensor outputs 4 and 5 are connected to block 6 - a circuit for calculating the voltage difference of capacitors C1 and C2. Block 6 is connected to the key state combination selection circuit - block 7. The output of block 7 is connected to the input of the pulse-width modulation block - 8.

The method of balancing the voltages on the OTP capacitors is as follows: the voltage from capacitors C1 and C2 - 3 and 4 is removed by sensors 5, 6 and fed to the input of block 6. In this block, the voltage difference of the capacitors C1 and C2 is calculated. The calculation result is fed to block 7, where the key state combinations are selected, which are responsible only for the voltage balance of the capacitors of the DC link C1 and C2. These combinations of key states go to block 8, where they form the control pulses of the OTP transistors to balance the voltages across capacitors C1 and C2.

Thus, the absence of combinations of key states during the formation of OTP control pulses that are not responsible for the voltage balance on the capacitors is a condition for increasing the voltage balance speed of the capacitors C1 and C2.

We show this by analyzing the electromagnetic processes in a single-phase three-level converter.

In the synthesis of the driving vector V * at the pulse-width modulation cycle within the first sector I (Fig. 2), we write in a general form the expressions for the voltages on the capacitors C1 and C2

, $$T_{10}^I$$

, $$T_{20}^I$$

- временные интервалы, относящиеся к комбинациям состояний ключей (2; 1), (1; 0) и (2; 0) на такте широтно-импульсной модуляции соответственно.where i _~ , Z is the current and the complex resistance of the AC link, X _C1 and X _C2 are the reactance of the capacitors, U _C10 , U _C20 are the initial average values of the voltages on the capacitors C1 and C2, respectively. $$T_{21}^I$$

, $$T_{10}^I$$

, $$T_{\mathrm{twenty}}^I$$

- time intervals related to combinations of key states (2; 1), (1; 0) and (2; 0) on the pulse-width modulation cycle, respectively.

The rate of change of voltage across the capacitors is defined as the sum of the voltage increments, referred to the time interval

where N is the sector number.

Define the voltage increment on the capacitors C1 and C2 in the first sector in the form

, $$T_{10}^I$$

- длительности подключения комбинаций состояний ключей, отвечающих за заряд и разряд конденсаторов. Соответственно, как видно из (4), на скорость баланса напряжений конденсаторов влияет величины $$T_{21}^I$$

, $$T_{10}^I$$

.The value of U _C10 - U _C20 reflects the difference in the initial values of the voltage across the capacitors. $$T_{21}^I$$

, $$T_{10}^I$$

- the duration of connecting combinations of key states responsible for the charge and discharge of capacitors. Accordingly, as can be seen from (4), the values of the capacitors $$T_{21}^I$$

, $$T_{10}^I$$

.

, увеличиться скорость изменения напряжений на конденсаторах, а следовательно, и скорость баланса.Accordingly, excluding from (4) $$T_{21}^I$$

, increase the rate of change of voltage across the capacitors, and hence the speed of balance.

The technical result is the creation of a method of balancing the voltage at the capacitors of a DC link of a single-phase three-level converter with fixing diodes during the implementation of vector pulse-width modulation, in which time intervals corresponding to combinations of key states that are not responsible for the voltage balance at the capacitors of a DC link are eliminated, which leads to increase the time intervals of combinations of key states affecting the voltage balance of capacitors and traces it is necessary to increase the speed of the voltage balance across the capacitors of the DC link.

Claims (1)

A method of balancing the voltages on the capacitors of a single-phase three-level converter with fixing diodes, which consists in the fact that at the pulse-width modulation cycle, key state combinations are selected that are responsible for the formation of the driving vector, control pulses are generated according to the selected key state combinations, the generated control pulses are fed to the transistor inputs single-phase three-level converter with locking diodes, characterized in that from the selected combinations of key states are used Luciano combinations which do not implement the stress balance of the capacitors.

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