RU2522036C2 - Method for control of three-phase voltage inverter with current stabilisation at transfer to overload mode - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: invention relates to the field of electric engineering and power electronics. A method for control of a three-phase voltage inverter with current stabilisation at transfer to overload mode consists in generation of two preset signals for two load voltage orthogonal projections, the preset signal of overload current is shaped, the reference bidirectional signal is shaped, control signals are generated in two orthogonal projections against the preset signals and feedback signals, the control signals in two orthogonal projections are converted into three modulating signals in the temporary area, pulses are generated for control of the voltage inverter gates when the modulating voltage exceeds the reference voltage, phase current instantaneous values are measured for the voltage inverter, an amplitude of the generalised vector for phase currents is calculated for the voltage inverter and when it reaches the preset value, the preset overload voltage signal is corrected so that current equal to the overload current preset signal is generated for the load. Thus, in the overload mode load current stabilisation is provided at the level defined by the setting. At that smooth transition is ensured from the normal mode to the current limiting mode and vice a versa, i.e. regulators all the time operate in a linear mode (they are not limited), and only the voltage preset signal changes.

EFFECT: provision of smooth transition from the normal mode to the current limiting mode and back.

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Description

The invention relates to the field of electrical engineering and power electronics, can be used in the construction of three-phase alternating current electric power generation systems or guaranteed alternating current power supply systems, in which a voltage inverter is used to reduce the mass and dimensions of the generation system, increase the operating life. The primary sources with unstable input energy parameters in such systems can be an industrial frequency network, a synchronous generator with a variable shaft speed or a battery. The function of ensuring quality indicators of the generated electric energy is assigned to the voltage inverter and the output power low-pass filter.

A known method of controlling a three-phase voltage inverter [S. Hiti, D. Boroyevich and C. Cuadros, "Small-signal modeling and control of three-phase PWM converters", Conference Record of the IEEE Industry Applications Society Annual Meeting, 1994, vol. 2, pp. 1143-1150, 2- 6 Oct. 1994], based on a closed bypass control system with subordinate regulation in a rotating orthogonal coordinate system. The external circuit in such a system monitors the voltage, the internal circuit monitors the current. Thus, the current reference signal is generated by the external circuit controller that monitors the voltage.

However, in this method, the magnitude of the generated current is determined only by the load. In a real system, it is necessary to limit the amount of current during overload so that the inverter keys do not fail.

In addition, a dynamic method for controlling the current limiting of a three-phase voltage inverter is known [Xunwei Yu and Zhenhua Jiang, "Dynamic Current Limiting Control of Voltage Source Inverters", IEEE International Electric Machines and Drives Conference, 2009. IEMDC '09, pp.1664-1668, 3-6 May 2009], which is the prototype of the invention, which consists of generating two reference signals for two orthogonal projections of the voltage across the load, generating a setpoint signal for the overload current, generating a bipolar reference signal, generating signals according to the reference signals and feedback signals management in two orthogonal projections, the projections of orthogonal transform signals control three simulating signal in the time domain, develop the valve control inverter voltage pulses in excess of simulating the stress over a reference voltage.

In this method, at the time when overload is detected, a restriction on the current reference signal is introduced. As a limitation of the reference signal for the projection current “d”, the value taken by the regulator of the voltage circuit of the projection “d” before overload is taken. As a limitation of the reference signal on the projection current “q”, a value is taken, which is calculated by the following formula:

$$I_{g.Limit}=\sqrt{I_{rms.Limit}^2-I_{d.Limit}^2}\left(\mathrm{one}\right)$$

where I _rms.Limit is the value of the setpoint of the effective current value in overload mode; I _d.Limit - restriction on setting the projection current “d”.

In this method, the effective current value is continuously measured, when it is less than the setting of the overload mode I _rms.Limit , the control system works as the first analogue. When switching to overload mode, restrictions on the current set signals are introduced, and as a result, the current is limited at the level of the set value I _rms.Limit , while the load voltage decreases.

The disadvantage of this control method is that at the time of overload, the projection current signal “q” changes abruptly, and if the load cosφ also changes, the control system will fluctuate between normal mode and current limiting mode. Switching between modes can bring the regulators out of a stable state and cause oscillation generation at the output of the control system, which will lead to a lack of stabilization of the inverter output parameters.

The objective of the invention is to ensure a smooth transition from normal to current limiting mode and vice versa.

The problem is achieved in that in the known method of controlling the voltage inverter, which consists in the fact that the dual-circuit slave control system generates control signals in a rotating orthogonal coordinate system for a PWM modulator; the projection voltage setting signal “q” is always zero, and the projection voltage setting signal “d” is equal to the required amplitude of the output voltage when the load current is less than the setting of the amplitude of the overload current, and is adjusted during overload so as to form the output current specified at bid.

Figure 1 presents a structural diagram that implements the proposed method of controlling a voltage inverter. It can be conditionally divided into a power circuit (block 18) and a control system (block 19). The power circuit contains a voltage inverter (block 20), the three outputs of the racks of which are connected to the inputs of the low-pass filter (block 21), and the outputs of the latter through current sensors (blocks 23, 24, 25) are connected to the load inputs (block 22). The outputs of the low-pass filter and information signals of current sensors (blocks 23, 24, 25) are connected to the inputs of the control system (block 19). The control system includes a control system block (block 26), the inputs and outputs of which are connected to coordinate transformer blocks (blocks 27, 28, 29), the three outputs of the coordinate transformer block (block 27) are connected to the inputs of the comparison circuits (blocks 31, 32 , 33), to the other inputs of which the output of the generator of the supporting bipolar sawtooth voltage is connected (block 30). The outputs of the comparison circuits are connected directly to the inputs of the first group of drivers (blocks 38, 40, 42) and through the logical elements “not” (blocks 34, 35, 36) to the inputs of the second group of drivers (blocks 37, 39, 41). The outputs of the first group of drivers (blocks 38, 40, 42) are connected to the gates of the upper transistors of the voltage inverter racks (block 20), and the outputs of the second group of drivers (blocks 37, 39, 41) are connected to the gates of the lower transistors of the voltage inverter racks (block 20) . Figure 2 presents the structural diagram of the regulation system. It can be divided into two parts. One part generates a projection control signal "q" for the PWM modulator (blocks 2, 8, 10, 12, 14), the other part generates a projection control signal "d" (other blocks). The circuit consists of a current loop controller (blocks 13, 14), a voltage loop controller (blocks 11, 12), subtraction circuits (blocks 7-10), generating error signals between the reference signals and feedback signals; a voltage source (block 2), forming a signal for setting the projection voltage “q”; a voltage source (block 1), forming a signal for setting the projection voltage “d” in the absence of overload; a voltage source (block 3) generating a signal for setting the overload current; block 4, performing the function of algebraic division; block 5, performing the function of algebraic multiplication; block 6, performing the function of switching the signal for setting the projection voltage “d”; blocks 15 and 16, calculating the root of the sum of the squares of two quantities; a comparison device (block 17) generating a logical “1” signal when the magnitude of the amplitude of the generalized load current vector exceeds the setting of the amplitude of the overload current, and generating a logical “0” signal otherwise.

Blocks of the circuit perform the following functions. Block 26 performs the function of regulating the output parameters of the voltage inverter, block 16 measures the amplitude of the generalized load current vector I _L.max.fdb according to the following formula:

$$I_{L.\max .fdb}=\sqrt{I_{L.d.fdb}^2+I_{L.q.fdb}^2}\left(2\right)$$

where I _Ldfdb is the projection "d" of the generalized load current vector; I _Lqfdb b - projection "q" of the generalized load current vector.

The projection “d” I _Ldfdb and the projection “q” I _{Ldfdb of the} generalized load current vector using the abc / dq coordinate transformation unit (block 29) are obtained from phase currents using the following formulas:

$$I_{L.d.fdb}=\frac{2}{3}\cdot \left(I_{LA}\cdot \cos \left(\omega \cdot t\right)+I_{LB}\cdot \cos \left(\omega \cdot t-\frac{2\cdot \pi }{3}\right)+I_{LC}\cdot \cos \left(\omega \cdot t+\frac{2\cdot \pi }{3}\right)\right)\left(3\right)$$

$$I_{L.q.fdb}=\frac{2}{3}\cdot \left(I_{LA}\cdot \sin \left(\omega \cdot t\right)+I_{LB}\cdot \sin \left(\omega \cdot t-\frac{2\cdot \pi }{3}\right)+I_{LC}\cdot \sin \left(\omega \cdot t+\frac{2\cdot \pi }{3}\right)\right)\left(\mathrm{four}\right)$$

where I _LA , I _LB , I _LC are the phase values of the load currents; ω is the cyclic frequency of the output voltage; t is time.

Similarly, block 15 measures the amplitude of the generalized load voltage vector U _L.max.fdb according to the following formula:

$$U_{L.\max .fdb}=\sqrt{U_{L.d.fdb}^2+U_{L.q.fdb}^2}\left(5\right)$$

where U _Ldfdb is the projection "d" of the generalized load voltage vector; U _Lqfdb is the projection "q" of the generalized load voltage vector.

The projection “d” U _Ldfdb and the projection “q” U _{Lqfdb of the} generalized load voltage vector using the coordinate transformation unit abc / dq (block 28) are obtained from phase voltages using the following formulas:

$$U_{L.d.fdb}=\frac{2}{3}\cdot \left(I_{LA}\cdot \cos \left(\omega \cdot t\right)+U_{LB}\cdot \cos \left(\omega \cdot t-\frac{2\cdot \pi }{3}\right)+U_{LC}\cdot \cos \left(\omega \cdot t+\frac{2\cdot \pi }{3}\right)\right)\left(6\right)$$

$$U_{L.q.fdb}=\frac{2}{3}\cdot \left(U_{LA}\cdot \sin \left(\omega \cdot t\right)+U_{LB}\cdot \sin \left(\omega \cdot t-\frac{2\cdot \pi }{3}\right)+U_{LC}\cdot \sin \left(\omega \cdot t+\frac{2\cdot \pi }{3}\right)\right)\left(7\right)$$

where U _LA , U _LB , U _LC are the phase values of the load voltages; ω is the cyclic frequency of the output voltage; t is time.

The “not” logic elements (blocks 34, 35, 36) are ordinary pulse (digital) signal level inverters. Blocks 37, 38, 39, 40, 41, 42 are drivers, amplify the signal by power, perform galvanic isolation between the electrical circuits of the control system and the power circuit of the voltage inverter (block 20). The voltage inverter can be performed on any controlled valves, as an example of the invention, a voltage inverter is shown on IGBT transistors VT1, VT2, VT3, VT4, VT5 and VT6. Blocks 23, 24 and 25 are current sensors, the signals from their output are proportional to the load currents of the inverter, and are fed to the input of block 29, which generates a voltage proportional to the amplitude of the generalized vector of three inverter currents. The load circuit can be performed with or without a neutral wire.

The proposed method is as follows: using block 16, the amplitude of the generalized load current vector I _{L.max.fdb is measured} , if this value is less than the setpoint set by block 3, then block 17 will give a logical “0” signal and switch 6 will be in state "0". In this case, the reference signal to the projection voltage circuit “d” will be set by block 1, and the whole system will work as the first analogue.

If the magnitude of the amplitude of the generalized vector of the load current I _{L.max.fdb is} greater than the setting specified by block 3, then block 17 will give a logical signal “1” and switch 6 will be in state “1”. Using blocks 4, 15 and 16, the load resistance module is calculated according to Ohm's law:

$$|\; |\; |Z_L|\; |\; |=\frac{U_{L.\max .fdb}}{I_{L.\max .fdb}}\left(8\right)$$

Then, using blocks 3 and 5, such a reference signal is generated on the projection voltage circuit “d” to form the load current specified by the set point (block 3). The reference signal to the projection voltage circuit "d" is determined by Ohm's law:

$$U_{L.d.ref}=I_{L.\max .ref}\cdot |\; |\; |Z_L|\; |\; |\left(9\right)$$

Thus, in the overload mode, the load current is stabilized at the level determined by the set point (block 3).

At the output of blocks 7 and 8, signals are formed equal to the difference between the reference signal and the feedback signal of the load voltage. These signals are supplied to voltage regulators (blocks 11 and 12), which form such a reference signal for the current of the corresponding projection so that the difference signal at the output of blocks 7 and 8 is zero, i.e. so that the load voltage is equal to the voltage reference signal.

Further, at the output of blocks 9 and 10, signals are formed equal to the difference between the reference signal and the feedback signal of the load current. These signals are fed to current controllers (blocks 13 and 14), which form such a control signal of the corresponding projection so that the difference signal at the output of blocks 9 and 10 is zero, i.e. so that the load current is equal to the current reference signal. The control signals are input to the coordinate transformation block dq / abc (block 27), which generates three modeling signals according to the following formulas:

$$U_{A.ref}=U_{d.ref}\cdot \cos \left(\omega \cdot t\right)+U_{q.ref}\cdot \sin \left(\omega \cdot t\right)\left(10\right)$$

$$U_{A.ref}=U_{d.ref}\cdot \cos \left(\omega \cdot t-\frac{2\cdot \pi }{3}\right)+U_{q.ref}\cdot \sin \left(\omega \cdot t-\frac{2\cdot \pi }{3}\right)\left(\mathrm{eleven}\right)$$

$$U_{A.ref}=U_{d.ref}\cdot \cos \left(\omega \cdot t+\frac{2\cdot \pi }{3}\right)+U_{q.ref}\cdot \sin \left(\omega \cdot t+\frac{2\cdot \pi }{3}\right)\left(12\right)$$

Three modeling signals and a reference signal (from the output of block 30) are supplied to comparators (blocks 31, 32, and 33), which generate pulses when the modeling voltages exceed the reference voltage. These pulses are fed to the logical elements “not” (blocks 34, 35, 36) and the drivers (blocks 38, 40, 42) of the upper transistors (VT1, VT3, VT5) of the voltage inverter (block 20). The voltages from the outputs of the logic elements are not applied to the drivers (blocks 37, 39, 41) of the lower transistors (VT2, VT4, VT6) of the voltage inverter (block 20). The output voltage of the inverter is removed from the midpoints of the racks A, B, C and fed to the input of the power low-pass filter (block 21). A low-pass filter suppresses high-frequency harmonics, an almost sinusoidal three-phase voltage with a frequency applied to the load (block 22).

Thus, using this control method, the external characteristic shown in FIG. 3 is realized. This ensures a smooth transition from the normal mode to the current limiting mode and vice versa, because regulators work in linear mode all the time (not limited to), and only the voltage reference signal changes.

Claims (1)

A method of controlling a three-phase voltage inverter with current stabilization during transition in overload conditions, which consists in generating two reference signals to two orthogonal projections of the voltage on the load, generating a setpoint signal for the overload current, generating a bipolar reference signal, and generating it according to the reference signals and reverse signals communications control signals in two orthogonal projections, convert control signals of orthogonal projections into three modeling signals in the time domain, generate imp The control signals of the voltage inverter valves when the modeling voltage exceeds the reference voltage, characterized in that the instantaneous values of the phase currents of the voltage inverter are measured, the amplitude value of the generalized vector of the phase currents of the voltage inverter is calculated, and when it reaches the specified value, the voltage reference signal is adjusted so that load current equal to the setpoint signal for overload current.

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