RU2565526C1 - Phase-locked loop device - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: phase-locked loop device comprises a sign-module logic phase discriminator, a controlled generator, three voltage adders, an integrator, a proportional link, two voltage formers, two nulled integrators and a frequency divider.

EFFECT: high stability which defines the frequency lock-in band, while maintaining high accuracy of phase locking.

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Description

The invention is intended to stabilize the parameters of oscillators used in radio engineering and measuring devices.

Known devices (systems) phase-locked loop (PLL) [1-3], providing high accuracy of synchronization, manifested in the high stability of the useful oscillations generated on the basis of the reference oscillation. PLL systems with filtering chains of an astatic type [1] realize phase synchronization of the generated oscillation relative to the reference one with an accuracy determined by the parameters of the phase detector (discriminator).

The use of digital type phase discriminators (logical phase discriminators) [4, 5, 7] as part of PLL systems [4, 5, 7] allows tuning the generated oscillation relative to the reference oscillation with a phase difference Δφ → 0. This is confirmed by calculations published in [9, 10].

The highest synchronization accuracy with sufficient stability of the structure is ensured in the PLL astatic system [6]. In it, to increase stability, a stress generation block is used, which contains a set of nullable integrators with positive feedbacks that make it possible to implement the nonlinear law of formation of control voltages. The specified PLL system is selected as a prototype.

The use of such a structure in the case when the sign of the phase difference during the frequency adjustment process changes with a period significantly exceeding the period of the frequency of the reference oscillation makes it possible to obtain a high level voltage at the output of the driver. This voltage, acting on a controlled (adjustable) generator, contributes to the intensification of the capture process in the system. At the same time, when the phase difference is in the range near zero, the sign of the phase difference at the output of the phase discriminator is changed periodically with a period of reference oscillation. Over the specified time, the voltage at the output of the voltage driver increases slightly. The latter reduces the intensity of the impact on the controlled generator and, accordingly, reduces the level of fluctuation of the phase difference in the synchronization mode.

The disadvantage of the prototype is that the desire to reduce the level of fluctuation of the phase difference in the steady state leads to a decrease in its stability, which is manifested in a decrease in the capture band of the system. This is illustrated by the analytical calculations presented in [8]. It is shown here that, while ensuring a steady-state phase error (fluctuations in the phase difference in the steady-state PLL operation) Δφ _min = 2.3π · 10 ^-4 , in the automatic frequency control system with respect to the time constants T _{p of the} forward and reverse T _o of null integrators equal to 1000, a capture bandwidth of Ω _z ≤0.1Ω _{y is} provided, where Ω _y is the PLL system holding band. Such a capture band is insufficient.

The expansion of the capture band is possible due to the introduction of a familiar phase modifier phase discriminator into the PLL control loop [5, 7] and the formation of an additional frequency adjustment channel using information generated on the modular (proportional) discriminator outputs.

The aim of the invention is to increase stability while maintaining high accuracy of phase synchronization. This goal is achieved by improving the invention according to copyright certificate No. 1415441 [6]. The essence of the invention consists in replacing the logical phase discriminator of the sign type used in the prototype, the logical discriminator of the familiar type (application No. 2013157154/08 (089096) dated 12/23/2013, a positive decision on the grant of a patent dated 10.27.2014), in which Separate operation of iconic and modular outputs is provided, and the introduction of an additional frequency adjustment channel containing additional voltage former, voltage combiner and frequency divider into the prototype structure.

Consider the structure and principle of operation of the proposed device. In FIG. 1 shows a structural diagram of the proposed PLL device, and in FIG. 2 is a timing diagram explaining its operation.

The PLL device shown in FIG. 1, contains a familiar module logic phase discriminator (ZMLFD) 1, a controlled generator 2, a first voltage adder 3, an integrator 4, a proportional link 5, a first voltage shaper 6, nullable integrators 7 and 8, a second adder 9, a second voltage shaper 10, and a third adder voltage 11 and the frequency divider 12.

The proposed PLL device operates as follows. The first input of the ZMLFD 1 receives the voltage of the reference oscillation U _op , which has digital logic levels, and the second input of it, the voltage U _{pr of an} adjustable oscillation obtained based on the output oscillation of a controlled generator (UG) 2, by dividing its frequency using a frequency divider 12 The inclusion of a frequency divider in the PLL structure is due to the fact that the familiar module logic discriminator provides its properties when the frequencies it compares have close values. When the frequency generated by the UG is a multiple of the reference f _y = nf _op , where n is the multiplicity factor, for their equalization between the UG output and the input of the ZMFD it is necessary to include a frequency divider with a division coefficient n. When the compared frequencies are close, there is no need to use a frequency divider in the structure.

, первый формирователь напряжения 6 вырабатывает отрицательное напряжение, которое интегрируется интегратором 7 (интегратор 8 в это время поддерживается в обнуленном состоянии сигналом $$U_z^{-}=1$$

). Кода знак разности фаз отрицателен $$(U_z^{+}=\mathrm{1,}{U}_z^{-}=0)$$

формирователь 6 вырабатывает положительное напряжение, при этом работает интегратор 8, а интегратор 7 обнулен. Суммируемые вторым сумматором 9 напряжения по цепям обратных связей подаются на вторые входы обнуляемых интеграторов 7 и 8. Поскольку связи со стороны сумматора 9 являются положительными, это обеспечивает на выходе интеграторов, и, следовательно, на выходе сумматора 9, формирование напряжения, изменяющегося по закону экспоненты.Significant outputs of the discriminator control the first voltage driver 6 and zeroing of the integrators 7 and 8. The resettable integrators 7 and 8 operate as follows. When the sign of the phase difference of the oscillator discriminated by the discriminator is positive $$(U_z^{+}=0U_z^{-}=\mathrm{one})$$

, the first voltage driver 6 generates a negative voltage, which is integrated by the integrator 7 (the integrator 8 is maintained at this time by a signal zeroed $$U_z^{-}=\mathrm{one}$$

) Code the sign of the phase difference is negative $$(U_z^{+}=\mathrm{one,}{U}_z^{-}=0)$$

the shaper 6 generates a positive voltage, while the integrator 8 is working, and the integrator 7 is reset. The voltages summed by the second adder 9 through the feedback circuits are fed to the second inputs of the resettable integrators 7 and 8. Since the connections from the adder 9 are positive, this ensures that the output of the integrators, and therefore the output of the adder 9, generates a voltage that varies according to the law of the exponent .

In the case when the lifetime of the phase difference of the same sign is significant (takes place in the phase capture mode), the output of the adder 9 can reach significant values. At the same time, with a frequent change in the phase difference (takes place in the beating mode and the synchronism mode) analyzed by the oscillator, due to the reset of the voltage of the resettable integrators, the voltage at the output of the adder 9 changes insignificantly.

In the logical device of the familiar module type used in the proposed device, the simultaneous operation of symbolic and modular outputs is prohibited. So in beat and capture modes due to the fact that the phase difference of the analyzed oscillations is significant, the operation of only modular (proportional) discriminator outputs is allowed. If the phase difference is reduced to the values determined by the deadband of the modular channel of the discriminator, the operation of the modular outputs is prohibited, and the operation of the iconic outputs is allowed. An insignificant change in the phase difference provided by the auto-tuning ring is realized in the synchronism mode and is provided by the action of the signals generated by the discriminating sign outputs of the discriminator on the controlled generator.

на модульных выходах дискриминатора. Причем длительности импульсных сигналов, формируемых на пропорциональных выходах дискриминатора, уменьшены на величину, определяемую зоной нечувствительности Δt_зн модульного канала ЗМЛФД. Напряжения с выходов второго сумматора 9 и второго формирователя 10 суммируются третьим сумматором напряжений 11 и подаются на входы пропорционального звена 5 и интегратора 4.The voltages generated at the modular outputs of the discriminator carry information about the magnitude of the phase difference between the analyzed oscillations. Under their influence, in the second voltage driver 10, pulse voltages of different signs are created, the duration of which is determined by the durations of the pulse signals $$U_m^{+},U_m^{-}$$

on modular discriminator outputs. Moreover, the duration of the pulse signals generated at the proportional outputs of the discriminator is reduced by an amount determined by the deadband Δt _{zn of the} modular channel ZMLFD. The voltages from the outputs of the second adder 9 and the second driver 10 are summed by the third voltage adder 11 and fed to the inputs of the proportional link 5 and integrator 4.

To ensure a wide capture band, the impact from the side of the shaper 10 is made more intense than from the side of the second adder 9. This is ensured by the fact that the level of the amplitudes of the voltages at the output of the shaper 10 is set larger than the amplitude of the voltages at the output of the shaper 6.

The voltage supplied to the control input of UG 2 from the side of the first adder 3, formed by summing the voltages of the integrator 4 and the proportional link 5, causes a change in the frequency of the tuned oscillation. The astatic link, consisting of integrator 4 and proportional link 5, provides the PLL phase astatism, which contributes to the complete development of the phase error.

Since in the capture mode a significant influence on the frequency adjustment process is exerted by the control loop based on the use of signals from the discriminator modular outputs, and the influence of the frequency adjustment ring using signals from the discriminator sign outputs is insignificant, in this operating mode the proposed system is likened to an autonomous PLL with first-order filter made in the form of an astatic link. In [1, p. 179] it is shown that in such a PLL system a capture band equal to the confinement band is provided.

The inclusion in the control loop of the frequency divider 12 can lead to the appearance of an additional static phase shift between the reference and adjustable oscillations. However, the use of synchronous frequency divider circuits can reduce this shift. Moreover, the shift will be stable and have a value, in temporary terms, determined by the switching speed of one counter trigger. When using modern logic circuits, the magnitude of this shift in time expression may not exceed units of nanoseconds. To avoid the delay arising while using the tunable and reference oscillations, in order to exclude a static phase shift, the reference oscillation signal supplied to the input of the proposed device should be passed through an additional logic circuit (for example, through a chain of series-connected logic gates) before using it in other circuits ) It is only necessary to choose the type of logic gates having a delay equal to the switch trigger time of the counter.

When the frequencies of the reference and adjustable oscillations are close (the multiplicity factor is 1), the need for a frequency divider disappears and no constant phase error occurs between the reference and adjustable oscillations.

Voltage diagrams shown in figure 2, reflect the processes existing in the proposed device. The interval t ₀ -t ₁ illustrates the behavior of the proposed device in the beating mode. Moreover, cases where the phase difference between the reference U _op and the tunable U _pr oscillation is located outside the dead band of the modular channel ZMLFD (at this time, the control voltage U _f2 is formed only at the output of the second voltage _driver (U _f1 = 0, U _f2 ≠ 0)) and the dead band (at this time the control voltage U _c2 is formed only at the output of the second adder (U _F1 ≠ 0, U _Q2 = 0)), the scope of which is defined as 2Δt _receptacle (| -Δt _receptacle | = | + Δt _char |). The voltages generated at the output of the second voltage driver have a duration determined by the signals at the modular outputs of the logical discriminator. Their duration in comparison with the real delays of the fronts of the analyzed oscillations U _op and U _ol reduced by Δt _characters . The latter is determined by the logic of the operation of ZMLFD.

The interval t ₁ -t ₂ illustrates the behavior of the proposed device in the phase capture mode. In this case, the phase difference is outside the dead zone of the modular discriminator channel. In this case, control is provided only by the effects of U _f2 from the side of the second voltage driver.

The interval from t ₂ and further illustrates the behavior of the proposed device in the mode of phase retention, when the phase difference does not exceed the value of the dead zone of the modular channel ZMLFD. Only the tuning channel works here, controlled by the discriminator's sign outputs. If the phase difference is significant, then its development is carried out for several periods of the reference oscillation (in the interval t ₂ -t ₃ ). In this case, the voltage U _c2 at the output of the second adder varies significantly, which helps to keep the phase difference within the dead band and increase the efficiency of its development. After t _{3, the} case where the phase difference varies periodically with the period of the reference oscillation is illustrated. In this case, the effect on the frequency adjustment process from the side of the second voltage adder is negligible. This provides a small fluctuation of the phase difference in the steady state operation of the proposed device.

The tuning process is also illustrated by the behavior of voltage U _and at the output of the integrator of the astatic link.

BIBLIOGRAPHIC LIST

1. Phase synchronization systems with elements of discrimination. 2nd ed., Ext. and reslave. / V.V. Shahgildyan, A.A. Lyakhovkin, V.L. Koryakin et al .; under the editorship of V.V. Shahgildyan. - M .: Radio and communications, 1989 .-- 320 p.

2. The principles of phase synchronization in measurement technology. - Tomsk: Radio and Communications, 1989 .-- 384 p.

3. Digital phase synchronization systems / Ed. M.I. Zhodzishsky. - M .: Owls. Radio, 1980 .-- 208 p.

4. A.S. 1248026 USSR, MKI H03D 13/00, G01R 25/00. Phase discriminator / V.F. Lonely. No. 3669946 / 24-09; claimed 11/25/83; publ. 07/30/86 in BI No. 28.

5. A.s. 1432724 USSR, MKI H03D 13/00, G01R 25/00. Phase discriminator / V.F. Odinokov, S.I. Slaves. No. 4212180 / 24-09; claimed March 19, 87; publ. 10.23.88 in BI No. 39.

6. A.S. 1415441 USSR, MKI H03L 7/00. Device phase-locked loop / V.F. Odinokov, S.I. Kholopov, M.V. Petrov. No. 4162161 / 24-09; Declared 12/11/86; publ. 08/07/88. Bull. No. 29.

7. A.S. 1568207 USSR, MKI H03D 13/00. Phase discriminator / V.F. Odinokov, S.I. Slaves. No. 4,374,505; claimed 05.02.88; publ. 05/30/90 in BI No. 20.

8. Kholopov S.I. Extension of the capture band of the relay astatic phase synchronization system // Bulletin of the Ryazan State Radio Engineering University. 2013. No3 (issue 45). S. 49-53.

9. Kholopov S.I., Odinokov V.F. Zero shift of the discriminatory characteristic of a logical phase discriminator // Deposited manuscripts. No. 1135-sv 87. VINITI, 1987. No. 12.

10. Kholopov S.I. Analysis of the PLL relay system with resettable integrators // Bulletin of RGRTU. 2011. No4 (issue 38). - S. 50-54.

Claims (1)

A phase locked loop device containing a controlled generator, the output of which is the output of the device, and the input is connected to the output of the first voltage adder, the inputs of which are connected to the outputs of the proportional link and integrator, the inputs of the proportional link and integrator are combined; a voltage shaper having two separate inputs, the first of which is connected to the reset input of the first nullable integrator, and the second input is connected to the zero input of the second nullable integrator, the combined first inputs of the nullable integrators are connected to the output of the voltage shaper, the outputs of the first and second nullable integrators are separately connected to the inputs of the second voltage adder, the output of which is connected to the second inputs of the resettable integrators, characterized in that a familiar module logic is introduced into it a phase discriminator with a deadband through a modular channel, the first input of which is the input of the device, and the second input is connected to the output of the controlled oscillator through an additionally introduced frequency divider, the discriminator's significant outputs are separately connected to the shaper inputs, an additional voltage shaper is introduced, the inputs of which are separately connected to the modular outputs of the discriminator, the output of the additional driver is connected to the first input of the additional voltage adder, the second input of which is connected to the output of the second voltage adder, and the output of the additional adder is connected to the combined inputs of the integrator and the proportional link.

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