RU2261528C1 - Network-synchronization pulse phase jitter compensator - Google Patents

Abstract

FIELD: network clock synchronization engineering.

SUBSTANCE: proposed pulse phase jitter compensator is built around PLL and has newly introduced internal pulse modulator, phase inverter, and delay line affording complete compensation for sync pulse phase jitter in network clock synchronization.

EFFECT: minimized effectiveness of network clock synchronization.

1 cl, 1 dwg

Description

The invention relates to the field of network clock synchronization (TSS), and more specifically to compensation for the phase wander of the network synchronization pulses (jitter).

Jitter is the asynchronism of TSS clock pulses, which sharply reduces its effectiveness. It can be considered as modulation in time (phase) of periodic clock pulses with equivalent jitter interference. This is spurious time-pulse (VIM) or phase-pulse (PIM) modulation. Therefore, to reduce jitter, the phase-locked loop (PLL) of a pulsed oscillator is often used according to the input signal from the VIM (PIM), which is noted in the sources [1,2,3]. From the theory and practice of FAP, it is known that the oscillations of a pulsed oscillator, which is tuned in its FAP loop, repeat the input modulated signal, but with a lower modulation depth of the corresponding parameter (in this case, the temporal shift of pulses). This means that such oscillations have less jitter compared to the input pulse signal. In [1], PLL is called PLL, ie phase-locked loop, and in [2] - a temporary auto-selector, because it uses a time discriminator instead of a phase detector. But also in [1], a trigger is used as a phase detector. In [3], general issues of TSS are considered.

For the prototype of the invention, the device described in the first source [1] was selected as the closest to it in technical essence.

The prototype consists of a series-connected amplitude limiter, a temporary discriminator, a low-pass filter (LPF), a pulse phase-controlled oscillator (VCO), the output of which, which is the output of the prototype, is connected to the second (reference) input of the temporary discriminator. The VCO is covered by the loop of the phase-to-phase converter, including the above blocks, and at its output, the oscillations repeat the input modulated signal, but with less jitter.

The main disadvantage of the prototype is the lack of elimination of the wandering phase of the clock (jitter), which does not allow to have the maximum efficiency of the TSS.

The technical result of the claimed object is to ensure maximum efficiency of the TSS due to the complete elimination of jitter.

The essence of the invention lies in the fact that in the prototype, consisting of a series-connected amplitude limiter, time discriminator, low-pass filter, VCO, the output of which is connected to the second input of the temporary discriminator, an additional phase inverter (analog) with adjustable transmission coefficient, time-pulse modulator, delay line, moreover, the modulator with its low-frequency input is connected to the output of the low-pass filter through the input phase inverter, and the high-frequency input is connected to the output of the amplitude limiter through the input line delays. The output of the modulator is the output of the invention.

A significant difference of the invention are the introduced elements and their relationships, because only they can completely eliminate jitter and thereby increase the efficiency of TSS to the maximum.

The invention is illustrated in the drawing.

The drawing shows a structural diagram of the compensator. The compensator consists of an amplitude limiter 1, a temporary discriminator 2, a pulse oscillator controlled by phase voltage (VCO) 3, low-pass filter 4, a delay line 5, a phase inverter 6 with an adjustable transmission coefficient, a pulse-time modulator 7. Blocks 2,3,4 form synchronously PLL-based phase demodulator (SFD). The demodulator works at discrete points in time, because VCO - pulse adjustable oscillator. Entered elements are outlined with a dashed line.

The work of the entire compensator is as follows.

Input non-periodic pulses with VIM are limited in amplitude in block 1 to eliminate spurious amplitude modulation, as a result of which VIM oscillation with a constant amplitude takes place at its output

where f (t) is the normalized function characterizing the shape of the pulse:

T _p - the pulse repetition period,

Δτ _m is the maximum shift of the pulse relative to the clock point,

b (t) is the normalized modulating function equivalent to jitter.

VIM - oscillation u ₁ (t) is detected in a synchronous-phase demodulator (SFD), consisting of blocks 2,3,4, as a result of which at the output of the low-pass filter 4 there is a modulating analog signal u _f (t) = U _m b (t ) equivalent to jitter. In block 6, this signal changes its sign to the opposite and amplifies in level, after which it enters the low-frequency input of the VIM7 modulator. The signal u ₁ (t) is supplied to the high-frequency input of block 7 from the output of block 1 through the delay line 5. Block 5 equalizes the time shifts of the input signals. At the output of block 7, there is oscillation

where Δτm = kUm,

those. fully periodic synchronization pulses. This means that jitter is completely ruled out.

Since the oscillations at the output of the VCO repeat the input signal u _in (t), but with a smaller jigger, it is possible to connect the input of block 5 not to the output of block 1, but to the output of block 3, which will facilitate jitter compensation.

The technical and economic effect of the invention is to obtain the maximum possible efficiency of TSS due to the complete exclusion of jitter.

Sources of information

1. Breni S. Synchronization of digital communication networks / Translation from English. Ed. A.V. Ryzhkova. - M.: Mir, 2003 .-- C.111-113.

2. Pervachev S.V. Radio Automation. - M.: Radio and Communications, 1982.

3. Shmytinsky V.V., Korkhova V.I. The principles of building clock network synchronization in digital communication networks // Automation, Communications, Informatics. - 2000, 1, - S. 38-41.

Claims (1)

The phase wander of a network synchronization pulse, consisting of a series-connected amplitude limiter, a temporary discriminator, a low-pass filter, a phase-controlled pulse oscillator, the output of which is connected to the second (reference) input of the temporary discriminator, characterized in that it is additionally equipped with an analog phase inverter, time-pulse modulator, delay line, and the low-frequency input of the modulator is connected to the output of the low-pass filter through the phase inverter , and its high-frequency input - to the output of the amplitude limiter through the delay line, the output of the modulator is the output of the entire compensator.