RU2562796C1 - Radio receiving device with continuous automatic adjustment of susceptibility - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: device includes a blanking unit of pulse interference (1), N band-pass filters (8.1-8.N), two adders (9, 16), analogue-to-digital converter (10), two memory units (12, 15), delay unit (18), two multiplier units (13, 19), fast Fourier transformation unit (14), inverse value calculation unit (17), narrow-band interference blanking unit (20); correlation device (21), reference signal shaping unit (22), threshold unit (23) and amplification adjustment unit (2) including controlled attenuator (3), amplitude detector (4), two comparators (5, 6), counter (7) and delay unit (11).

EFFECT: reducing probable non-reception of a signal under conditions of action on a radio receiving device of blanking interference with a dynamically changing level.

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Description

The invention relates to techniques for receiving and processing radio signals and can be used to create promising radio facilities with programmable architecture with digital signal processing under the influence of blocking signals with a dynamically changing level and a priori uncertainty of parameters to ensure stable radio communication in a complex jamming environment.

Such receivers are described, for example, in the books “Undersampling techniques simplify digital radio”. Electronic Design, Vol. 39, May 23, 1991, No. 10, pp. 67, 68, 70, 73-75, 78 authors Richard Groshong and Stephen Ruscar, and Software denned radio: enabling technologies, John Wiley & Sons, Chichester, UK, 2002. - p.p. 440 by W. Tuttlebee, Ed.

The essence of such devices is to maintain the maximum possible signal level at the input of the analog-to-digital converter (ADC), which does not lead to limitation by redistributing the amplification of the analog-to-digital path (ADC) between the analog and digital domains while keeping the overall transmission coefficient unchanged. In existing analogs, the process of automatic susceptibility control (ARV) is implemented in blocks, due to the need to accumulate a signal sample buffer to calculate the fast Fourier transform (FFT), which can lead to signal distortion due to ADC overflow under the influence of blocking signals with a dynamically changing level.

Closest to the claimed is the device described in the copyright certificate No. 1637026. Device for correlation processing of broadband signals. - Poppy V.A., Katkova T.P. MKI Н04В 1/10, H04L 7/02 - 4 s. Registration 08/23/1988 - Publ. 03/23/91, Bull. No. 11, taken as a prototype [1].

In FIG. 1 shows a functional diagram of a prototype device; in FIG. 2 is a functional block diagram of the gain control, where indicated:

1 - block blanking pulse interference (BIL);

2.1-2.N - from the first to the Nth gain control unit (RU);

3 - controlled attenuator;

4 - amplitude detector;

5 - the first comparator;

6 - second comparator;

7 - counter;

8.1-8.N - from the first to the N-th band filters;

9 - the first adder;

10 - analog-to-digital Converter (ADC);

14 - block fast Fourier transform (FFT);

15 - memory block;

16 - second adder;

17 - block calculating the reciprocal of the value (BOB);

18 - block delay;

19 - block multiplication;

20 - block blanking narrowband interference (BUP);

21 - correlator;

22 - block forming a reference signal (FOS);

23 - threshold block;

24.1-24.N - from the first to the Nth multiplier.

The prototype device contains a unit BIL 1, the input of which is the input of the device, and the output of which is connected to the inputs of N bandpass filters 8.1 ... 8.N, the outputs of which are connected to the corresponding inputs of N identical units of RU 2.1 ... 2.N. The input of each of the RU 2.1 ... 2.N blocks is connected to the signal input of the controlled attenuator 3, the output of which is the first output of the RU block and connected to the corresponding input of the first adder 9, and also connected to the input of the amplitude detector 4, the outputs of which are connected to the corresponding inputs of the first 5 and the second 6 comparators, the outputs of which are connected to the corresponding inputs of the counter 7, the clock input of which is the clock input of the RU 2 unit, and the output of the counter 7 is connected to the control input of the controlled attenuator 3 and is in the second output of the RU 2.1 ... 2.N block, which is connected to the input of the corresponding multiplier 24.1 ... 24.N. The first adder 9 is connected in series with the ADC 10 and the FFT unit 14, the group of outputs of which is connected to the first group of inputs of the multiplication unit 19. A memory block 15 having N groups of outputs is connected to the input groups of the corresponding multipliers 24.1 ... 24.N, the output groups of which are connected with the corresponding N input groups of the second adder 16, which is connected in series with the BOB unit 17 and the delay unit 18. The output group of the delay unit 18 is connected to the second input group of the multiplication unit 19, which is connected in series with the PCU 20, and the a relator 21, the second group of inputs of which is connected to the group of outputs of the FOS block 22. The correlator 21 is connected in series with the threshold block 23, the output of which is the information output of the radio receiver.

In blocks 10, 14-23 there are also standard clock inputs, to which signals are supplied that ensure synchronization of the operation of the device as a whole.

The prototype device operates as follows. The input RF signal, which is an additive mixture of the signal, fluctuation, pulsed and concentrated noise, is fed to the input of the radio receiver and passes through the block 1 BIP and simultaneously arrives at N bandpass filters 8.1-8.N, which divide the frequency range of the input signal into N subbands . The signal from the output of the bandpass filters is fed to the inputs of the N blocks of RU 2.1-2.N (Fig. 2).

The transfer coefficient of each RU unit is determined by a digital code coming from the counter 7 output to the control input of the controlled attenuator 3. From the output of the controlled attenuator 3, the signal is sequentially fed to the amplitude detector 4, to two comparators 5 and 6, which compare the value of the input signal with the preset maximum and minimum values. If the amplitude of the output signal of the amplitude detector 4 is higher than the maximum value, then a signal is received from the output of the first comparator 5 to the first enable input of the counter 7, allowing the reduction of the transmission coefficient until the output signal becomes less than the set value. If the amplitude of the output signal of the detector 4 is lower than the minimum value, then from the output of the second comparator 6, a signal is received at the second enable input of the counter 7, allowing the transmission coefficient to increase until the output signal becomes higher than the set minimum value. In this case, the clock input of the counter 7 receives clock pulses (TI1).

The RU 2.1-2.N blocks set the amplification factors so that the voltage at their outputs is within predetermined, predetermined limits, the same for all RU blocks. Control signals that determine the values of the steady-state gain are fed to the first inputs of the corresponding multiplication units 24.1-24.N.

The output signals of the RU 2.1-2.N blocks are fed to the corresponding inputs of the first adder 9. The result of the summation through the ADC 10 is fed to the input of the FFT block 14, in which the signal samples are converted from time to frequency domain.

The output of the FFT block 14 is a group of values of the spectral components of the signal, arriving in parallel to the first group of inputs of the multiplication block 19. In block 19 of the multiplication, the values of the spectral components are multiplied by the corresponding samples of the inverse complex transfer coefficient of the bandpass filters 8.1-8.N, taking into account the gain in the RU 2.1-2.N blocks. The number of samples of the inverse complex transfer coefficient coincides with the number of spectral components at the output of the FFT unit 14. The formation of samples of the inverse total transfer coefficient of bandpass filters and switchgear blocks is as follows.

In block 15 of the memory are samples of the complex transfer coefficient of each of the N bandpass filters, which are simultaneously fed to the second inputs of the respective blocks 24.1-24.N multipliers, where the samples of the transmission coefficients of each filter are multiplied by the corresponding gain in the RU unit. The samples from the output groups of the multiplication units 24.1-24.N are sent to the corresponding input groups of the second summing unit 16, in which the corresponding samples of the transmission coefficients of the various band-pass filters are simultaneously added.

In block 17 BOB, samples of the inverse total transfer coefficient of bandpass filters 8.1-8.N are formed taking into account the gain factors in RU 2.1-2.N blocks. The samples of the inverse total transmission coefficient through the delay unit 18 are supplied to the second group of inputs of the multiplication unit 19.

The signal reconstructed in this way is fed to the input of the ECU unit 20, where the spectral components of this interference are suppressed. The signal from the output of the PCU block 20 is supplied to the first group of inputs of the correlator 21, the second group of inputs of which receives the signal from the output of the FOS block 22.

The correlator 21 is a series connection of a multiplication block similar to block 19 and an inverse fast Fourier transform block, implemented similarly to the FFT block 14.

In the correlator 21, the cross-correlation function of the reference signal and the signal from the output of the PCU block is determined. Samples from the correlator output go to threshold block 23. Exceeding the threshold means signal detection. Information about the detection of the signal is fed to the output of the radio receiver.

The problem of providing reception under difficult interference conditions at various levels of the input signal is especially acute in receivers with digital processing [2].

The disadvantage of the prototype device is the need to buffer the signal samples for calculating the FFT, so that the frequency f _{1 of the} clock signal TI1, which the gain control blocks 2.1-2.N and the multiplication block 19 are clocked at, should be less than L times (where L is the number of buffering samples ) than the main clock frequency f of the _main ADC block 10, which can lead to signal distortion due to ADC overflow under the influence of blocking signals with a dynamically changing level.

The objective of the invention is the implementation of a continuous, in-line ARV process without buffering, with a single clock signal of frequency f _main for the gain control unit and the ADC, to prevent the ADC from overflowing with interference with a rapidly changing level while maintaining all the positive properties of the prototype device.

Achievable technical result - reducing the possibility of distortion of the received signal by blocking noise with a dynamically changing level and a priori uncertainty of the parameters.

To solve this problem, a radio receiving device containing a pulse interference blanking unit (BIL), the input of which is the device input, N bandpass filters, gain control unit (RU), the first memory unit, the first adder and the analog-to-digital converter (ADC) are connected in series , which is clocked by a clock signal with a frequency f _DOS ; a series-connected block of fast Fourier transform (FFT), the first block of multiplication, block blanking narrowband interference (BUP), a correlator and a threshold block, the output of which is the information output of the device; connected in series to a second adder, a reciprocal-calculating unit (BOB) and a first delay unit, the output group of which is connected to a second group of inputs of the first multiplication unit, a reference signal generating unit (FOS), the output group of which is connected to a second group of correlator inputs, the RU unit contains a controlled attenuator (UA), the output of which, which is the first output of the RU unit, is connected to the input of the amplitude detector, the outputs of which are connected to the inputs of the corresponding first and second comparators, output rows are connected to respective inputs of a counter whose output is connected to the control input of the V, and the clock input of the counter is a clock input of the EN block; wherein the first memory block, the second adder, the BOB unit, the first delay unit, the first multiplication unit, the ECU unit, the correlator, the FOS unit and the threshold unit are clocked with a frequency signal f ₁ = f _main / L, where L is the number of buffering samples, according to the invention, a second memory unit and a second multiplication unit are introduced, and a second delay unit is added to the RU unit, the input of which is connected to the counter output, the clock input of the second delay unit is connected to the clock input of the counter, and the output of the second delay unit is the second output m RC unit and connected to a control input of the second memory unit, whose output is connected to a second input of the second multiplier having an input connected to the output of ADC, and second multiplier output connected to an input of an FFT unit; the output of the BIL unit is connected to the input of the RU unit, the first output of which is connected to the combined inputs of N bandpass filters, the outputs of which are connected respectively to the N inputs of the first adder; N groups of outputs of the first memory block are connected respectively to N groups of inputs of the second adder; wherein the RU unit, the second memory unit, the second multiplication unit and the FFT unit are clocked with a clock signal with a frequency of f _main .

This allows continuous ARV without preliminary buffering by using the same clock signal for the ADC and the RU unit, and subsequent transformations in the frequency domain, requiring block processing with a lower clock frequency, should be performed after signal level compensation.

Functional diagram of the claimed device is presented in FIG. 3, where indicated:

1 - block blanking pulse interference (BIL);

2 - gain control unit (RU);

3 - controlled attenuator;

4 - amplitude detector;

5 - the first comparator;

6 - second comparator;

7 - counter;

8.1-8.N - from the first to the N-th band filters;

9 - the first adder;

10 - analog-to-digital Converter (ADC);

11 - the second block delay;

12 - the second block of memory;

13 - the second block of multiplication;

14 - block fast Fourier transform (FFT);

15 - the first block of memory;

16 - second adder;

17 - block calculating the reciprocal of the value (BOB);

18 - the first block delay;

19 - the first block of multiplication;

20 - block blanking narrowband interference (BUP);

21 - correlator;

22 - block forming a reference signal (FOS);

23 is a threshold block.

The inventive device contains a series-connected unit for blanking pulse interference (BIL) 1, the input of which is the input of the device, and a gain control unit (RU) 2, the first output of which is connected to the combined inputs of N bandpass filters 8.1 ... 8.N, the outputs of which are connected to the corresponding the inputs of the first adder 9, the output of which is connected through an analog-to-digital converter (ADC) 10 to the first input of the second multiplier 13.

The RU 2 block contains a controlled attenuator (UA) 3, the output of which, which is the first output of the RU 2 block, is connected to the input of the amplitude detector 4, the first and second outputs of which are connected to the inputs of the corresponding first 5 and second 6 comparators, the outputs of which are connected to the corresponding inputs counter 7, the clock input of which is the clock input of the RU 2 unit and connected to the clock input of the second delay unit 11. The output of the counter 7 is connected to the control input of UA 3 and the input of the second delay unit 11, the output of which is the second output the unit block RU 2, which is connected to the control input of the second memory unit 12, the output of which is connected to the second input of the second multiplication unit 13, the output of which is connected to the input of the fast Fourier transform unit (FFT) 14, the group of outputs of which is connected to the first group of inputs of the first block multiplications 19.

The first memory block 15 has N groups of outputs connected to the corresponding N input groups of the second adder 16, which is connected in series with the reciprocal calculating unit (BOB) 17 and the first delay unit 18, the output group of which is connected to the second group of inputs of the first multiplication block 19, which is connected in series with the blocking unit for narrowband interference (BUP) 20 and the correlator 21, the second group of inputs of which is connected to the group of outputs of the block forming the reference signal (FOS) 22, and the group of outputs of the correlator 21 soy dinene with a group of inputs of the threshold block 23, the output of which is the information output of the device.

In blocks 10, 12-23 there are also standard clock inputs (not shown in the drawing), to which signals are provided that synchronize the operation of the device as a whole. Blocks 2, 10, 12, 13, and 14 are clocked by the main clock signal with a frequency f _main , and blocks 15-23 are clocked with a clock signal with a frequency f ₁ = f _main / L, where L is the number of buffering samples.

The inventive device operates as follows.

The input radio frequency signal, which is an additive mixture of the signal, fluctuation, pulsed and concentrated noise, is fed to the input of the radio receiver and passes through the unit BIL, in which the blanking of pulsed noise is carried out, the result of which is fed to the input of the RU 2 unit, which sets the gain to so that the voltage at its output is within predetermined, predetermined limits.

The transfer coefficient of the RU 2 unit is determined by the digital code generated at the output of the counter 7, which is supplied to the control input of the UA 3. Also, from the output of the counter 7, the digital code is fed to the second delay unit 11, in which it is delayed by the number of clock cycles equivalent to the propagation delay of the signal to the second block of multiplication 13. From the second output of the block 2 RU, the digital code is fed to the control address input of the second block of memory 12, which stores the coefficients corresponding to each digital code for digital compensation with I drove. The compensation coefficient corresponding to the digital code from the second memory block 12 is supplied to the second input of the second multiplication block 13.

From the output of the controlled attenuator 3, the signal is sequentially supplied to the amplitude detector 4, and then to the first 5 and second 6 comparators, which compare the value of the input signal with the preset maximum and minimum values. If the amplitude of the output signal of the amplitude detector 4 is higher than the maximum value, then a signal is received from the output of the first comparator 5 to the first enable input of the counter 7, allowing the reduction of the transmission coefficient until the output signal becomes less than the set value. If the amplitude of the output signal of the amplitude detector 4 is lower than the minimum value, then from the output of the second comparator 6, a signal is received at the second enable input of the counter 7, which allows an increase in the transmission coefficient until the output signal becomes higher than the set minimum value. In this case, the clock input of the counter 7 receives clock pulses (TI) with a frequency f _DOS .

The signal from the first information output of the RU 2 unit is supplied simultaneously to N bandpass filters 8.1-8.N, which divide the frequency range of the input signal into N subbands. The signals obtained after filtering from the outputs of N bandpass filters 8.1-8.N are fed to the corresponding inputs of the first adder 9 (Fig. 4). The results of the summation through the ADC 10 are fed to the first input of the second block of multiplication 13. After multiplying the signal with a compensating coefficient from the second block of memory 12, the result goes to the FFT block 14, in which the signal samples are converted from time to frequency domain.

The group of outputs of the FFT block 14 is a group L of samples of the spectral components of the signal that are fed in parallel to the first group of inputs of the second multiplication block 19, in which the values of the spectral components are multiplied by the corresponding samples of the inverse complex transfer coefficient of bandpass filters 8.1-8.N. Moreover, the number of samples of the inverse complex transfer coefficient of the bandpass filters coincides with the number of spectral components L at the output of the FFT block 14.

The formation of samples of the inverse transfer coefficient of bandpass filters is as follows. In block 15 of the memory are samples of the complex transfer coefficient of each of the N bandpass filters, which are simultaneously fed to the corresponding input groups of the second summing unit 16, in which the corresponding samples of the complex transmission coefficients of various bandpass filters are simultaneously added.

In block 17 of the BOB, samples of the inverse transmit coefficient of bandpass filters 8.1-8.N are generated, which, through the first delay block 18, enter the second group of inputs of the first multiplication block 19.

The samples obtained as a result of multiplication of the signals of the spectral components of the signals are sent to the unit 20 of the FCU, where the spectral components of the interference are suppressed. Further, the samples of the signal from the L outputs of the PCU block 20 are supplied to the first group of inputs of the correlator 21, to the second group of inputs of which the reference signal samples from the output of the FSF block 22 are received.

The correlator 21 contains a series-connected multiplication unit, similar to block 19, and an inverse fast Fourier transform block, implemented similarly to the FFT block 14.

In the correlator 21, the cross-correlation function of the reference signal and the signal from the output of the BCU 20 is determined. The signal samples from the L outputs of the correlator 21 are supplied to the threshold block 23. Exceeding the threshold means signal detection. Information about the detection of the signal is fed to the output of the radio receiver.

Thus, in accordance with the task, a radio receiver was implemented in which a single clock signal is used for the ADC and the RU unit, and buffering and subsequent processing in the frequency domain are carried out after the signal is restored, which allows for a continuous ARV process.

The undoubted advantages of such an implementation of the device include the possibility of continuous in-line automatic adjustment of the susceptibility of the receiver to reduce the possibility of distortion of the received signal by blocking noise, regardless of the dynamics of changes in their amplitude. The dynamic range, for the increase of which N RP units were used in the prototype, will also not change, since in the proposed device the signal level is also maintained within the specified limits in front of the analog-to-digital converter unit, and the signal is restored by digitally multiplying by the inverse transfer coefficient of the unit gain control.

The implementation of blocks 1-10, 14-23 of the claimed device is similar to the blocks of the prototype device and can be performed in accordance with the monograph by Paul Horowitz and Winfield Hill “The Art of Circuit Engineering” in 2 volumes. Moscow, Mir, 1986, and the implementation of the introduced blocks 11, 12 and 13 is similar to the implementation of blocks 18, 15 and 19 of the prototype device, respectively.

Here is a proof of the effectiveness of the claimed device.

Consider the timing diagrams reflecting the signal level at several points of the prototype device (Fig. 5) and the inventive device (Fig. 6). In particular, at the output of the BIL unit 1 (Fig. 5a, Fig. 6a), at the output of the ADC 10 (Fig. 5b, Fig. 6b) and after compensation and the inverse fast Fourier transform in block 21 (Fig. 5c, Fig. 6c) )

The abscissa axis in the time diagrams shows the periods corresponding to the frequency of the clock signals of the TI used for automatic gain control. In FIG. 5 along the abscissa axis, the division price corresponds to the period of the clock signal TI1 with frequency f ₁ , and in FIG. 6 - period of the clock signal TI frequency f _DOS .

Let a signal U _sig be input to the prototype device, and at time t ₁ a blocking noise appears, which is shown in FIG. 5a. The diagram also shows the time moments corresponding to the periods of accumulation of samples for calculating the FFT and simultaneously clocking the RU units. Thus, at time t _{2 the} signal from the output of one or more filters exceeds the threshold of the comparator 5, and the counter 7 increases its value by one. The controlled attenuator 3 changes the transmission coefficient, and the corresponding signals to compensate for the attenuation are fed to the multipliers 24.1-24.N. The described process is shown in FIG. 5 B. Further, the level of blocking interference continues to grow, and at time t _{3 the} ADC 10 overflows, and the time interval 13-14 until the next threshold is triggered is the distortion interval of the receiving signal (Fig. 5c), which is undoubtedly a significant drawback of the prototype device.

When introducing blocks 11-13 into the receiver, we get that the RU 2 block will be clocked by the same signal as the ADC 10. Consider the same example. Let some U U _sig input at the input of the proposed device, and at time t ₁ a blocking noise appears, which is shown in FIG. 6a. The diagram also shows the time points corresponding to the periods of accumulation of samples for calculating the FFT, as well as the clocking of the ADC and the RU unit. Thus, at time t _{2 the} signal will exceed the threshold of the comparator 5, and the counter 7 increases its value by one. The controlled attenuator 3 changes the transmission coefficient, and the corresponding signal for compensating for attenuation enters through the delay units 11 and memory 12 to the second multiplication unit 13. The described process is shown in FIG. 6b. Further, the level of blocking interference continues to grow, and at subsequent clock cycles at times t ₃ and t _{4, the} controlled attenuator 3 continues to attenuate the input signal (Fig. 6b), and at the output of block 13, the signal is compensated, as shown in Fig. 6c.

Thus, since the control of the attenuator in this construction of the receiving device is carried out continuously without buffering, the received signal has no signal reception intervals, which is a positive distinguishing feature of the claimed device.

To calculate the FFT of the processed signal, a buffer of L samples is accumulated [3], and in the inventive radio receiver the interval of signal reception will be equal to the sampling period, which is L times smaller than the prototype, while the increase in the dynamic range is maintained due to the ARV mechanism.

This allows continuous ARV implementation by using a single clock signal for the ADC and the RU unit, and buffering and subsequent processing in the frequency domain are performed after the signal is restored.

Literature

1. Copyright certificate No. 1637026. Device for correlation processing of broadband signals. - Makoviy V.A., Katkova T.P. MKI H04B 1/10, H04L 7/02 - 4 pp., Registration 08.23.1988 - Publ. 03/23/91, Bull. No. 11.

2. Arthur G. Stephenson, "Digitizing Multiple RF Signals Requires an Optimum Sampling Rate", Electronics, Mar. 27, 1972. - pp. 106-110.

3. Digital signal processing: Reference / L.М. Goldenberg, B.D. Matyushkin, M.N. Pole. - M .: Radio and communications, 1985.S. 14-20.

Claims (1)

A radio receiver with continuous automatic adjustment of susceptibility, comprising a pulse interference blanking unit (BIP), the input of which is the device input, N bandpass filters, gain control unit (RU), a first memory unit, a first adder and an analog-to-digital converter (ADC) connected in series , which is clocked by a clock signal with a frequency f _DOS ; a series-connected block of fast Fourier transform (FFT), the first block of multiplication, block blanking narrowband interference (BUP), a correlator and a threshold block, the output of which is the information output of the device; connected in series to a second adder, a reciprocal-calculating unit (BOB) and a first delay unit, the output group of which is connected to a second group of inputs of the first multiplication unit, a reference signal generating unit (FOS), the output group of which is connected to a second group of correlator inputs, the RU unit contains a controlled attenuator (UA), the output of which, which is the first output of the RU unit, is connected to the input of the amplitude detector, the outputs of which are connected to the inputs of the corresponding first and second comparators, output rows are connected to respective inputs of a counter whose output is connected to the control input of the V, and the clock input of the counter is a clock input of the EN block; wherein the first memory block, the second adder, the BOB unit, the first delay unit, the first multiplication unit, the ECU unit, the correlator, the FOS unit and the threshold unit are clocked with a frequency signal f ₁ = f _main / L, where L is the number of buffering samples, characterized in that a second memory unit and a second multiplication unit are introduced, and a second delay unit is added to the RU unit, the input of which is connected to the counter output, the clock input of the second delay unit is connected to the clock input of the counter, and the output of the second delay unit is the second output m RC unit and connected to a control input of the second memory unit, whose output is connected to a second input of the second multiplier having an input connected to the output of ADC, and second multiplier output connected to an input of an FFT unit; the output of the BIP unit is connected to the input of the RU unit, the first output of which is connected to the combined inputs of N bandpass filters, the outputs of which are connected respectively to the N inputs of the first adder; N groups of outputs of the first memory block are connected respectively to N groups of inputs of the second adder; wherein the RU unit, the second memory unit, the second multiplication unit and the FFT unit are clocked with a clock signal with a frequency of f _main .

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