RU2562366C1 - Apparatus for expanding modular code bases - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: apparatus for expanding modular code bases is characterised by that the input of the apparatus, to which is transmitted a modular polynomial code A(z)=(α₁(z), α₂(z), …, α_n(z)), where α_i(z) are remainders on the base p_i(z), i=1, …, n, used in a polynomial modular code, is connected to the first inputs of modulo p_i(z) multipliers of a first unit of multipliers, respectively, and the second inputs of said multipliers are connected to the outputs of a first memory unit, the output of the 2.i-th modulo p_i(z) multiplier of the first unit of multipliers is connected to the first input of the 4.i-th modulo p_n+1(z) multiplier of a second unit of multipliers. The second input of the modulo p_n+1(z) multiplier is connected to the output of a second memory unit, the outputs of the multipliers of the second unit of multipliers are connected to inputs of a modulo two adder, the output of which is the output of the apparatus.

EFFECT: reducing hardware costs on the base expansion operation in a polynomial modular code.

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Description

The invention relates to computer technology and, in particular, to non-position computer systems, and is intended to provide the required accuracy in the calculation using a modular code

One of the main advantages of the polynomial modular code (PMC) is the parallel processing of data on the bases of the PMC p ₁ (z), p ₂ (z), ..., p _n (z), where p _i (z) is the irreducible polynomial of the field GF (2 ) This property of the polynomial modular code allows not only to increase the speed of data processing through the use of low-bit residuals, but also to ensure the construction of fault-tolerant computing systems.

Since information is processed in parallel-functioning computing channels according to the number of MVP bases, in the event of failures, the invalid channel can be turned off. This leads to degradation of the structure of the computing device and a decrease in the accuracy of the calculation. Therefore, to ensure the required accuracy, a base expansion procedure is carried out.

When expanding the set of bases of a polynomial modular code based on p _{n + 1} (z), the range of representation of numbers

Expands to value

The task of expanding the base system is to find the remainder α _{n + 1} (z) modulo p _{n + 1} (z) satisfying

where A (z) = (α ₁ (z), α ₂ (z), ..., α _n (z)) is the result of calculations in the modular code, presented in the base system p ₁ (z), p ₂ (z), ..., p _n (z)

In [1] (Chervyakov N.I., Sakhnyuk P.A., Shaposhnikov A.V., Makokha A.N. Neurocomputers in the residual classes. Book 11. - M.: Radio engineering, 2003, 272 pp. - S.138-139) presents an algorithm for implementing the procedure for expanding the base system.

This algorithm is based on the Chinese remainder theorem (CTO), with the help of which a translation from a modular code to a positional code is carried out

where B _i is the orthogonal basis of the i-th base; r _A (z) is the rank of A (z) in the modular code.

Then, to calculate the remainder α _{n + 1} (z), the expression ([1 p.138])

Thus, to expand the base system, it is necessary:

1. Calculate the value of rank r _A (z)

; m_i(z) - вес ортогонального базиса;Where

; m _i (z) is the weight of the orthogonal basis;

2. Find the remainder α _{n + 1} (z) by the formula (5).

The main disadvantage of the presented base expansion algorithm is significant hardware costs.

The aim of the invention is to reduce hardware costs for calculating the remainder α _{n + 1} (z). The goal is achieved through the use of a new algorithm for expanding the base system.

The technical result achieved by the implementation of the claimed invention is to reduce hardware costs for expanding the base system.

Consider the algorithm for translating from a polynomial modular code to a positional code according to the Chinese remainder theorem (CTO), we have

- рабочий диапазон.Where $$P\left(z\right)={\prod }_{i=\mathrm{one}}^n{p}_i\left(z\right)$$

- working range.

We use the definition of orthogonal bases B _i (z), then expression (7) can be represented as

; m_i(z) - вес ортогонального базиса.Where

; m _i (z) is the weight of the orthogonal basis.

Multiplying the remainder α _i (z) by the weight of the orthogonal basis m _i (z) modulo p _i (z), taking into account that summing in RMB is modulo two, we can refuse to calculate the rank r _A (z) using the Chinese theorem on balances when translating to positional code.

Then, to calculate the new residue α _{n + 1} (z) from the base p _{n + 1} (z), we use the following expression:

Example. Let an ordered base system p ₁ (z) = z + 1, p ₂ (z) = z ² + z + 1, p ₃ (z) = z ⁴ + z ³ + z ² + z + 1 be given.

In this case, the range is

We calculate the values of P _i (z) and m _i (z). We have

P ₁ (z) = p ₂ (z) * p ₃ (z) = (z ² + z + 1) * (z ⁴ + z ³ + z ² + z + 1) = z ⁶ + z ⁴ + z ³ + z ² +1

P ₂ (z) = p ₁ (z) * p ₃ (z) = (z + 1) * (z ⁴ + z ³ + z ² + z + 1) = z ⁵ +1

P ₃ (z) = p ₁ (z) * p ₂ (z) = (z + 1) * (z ² + z + 1) = z ³ +1

We calculate the value of the weight of the orthogonal basis m _i (z) from the condition

Then we have

m ₁ (z) = 1;

m ₂ (z) = z + 1;

m ₃ (z) = z ² + z + 1.

Therefore, the orthogonal bases of such a base system are equal

B ₁ (z) = m ₁ (z) * P ₁ (z) = z ⁶ + z ⁴ + z ³ + z ² +1;

B ₂ (z) = m ₂ (z) * P ₂ (z) = z ⁶ + z ⁵ + z + 1;

B ₃ (z) = m ₃ (z) * P ₃ (z) = z ⁵ + z ⁴ + z ³ + z ² + z + 1.

Let a polynomial A (z) = z ^{6 be given} . This polynomial in the modular code is represented by A (z) = (1, 1, z).

As the basis for the extension, select

p _{n + 1} (z) = p ₄ (z) = z ⁴ + z + 1

We calculate the values of P _i (z) modp ₄ (z)

Define the product

Substitute the obtained values in the expression (9)

Define the remainder

The structure of the base extension device of the modular code is presented in figure 1.

, сумматор 6 по модулю два, выход устройства 7.The device contains the input of device 1, the first block of multipliers 2, which contains n multipliers modulo p _i (z), where i = 1, 2, ..., n, the first block of memory 3, for storing orthogonal weights m _i (z); the second block of multipliers 4, which contains n multipliers modulo p _{n + 1} (z), the second block of memory 5 for storage $${\left|P_i\left(z\right)\right|}_{p_{n+\mathrm{one}\left(z\right)}}^{+}$$

, adder 6 modulo two, the output of the device 7.

Moreover, the input of device 1 is connected to the first input of each of the multipliers p _i (z), i = 1, ..., n, (range designation) of the first block of multipliers 2, the second inputs of the multipliers of this block are connected to the output of the first memory block 3. Output of the multiplier 2 .i performing a multiplication operation modulo p _i (z) of the first block of multipliers 2 is connected to the first input of the multiplier 4.i performing a multiplication operation modulo p _{n + 1} (z) of the second block of multipliers 4. The second input of the multiplier 4. i of the second block of multipliers 4 is connected to the input of the second block of memory 5. The output of the multiplier 4 .i is fed to the input of the adder 6 modulo 2, the output of which is the output of the device 7.

. Это значение подается на первый вход умножителя 4.i, выполняющего умножение по модулю p_n+1(z). На второй вход умножителя 4.i второго блока умножителей 4 подается значение $${\left|P_i\left(z\right)\right|}_{p_{n+1}\left(z\right)}^{+}$$

с выхода второго блока памяти 5. С выхода умножителя 4.i, второго блока умножителей 4 снимаем значениеThe device operates as follows. The input of device 1 receives a modular code (α ₁ (z), α ₂ (z), ..., α _n (z)). The remainder α _i (z) is fed to the input of the multiplier 2.i of the first block of multipliers 2. The second input of the multiplier 2.i is the weight of the orthogonal basis m _i (z) from the output of the first memory block 3. From the output of the multiplier 2.i of the first block 2 multipliers are removed $${\left|({\alpha }_i\left(z\right)\ast m_i\left(z\right)\right|}_{p_i\left(z\right)}^{+}$$

. This value is supplied to the first input of the multiplier 4.i, which performs multiplication modulo p _{n + 1} (z). At the second input of the multiplier 4.i of the second block of multipliers 4, the value $${\left|P_i\left(z\right)\right|}_{p_{n+\mathrm{one}}\left(z\right)}^{+}$$

from the output of the second memory block 5. From the output of the multiplier 4.i, the second block of multipliers 4, remove the value

The calculated values of the product are fed to the inputs of the adder 6 modulo 2. At the input of the adder 6 modulo two appears the remainder value α _{n + 1} (z) in the extended base system. The calculated value of the remainder α _{n + 1} (z) goes to the output of the device 7.

Claims (1)

The base extension device of the modular code is characterized in that the input of the device to which the modular polynomial code A (z) = (α ₁ (z), α ₂ (z), ..., α _n (z)) is supplied, where α _i (z ) - residuals on the base p _i (z), i = 1, ..., n, used in the polynomial modular code, is connected to the first inputs of the multipliers modulo p _i (z) of the first block of multipliers, respectively, and the second inputs of these multipliers are connected to the outputs of the first memory block, the output of the 2.ith multiplier modulo p _i (z) of the first block of multipliers is connected to the first input of the 4.ith multiplier modulo p _{n + 1} (z) of the second block of multipliers, while the second input of the multiplier modulo p _{n + 1} (z) is connected to the output of the second memory block, the outputs of the multipliers of the second block of multipliers are connected to the inputs of the adder modulo two, the output of which is the output of the device .