RU2553221C2 - Methods of executing computational primitives and device therefor - Google Patents

Abstract

FIELD: physics, computer engineering.

SUBSTANCE: group of inventions relates to digital computer engineering and can be used to execute computational operations. The device comprises in each binary bit two RS flip-flops, eight AND logic elements, four OR logic elements, four NOT logic elements, a data input and five control inputs. The device includes a computational operation control unit which includes three RS flip-flops, thirteen AND logic elements, six OR logic elements, two NOT logic elements, three clock inputs, five control inputs, three outputs for an operation of comparing the modules of two codes.

EFFECT: faster operation.

6 cl, 2 dwg

Description

и $$\left|B\right|$$

, т.е. определение $$\left|A\right|>\left|B\right|$$

; $$\left|A\right|<\left|B\right|$$

и $$\left|A\right|=\left|B\right|$$

без увеличения оборудования УВВО, при этом устройство содержит как собственно устройство выполнения вычислительных операций, так и блок управления выполнением операций (БУВО).The invention relates to the field of computer technology and can be used in computer processors and in digital automation devices. Known methods and devices for performing computational operations (UVVO), which consist in sequentially performing elementary operations (EO) of receiving terms, forming a transfer and amount in each category, and entering the amount in the triggers of the result register or in the triggers of the first term. Methods and devices for performing computational operations are discussed in detail in M.A. Kartseva "Arithmetic of digital machines", publishing house "Science", 1969, pp. 130-201, 273-286, 331-338. Common disadvantages of the known methods and devices are the need to use three trigger registers to perform the basic addition operation, the costs of at least three time steps to perform the EO of receiving the code, the formation of the transfer potential T _p = 2nτ (here n is the number of bits, τ is the time delay of the transfer signal on one element AND, OR) and storing the summation result in the result register. To improve the performance of addition operations, various circuits of accelerating the spread of the transfer potential are widely used, but this is associated with additional equipment costs, power consumption and financial costs. The closest adopted for the prototype is the device according to patent RU 2388041 A method and device for adding binary codes, which uses only two RS-flip-flops in each category, partially combined in time performing elementary operations of receiving the second term and generating transfer, but the total signal delay transfer remains equal to 2nτ. The proposed methods and device eliminate the noted disadvantages of the prototype. The aim of the invention is to increase the speed of computing operations by reducing the time delay of the transfer signal, expanding the list of operations with minimal hardware costs. To this end, methods and a device for performing computational operations (VO) are proposed that provide simultaneous EO reception of the code and the formation of transfer in one time cycle, with only two trigger registers built on the basis of RS-triggers and elements AND, OR, NOT, operation logical multiplication is performed in one time cycle without taking into account the time of reception of the code of the second factor, while no additional equipment is required, the operation of comparing the modules of register codes is introduced $$\left|A\right|$$

and $$\left|B\right|$$

, i.e. definition $$\left|A\right|>\left|B\right|$$

; $$\left|A\right|<\left|B\right|$$

and $$\left|A\right|=\left|B\right|$$

without increasing the UVVO equipment, the device contains both the actual device for performing computational operations and the operation control unit (BWO).

21, ВУ выполнением операцией сложения по модулю 2 (ОСМ2) 22, ВУ выполнением операции логического умножения (ОЛУ) 23, ВУ формированием имитационного потенциала переноса (ИПП) 24, выход потенциала переноса i-го разряда (P_i) 26, выход A_i 27. На фиг. 2 приведена функциональная схема блока управления выполнением вычислительных операций, БУВО, содержащая элементы И 201-213, элементы ИЛИ 214-219, элементы НЕ 220, 221, триггер знака кода регистра А (3 нА) 223, триггер знака кода регистра В (3 нВ) 224, триггер индикации инверсного кода регистра А (Tr 3) 225, информационный вход знака регистра В 226. Входы первого, второго и третьего временных тактов (t1, t2, t3) 227, 228, 229 соответственно. Входы управления вычислительными операциями сложения, вычитания, инвертирования регистра А, логического умножения и операции сравнения модулей кодов (ОС, ОВ, ОИА, ОЛУ, ОСМ2) 230, 231, 237 232, и 233 соответственно.In FIG. Figure 1 shows a functional diagram of two categories of air-blast discharges, each discharge of which contains elements AND 1-8, elements OR 9-12, elements NOT 13-16, RS triggers (Tr) 17, 18, information input (II) 19, control input ( WU) by issuing a direct code B 20, WU by issuing an inverse code $$\overline{B}$$

21, VU by the operation of addition modulo 2 (OSM2) 22, VU by the operation of logical multiplication (OLU) 23, VU by formation of the simulation transfer potential (IPP) 24, the output of the transfer potential of the i-th discharge (P _i ) 26, the output A _i 27. In FIG. 2 is a functional diagram of a control unit for performing computational operations, BUVO containing AND 201-213 elements, OR 214-219 elements, HE 220, 221 elements, register code sign trigger A (3 nA) 223, register code sign trigger B (3 nV ) 224, the trigger for indicating the inverse code of register A (Tr 3) 225, the information input of the sign of register B 226. The inputs of the first, second and third time clocks (t1, t2, t3) 227, 228, 229, respectively. The control inputs for the computational operations of addition, subtraction, inversion of register A, logical multiplication, and comparing code modules (OS, OV, OIA, OLU, OSM2) are 230, 231, 237 232, and 233, respectively.

и $$\left|B\right|$$

(ОСМ) 233 подключен к третьему входу ИЛИ 216, выходы И 6 каждого разряда УВВО через связь 27 соединены с входами И 211, выход которого подключен к первым входам И 210, 213. Выход И 210 подключен к входу ИЛИ 218. Выход потенциала переноса самого старшего разряда УВВО Pn 26 подключен к входу И 208 и через НЕ 221 к входу И 207. Выходы И 208, 207, 213 являются признаками $$\left|A\right|>\left|B\right|$$

, $$\left|A\right|<\left|B\right|$$

или $$\left|A\right|=\left|B\right|$$

, и $$\left|A\right|=\left|B\right|$$

234, 235, 290 соответственно. Вход операции ОСМ2 233 соединен с третьим входом ИЛИ 216. Вход операции ОИА 237 соединен с четвертым входом ИЛИ 219.A device for performing computational operations is as follows. In the initial state (in statics), the code of the first term is stored in Tr 17, the zero code is stored in Tr 18, and there are no high potentials (VP) on VU 20-24. Each bit of the device performing computational operations is as follows. Information input (II) 19 is connected to a single input Tr 18. The single and zero outputs Tr 18 are connected to the first inputs And 1, 2, respectively, the second inputs of these elements are connected to WU 20, 21. The outputs And 1, 2 through OR 9 are connected to the first inputs OR 11 and AND 7. The second inputs of these elements are connected to the output OR 12 of the least significant bit, the output OR 11 is connected to the first inputs AND 8, AND 3. The second input AND 8 is connected to the output AND 6. The outputs AND 8, 7 are connected to the first and second inputs OR 12, the third input of which is connected to VU 24. The output And 7 through NOT 13 is connected to the second input And 3, tr the input of which is connected to the VU 22. The output And 3 is connected to the first inputs And 4, 5, the second inputs of which are connected to the input and output NOT 16, respectively. The output AND 4 through HE 14 is connected to the zero input Tr 17. The output AND 5 through NOT 15 is connected to a single input Tr 17 and the first input AND 6. The output AND 6 is the output of the counting trigger Ai. The output AND 4 is connected to the first input OR 10, the second and third inputs of which are connected to a single output Tr 17 and VU 23, respectively. The output OR 10 is connected to the second input AND 6. The output AND 6 is connected to the second input AND 4 and NOT 5. The output is NOT 16 connected to AND 6. The output of the AND 6 element of each digit is connected to the inputs AND 211 of the BUVO. The operation of the operation control unit (Fig. 2) is as follows. The information input of the register sign B 226 is connected to a single input Tr 224, the single and zero outputs of this trigger are connected to the first inputs AND 201, 202, their second inputs are connected to the single and zero outputs Tr 223. The outputs AND 201, 202 through OR 214 are connected with inputs AND 204, 205 and through NOT 220 with inputs AND 203, 206. Outputs AND 203, 205 through OR 216 are connected to the first input. And 209, the second input of which is connected with the output And 207. The output And 209 is connected to a single input Tr 223 and through OR 218 with a zero input of the same trigger and a single input Tr 225. The outputs AND 204, 206 are connected to the inputs OR 215. The outputs OR 215, 216 are WU 20, 21 devices for performing computational operations. The input of the first time cycle (t1) 227 is connected to OR 219, the input t2 228 is connected to the input OR 217 and to the first inputs AND 208, 207, the input t3 229 is connected to the zero input Tr 225 and to the first inputs And 210, 212, 213. The second input And 212 is connected to a single output Tr 225, the output of the said And is connected to the inputs OR 219, 217, the outputs of which are WU 24, 22 of the computing device. The input of the subtraction operation (OB) 231 is connected to the second inputs AND 205, 206. The input of the addition operation (OS) 230 is connected to the second inputs AND 204, 203. The input of the operation of logical multiplication (OLU) 232, then VU 23 and through OR 219, 215 is connected to WU 24, 20, respectively. Input of code module comparison operation $$\left|A\right|$$

and $$\left|B\right|$$

(OSM) 233 is connected to the third input of OR 216, the outputs And 6 of each discharge of the air-borne air supply are connected via inputs 27 to the inputs of AND 211, the output of which is connected to the first inputs of AND 210, 213. The output of AND 210 is connected to the input of OR 218. The output of the transfer potential itself high-order discharge of the air-borne air discharge system Pn 26 is connected to the input And 208 and through NOT 221 to the input And 207. The outputs And 208, 207, 213 are signs $$\left|A\right|>\left|B\right|$$

, $$\left|A\right|<\left|B\right|$$

or $$\left|A\right|=\left|B\right|$$

, and $$\left|A\right|=\left|B\right|$$

234, 235, 290, respectively. The input of the OSM2 233 operation is connected to the third input of the OR 216. The input of the operation OIA 237 is connected to the fourth input of the OR 219.

Consider the operation of the device for computing operations and the control unit of computing operations.

, который поступит на входы И 4, 5, выходы которых через НЕ 14, 15 соединены с нулевым и единичным входами Tr 17, и выполнит инвертирование кода упомянутого триггера. При этом в тех разрядах устройства, в которых P_i-1=Bi=1, инвертирование Tr 17 запрещается низким потенциалом с выхода НЕ 13. При Bi=P_i-1=0, также запрещается инвертирование Tr 17. Результат суммы i-го разряда формируется согласно соотношению $$Si=\left(Ai\oplus \overline{Qi}\right)v\left(\overline{Ai}\oplus Qi\right)$$

, здесь Qi - импульс, сформированный на выходе элемента И 3; $$\oplus$$

- знак сложения по модулю два. При 3 нА=3 нВ результат суммирования кодов $$\left|A\right|$$

и $$\left|B\right|$$

с учетом переносов сохраняют знак регистра А. Операция сложения выполняется за два временных такта, результат операции хранится в триггерах А в прямом коде. В том случае, если знаки слагаемых кодов А и В не равны, т.е. 3 нА≠3 нВ, по t1 высокий потенциал с НЕ 220 по цепи элементов И 203, ИЛИ 216, ВУ 21 поступит на И 2 УВВО и осуществит выдачу инверсного кода Tr 18 на входы элементов формирования Pi и Si. Все другие выполняемые по t1 ЭО выполняются аналогично выполнению операций, рассмотренных при сложении кодов с одинаковыми знаками. По t2 при 3 нА≠3 нВ анализируется потенциал переноса Pn, выработанный в самом старшем разряде УВВО, и выполняется сложение по модулю два кода регистра А, инверсного кода регистра $$\overline{B}$$

и ПП P_i-1. При Pn=1, что имеет место при модуле кода $$\left|A\right|$$

больше модуля кода $$\left|B\right|$$

, т.е. $$\left|A\right|>\left|B\right|$$

, выполняют сложение кодов $$\left|A\right|$$

и $$\left|B\right|$$

с учетом ПП и прибавляют к коду самого младшего разряда устройства единицу за счет подключения Pn=1 к входам элементов ИЛИ 11, И 7 упомянутого разряда. Знак регистра А присваивается полученной сумме. При Pn=0, что имеет место при $$\left|A\right|<\left|B\right|$$

или $$\left|A\right|=\left|B\right|$$

выполняют ЭО сложения кодов $$\left|A\right|$$

и $$\left|\overline{B}\right|$$

с учетом переносов, при этом с выхода НЕ 221 на вход И 207, через И 209, на счетный вход Tr 223 поступит ВП, который выполнит инвертирование кода упомянутого триггера и установит в «1» Tr 225, что является признаком инверсного кода, сформированного по t2 в регистре А. По третьему временному такту t3 ВП, поступивший по входу 229, установит Tr 225 в «0», по цепи элементов И 212, ИЛИ 219 поступит на ВУ 24 и по цепи элементов ИЛИ 217, ВУ 22, И 3 поступит на входы И 4, 5 УВВО и выполнит инвертирование кода всех разрядов регистра А, кроме знакового разряда. Кроме того, при наличии кода «1» с выхода И 6 во всех разрядах регистра А за счет информационной связи 27 на выход И 211, 210 будет выработан ВП, который через ИЛИ 218 поступит на нулевой вход Tr 223 и установит его в «0». При этом на вход 229 поступит ВП, который по цепи элементов И 212, ИЛИ 219, ВУ 24 УВВО поступит на ИЛИ 12, И 3 всех разрядов и разрешит выполнение ЭО инвертирования кода регистра А. Одновременно ВП с выхода И 212 через ИЛИ 217 поступит на ВУ 22 и выработает сигнал $$Q_c^2$$

инвертирования кода регистра А. Кроме того, ВП с входа 229 установит Tr 225 в «0» и, в случае равенства единице кода всех триггеров регистра А, с выхода И 211, 210 ВП через ИЛИ 218 установит Tr 223 в «0». Также по t3 запрещается выдача на входы элементов И 7, ИЛИ 11, т.е. с ВУ 21 снимается ВП. На этом ОС при 3 нА≠3 нВ завершается. Результат операции будет храниться в триггерах регистра А в прямом коде.1. The addition operation (OS). The operation is performed in two to three time steps t1, t2, t3. By t1, the control input (WU) 230 receives a high potential (VP) of the OS. At the same time, they perform EO: receiving the code of the second term coming through the information inputs (ИВ) 19 to the unit inputs Tr 18 and to Tr 224; comparing the signs of the terms on AND 201, 202, OR 214 BUVO, at 3 nA = 3 nV, the output of the OR 214 is generated by the VP, which through the And 204, OR 215 circuit goes to the WU 20 issuing the direct code B; formation of the simulated transfer potential (IPP) Pi ′ ″, the primary and auxiliary transport potentials Pi ′ and Pi ″ equal to Pi ′ = (BivP _i-1 ) · Ai and Pi ″ = Bi · P _i-1, respectively. Pi ″ ′ = 1 in all discharges is formed due to the supply of the VI to VU 227. Then the signal passes through the OR 219, VU 24 circuit and enters the third input OR 12 of each air-blast discharge. All three types of transfer potentials logically add up to OR 12. Thus, the transfer potential in each category is formed by the relation Pi = [A · (BivP _i-1 )] vBi · P _i-1 vIPP = Pi′vPi ″ vPi ″ ′ = one. This method of forming the maximum PP without time delay of the signal is achieved under the condition A ₁ = B ₁ = 1, in all the higher digits AivBi = 1. This makes it possible to eliminate the time delays of the formation of the end-to-end transfer signal determined by the known relation Pt = 2nτ (n is the number of bits; τ is the delay time of the signal on one AND, OR element) and reduce the maximum time delay of the transfer to a duration equal to the duration t1. This allows us to exclude the dependence of OS performance on the number of air-blast discharges without additional use of equipment. According to t2, after the VP is removed from VU 24, real potentials Pi will be generated in each discharge of the device. To obtain Si VP through VU 228, OR 217, VU 22 is fed to input And 3 and generates a pulse Qi of performing EO addition modulo two, determined by the ratio $$Qi=\left(Biv{P}_{i-\mathrm{one}}\right)\cdot \left({\overline{P}}_{i-\mathrm{one}}\cdot \overline{Bi}\right)\cdot \mathrm{AT}\mathrm{At}\text{22}$$

which will go to the inputs And 4, 5, the outputs of which through NOT 14, 15 are connected to the zero and single inputs Tr 17, and will invert the code of the above trigger. Moreover, in those bits of the device in which P _i-1 = Bi = 1, the inversion of Tr 17 is prohibited by the low potential from the output of HE 13. At Bi = P _i-1 = 0, the inversion of Tr 17 is also prohibited. discharge is formed according to the ratio $$Si=\left(Ai\oplus \overline{Qi}\right)v\left(\overline{Ai}\oplus Qi\right)$$

, here Qi is the impulse generated at the output of the And 3 element; $$\oplus$$

- modulo two addition sign. At 3 nA = 3 nV, the result of the summation of the codes $$\left|A\right|$$

and $$\left|B\right|$$

taking into account transfers, they keep the register sign A. The addition operation is performed in two time steps, the result of the operation is stored in triggers A in direct code. In the event that the signs of the terms of codes A and B are not equal, i.e. 3 nA ≠ 3 nV, with t1 high potential with NOT 220 along the AND 203, OR 216 circuit, VU 21 will go to And 2 UVVO and will issue an inverse code Tr 18 to the inputs of the Pi and Si formation elements. All other EOs performed on t1 are performed similarly to the operations considered when adding codes with the same signs. With respect to t2, at 3 nA ≠ 3 nV, the transport potential Pn developed in the highest-order discharge of the AHE is analyzed, and modulo two codes of register A and an inverse code of the register are added $$\overline{B}$$

and PP P _i-1 . With Pn = 1, which takes place with the code module $$\left|A\right|$$

more code module $$\left|B\right|$$

, i.e. $$\left|A\right|>\left|B\right|$$

perform the addition of codes $$\left|A\right|$$

and $$\left|B\right|$$

taking into account the PP, they add one to the code of the least significant bit of the device by connecting Pn = 1 to the inputs of the elements OR 11, AND 7 of the mentioned discharge. The sign of register A is assigned to the amount received. For Pn = 0, which takes place for $$\left|A\right|<\left|B\right|$$

or $$\left|A\right|=\left|B\right|$$

perform EO code addition $$\left|A\right|$$

and $$\left|\overline{B}\right|$$

taking into account transfers, while from the output NOT 221 to the input AND 207, through And 209, the counting input Tr 223 will receive a VP that inverts the code of the above trigger and sets Tr 225 to “1”, which is a sign of the inverse code generated by t2 in register A. According to the third time cycle t3, the VI received at input 229 will set Tr 225 to “0”, through the chain of elements AND 212, OR 219 will go to VU 24 and through the chain of elements OR 217, VU 22, AND 3 will to the inputs And 4, 5 UVVO and will invert the code of all the digits of register A, except for the significant digit. In addition, if there is a code “1” from the output And 6 in all bits of the register A due to information communication 27 to the output And 211, 210 a VP will be generated, which through OR 218 will go to the zero input Tr 223 and set it to “0” . In this case, the input 229 will receive a VP, which through a chain of elements AND 212, OR 219, VU 24 UVVO will go to OR 12, AND 3 of all discharges and allow the EO to invert the code of register A. At the same time, the VP from the output AND 212 through OR 217 will go to VU 22 and will generate a signal $$Q_c^2$$

invert code of register A. In addition, the VI from input 229 will set Tr 225 to “0” and, if the code of all triggers of register A is equal to one, from the output And 211, 210 of the VI through OR 218 will set Tr 223 to “0”. Also on t3, the issuance of AND 7, OR 11 elements to the inputs is prohibited, i.e. VP is removed from VU 21. On this OS, at 3 nA ≠ 3 nV, it ends. The result of the operation will be stored in the triggers of register A in direct code.

на входы элементов формирования Pi и Si. Одновременно потенциал t1 формирует имитационный потенциал ИПП во всех разрядах УВВО, поступая по цепи элементов ВУ 227, ИЛИ 19, ВУ 24, ИЛИ 12 и на входы И 7, ИЛИ 3. Потенциал переноса (ПП) в каждом разряде формируется согласно соотношению $$Pi=\left[Ai\left(\overline{B}iv{P}_{i-1}\right)\right]\cdot \left(\overline{B}i\cdot P_{i-1}\right)\text{ ИПП}=\text{Pi'vPi''vPi'''}=\text{1}$$

, здесь Ai, $$\overline{B}i$$

- значение триггеров i-го разряда, P_i-1 - ПП, выработанных в младшем разряде, Pi″′ - имитационный потенциал переноса. Такой способ формирования ПП позволяет исключить временную задержку сигнала сквозного переноса при условии, что Ai·Bi=1, а во всех старших разрядах УВВО коды равны AivBi=1, при этом максимальное время задержки сигнала ПП не превышает длительности t1, что повышает быстродействие вычисления без увеличения аппаратурных затрат и обеспечивает независимость быстродействия выполнения ОВ от числа двоичных разрядов. По t2 анализируют наличие или отсутствие Pn, выработанного в самом старшем разряде, и выполняют ЭО сложения модулей кодов $$\left|A\right|$$

и $$\left|B\right|$$

с учетом выработанных ПП. При Pn=0 инвертируют код Tr 223, устанавливают Tr 225 в «1» и прибавляют к коду самого младшего разряда по связи 25 УВВО «1» за счет подключения выхода ИЛИ 12 самого старшего разряда УВВО к входам ИЛИ 11, И 7 младшего разряда. По ВТ 3 ВП по входу 229, И 212, ИЛИ 219, 217 поступает на ВУ 24, 22 и выполняет инвертирование всех разрядов регистра А, устанавливает Tr 225 в «0» и, при наличии кода «1» в каждом разряде регистра А, устанавливает Tr 223 в «0». При Pn=1 код регистра А сохраняется. На этом ОВ завершают, результат операции хранят в регистре А в прямом коде.2. Subtraction operation (OB). The operation is performed in two to three time steps. To perform an OB, a VI is supplied to the VU 231, which is connected to the first inputs AND 205, 206, at the same time, the code decreases from the IV 19, 226 to the unit inputs Tr Tr 18 and 224, the inequality of the signs of the registers A and B is determined using the comparison circuit on the elements And 201, 202, OR 214, NOT 220. If the signs of the registers A and B are equal, i.e. at 3 nA ≠ 3 nV along the chain of elements OR 14, NOT 220, AND 206, OR 215, WU 20 give a direct code Tr 18 to the inputs of the elements of the formation Pi and Si, i.e. to the elements AND 1, OR 9, OR 11, AND 7. At 3 nA = 3 nV, the VP from input 231 passes through the chain of elements AND 205, OR 216, VU 21 and gives an inverse register code $$\overline{B}$$

to the inputs of the elements of the formation of Pi and Si. At the same time, the potential t1 forms the simulation potential of the IPP in all the air-blast discharges, coming through the circuit of elements VU 227, OR 19, VU 24, OR 12 and to the inputs I 7, OR 3. The transfer potential (PP) in each discharge is formed according to the relation $$Pi=\left[Ai\left(\overline{B}iv{P}_{i-\mathrm{one}}\right)\right]\cdot \left(\overline{B}i\cdot P_{i-\mathrm{one}}\right)\text{IPP}=\text{Pi'vPi''vPi '''}=\text{one}$$

, here Ai, $$\overline{B}i$$

- the value of the triggers of the i-th category, P _i-1 - PP developed in the low-order bit, Pi ″ ′ - imitation transfer potential. Such a method of generating a PP allows eliminating the time delay of the end-to-end signal, provided that Ai · Bi = 1, and in all high-order bits of the UVBO codes are equal to AivBi = 1, while the maximum delay time of the PP signal does not exceed the duration t1, which increases the computational speed without increase in hardware costs and ensures the independence of the performance of the OB from the number of binary bits. Using t2, the presence or absence of Pn generated in the highest order is analyzed, and the EO addition of the code modules is performed $$\left|A\right|$$

and $$\left|B\right|$$

taking into account the developed PP. When Pn = 0, the code Tr 223 is inverted, Tr 225 is set to “1”, and the least significant bit is added to the code of the least significant bit by communication 25 of the UVBO “1” by connecting the output OR 12 of the oldest bit of the UVBO to the inputs of OR 11, AND 7 of the least significant bit. On VT 3 VP on input 229, And 212, OR 219, 217 is supplied to VU 24, 22 and inverts all bits of register A, sets Tr 225 to "0" and, if there is a code "1" in each bit of register A, sets Tr 223 to "0". With Pn = 1, register code A is saved. On this OB complete, the result of the operation is stored in register A in direct code.

3. The operation of logical multiplication (OLU). At t1, the code of the second factor is taken into register B. At t1 and t2, the OLU OL at input 232 goes to VU 23, through OR 219 to VU 24, and through OR 215 to VU 20. At the same time, the VI through VU 23, OR 10, AND 6 goes to AND 4, i.e. allows this item to work. VP from VU 24 through OR 12 of the i-th category goes to AND 7, OR 11 of the i-1 discharge, from the output of OR 11, the signal goes to the input And 3 and allows the operation of this element. When Bi = 1 VP with VU 20 through the circuit of elements AND 1, OR 9, AND 7, NOT 13 prohibits the operation AND 3. By t2 VP on the input 228, OR 217, VU 22 will go to the input And 3 of all discharges and install the triggers And at “0” of those digits in which Bi = 0, all triggers A of the other digits will retain their previous state. In this case, the signal from WU 22, AND 3, AND 4, NOT 14 passes to the zero input Tr 17. After the end of t2, the result of the OLU will be stored in Tr 17.

4. The operation of inverting the register code A (OIA). The operation is performed in two time steps. At t1, the EO is performed: IPP formation due to the input of 237 VPs, which, through the circuit of elements OR 219, VU 24, OR 12 of the i-th category, goes to AND 3 i + of the 1st category and allows its operation. By t2 VP, input 228, OR 217, VU 22, AND 3 is fed to inputs And 4, 5 and performs the inversion of the code Ai. If Ai = 1, then the VI from the single output of the RS-flip-flop 17 through OR 10, AND 6 goes to the second input And 4 and allows the pulse to go to the zero input Tr 17. In this case, the VI from the output of OR 10 will be kept constant for the duration of the signal with WU 22 due to the connection of the output AND 4 with the input OR 10. If Tr 17 stores the code “0”, then the high potential from the output NOT 16 will be maintained for the duration of the signal from WU 22, which is transmitted to the unit input Tr 17 through AND 5, NOT 15. Thus, the Ai trigger code will be inverted.

, при Pn=0 ВП с выхода НЕ 221, И 207 ВП выдается на выход 235, что соответствует $$\left|A\right|<\left|B\right|$$

или $$\left|A\right|=\left|B\right|$$

. Упомянутый сигнал через И 209 инвертирует код Tr 223 и устанавливают Tr 225 в «1». По t3 формируют ИПП, подключая ВП к входу 229, далее И 212, ИЛИ 219, ВУ 24, ИЛИ 11, на вход И 3 УВВО. Одновременно t3 с выхода И 212 через ИЛИ 217, ВУ 22 поступает на И 3 и выполнят инвертирование всех триггеров регистра А. При этом на выходе И 213 вырабатывается сигнал, соответствующий равенству сравниваемых кодов, т.е. $$\left|A\right|=\left|B\right|$$

. На выходе И 211, входы которого с помощью связи 27 соединены с выходом И 6 каждого разряда регистра А, вырабатывается ВП, который через И 210, ИЛИ 218 поступает на нулевой вход Tr 223 и устанавливает его в «0». По t3 триггер 225 устанавливается в «0». На этом ОСМ завершается.5. The operation of comparing code modules (OSM). At t1, the following EOs are performed: IPP formation in all discharges due to supply to the input of the 227 VP, which through OR 219 enters the VU 24, OR 12 of the i-th category and to the inputs AND 7 OR 11 of the i + 1-th category; accept the code of the second number in register B; provide an inverse code of the register B to the inputs of the formation of Pi and Si in each discharge; while the VP operation at the input 233, OR 216, WU 21 is connected to AND 2, AND 209 and stored for t1 and t2. By t2, the operation of adding direct code A and inverse code B is performed and the presence of Pn generated in the highest order is analyzed. When Pn = 1 at the output And 208 produce VP corresponding $$\left|A\right|>\left|B\right|$$

, at Pn = 0 VP from the output NOT 221, AND 207 VP is output 235, which corresponds to $$\left|A\right|<\left|B\right|$$

or $$\left|A\right|=\left|B\right|$$

. Said signal through AND 209 inverts the code Tr 223 and sets Tr 225 to “1”. On t3 form the IPP, connecting the VP to the input 229, then AND 212, OR 219, VU 24, OR 11, to the input AND 3 UVO. At the same time, t3 from the output of And 212 through OR 217, the WU 22 goes to And 3 and inverts all the triggers of register A. At the same time, the output corresponding to the equality of the compared codes is generated at the output And 213, i.e. $$\left|A\right|=\left|B\right|$$

. At the output And 211, the inputs of which are connected via the connection 27 to the output And 6 of each bit of register A, a VP is generated, which through And 210, OR 218 goes to the zero input Tr 223 and sets it to "0". At t3, trigger 225 is set to “0”. On this OSM ends.

Thus, the proposed methods and apparatus for performing elementary computational operations of addition, subtraction, logical multiplication, inversion, and comparison of code modules provide improved performance by combining the reception of the code and the formation of transfer signals in the time of the EO, while eliminating the dependence of the time of generating the transfer signal on the number binary bits of the device. Improving the speed of computing operations and the list of operations performed is achieved with minimal equipment costs.

Claims (6)

1. A method of performing an elementary computational operation (EVO) of adding binary codes, implemented on the basis of the parallel adder equipment, characterized in that the first term is stored in the first register A as a result of the previous operation, the second term is received in the second register according to the first time step t1 B, coming from the information inputs of each category, including the information input of the register sign B, determine the equality or inequality of the signs of the terms 3 nA = 3 nV or 3 nA ≠ 3 nV, with 3 nA = 3 nV code B due to the supply of high potential (VP) to the first control input (WU) by issuing a direct register code B to the inputs of hyphenation elements; form the simulated transfer potential (IPP) P ′ ″ in all binary bits of the computational operations device (IHE) by applying a pulse t1 to the fourth WU by developing the IPP, the transfer in each bit is formed according to the relation Pi = [Ai · (BivP _i-1 )] vBiP _i-1 vIPP = P ₁ ′ vP ₁ ″ vP ₁ ″ ”, here Ai, Bi - the value of direct codes of the i-th category A and B; P _i-1 - transfer from the least significant bit; Pi ′ is the main transfer equal to Ai · (BivP _i-1 ), the auxiliary transfer Pi ″ is equal to Bi · P _i-1 ; Pi ″ ′ - simulation transfer; at the same time, real transfer potentials are generated at Ai · Bi = 1 and at Ai · Pi = ₁ = 1, the mentioned transfer potentials (PS) are logically added using the fourth OR element, which allows to reduce the maximum delay time of the transfer signal from 2nτ to the pulse duration t1, τ is the time delay of the signal on one AND, OR element, provided that in each bit of the device the codes are AivBi = 1, and in the first bit, A ₁ = B ₁ = 1, according to the second time step t2, after removing the VP from IPP, in each discharge real transfer potentials will be formed, at 3 nA = 3 nV, perform EO addition modulo two trigger codes Ai with a trigger code Bi or with a carry signal received from the least significant bit P _i-1 , when B _i · P _i-1 = 1, perform EO addition modulo two in the ith the discharge is prohibited, the executive pulse of performing EO addition modulo two in the i-th discharge Q _{i is} generated according to the relation $$Q_i=\left(B_{i}v{P}_{i-\mathrm{one}}\right)\cdot {\overline{P}}_i\text{'}\text{'}\text{'}\text{'}\cdot \mathrm{AT}\mathrm{At}\text{3}$$

, here $${\overline{P}}_i\text{'}\text{'}\text{'}\text{'}$$

- inverse value of the auxiliary transfer potential of the i-th discharge; VU 3 - the third input for controlling the execution of EO addition modulo two, the mentioned pulse is connected to the inputs of the logic elements AND generating the pulses of setting Ai to "0" or "1", i.e. performing inversion of the trigger code Ai, the result of adding binary codes in the ith bit Si is generated according to the relation $$Si=\left(\overline{Ai}\oplus Q_i\right)v\left(A_i\oplus {\overline{Q}}_i\right)$$

, here $$\oplus$$

- the sign of addition modulo two, the result of addition is stored in register A in direct code, while the sum of S is assigned the sign of the first term, i.e. keep the sign of A; in the case of 3 nA ≠ 3 nV in t1, instead of issuing direct code B, a high potential of the inverter issuing the inverse code is generated and fed to the second control input of the VU 2 $$\overline{\left|B\right|}$$

to the inputs of the elements of the formation of potentials P _i and S _i , all other EOs are performed similarly to that considered, by t2 they analyze the real transfer potential developed in the oldest discharge of the device Pn, formed by the ratio $$Pn=\left[An\cdot \left(P_{n-\mathrm{one}}v{\overline{B}}_n\right)\right]\cdot \left(B_n\cdot P_{n-\mathrm{one}}\right)$$

, in the case of Pn = 1, i.e. at $$\left|A\right|>\left|B\right|$$

direct code modules summarize $$\left|A\right|$$

and inverse code $$\overline{\left|B\right|}$$

, i.e. $$\left|A\right|\oplus \left|\overline{B}\right|$$

and add “1” to the code of the first discharge of the device, the register sign A is assigned to the sum, i.e. keep the sign of the first term, the addition operation is completed; in the case of Pn = 0, i.e. at $$\left|A\right|<\left|B\right|$$

or $$\left|A\right|=\left|B\right|$$

perform an operation $$\left|A\right|\oplus \left|\overline{B}\right|$$

, set the trigger indication of the inverse code of the register And Tr 3 in "1", invert the trigger sign and register $$\left|A\right|$$

, according to the third time step t3, the triggers of register A are inverted, in addition to the sign discharge, set Tr 3 to “0”, when $$\left|A\right|=\mathrm{eleven}...\mathrm{one}$$

they also set the trigger 3 nA to "0", the result of the operation is stored in register A in direct code, this completes the addition operation. 2. The method of performing the EVO subtraction of binary codes, implemented on the basis of the equipment of the parallel adder, characterized in that the decremented is stored in the first register A in the direct code as a result of the previous operation, according to the first time step t1, the input received in the second register B is received from the information inputs of each category, including the sign category; form the simulation potential of IPP transfers in all bits of the device, except for the sign, by applying a high potential to the fourth input of the control of the formation of the simulation transfer potential; simultaneously formed and the real potentials of carries in Ai · Bi = 1 and Ai · P _i-1, the formation of STI operate on a parity _{Pi = [Ai · (P i} - ₁ vBi)] v (Bi · P i- ₁₎ vIPP = Pi′vPi ″ vP ′ ″, here Ai, Bi is the value of direct codes of triggers of the i-th category; P _i-1 - transfer from the least significant bit; Pi ′ = Ai · (BivP _i-1 ) is the main transfer signal; Pi ″ = Bi · Pi _i-1 is an auxiliary transfer signal Pi ′ ″ is a simulated transfer potential, this method of generating end-to-end transfer reduces the maximum transfer delay time from 2nτ in the known methods to a duration t1, provided that in the higher bits of the adder AivBi = 1, and the codes of the first category are 1, i.e. A1 · B1 = 1, τ is the time delay of the signal on one element AND, OR, determine the equality or inequality of the signs of the decremented and subtracted 3 nA = 3 nV or 3 nA ≠ 3 nV, in case of inequality of the characters give the direct code of the module subtracted $$\left|B\right|$$

to the inputs of the elements of generating transfer potentials P _i and the sum S _{i of} all bits due to the supply of high potential to the first control input of direct code B; The transfer potentials P _i ′, P _i ″ and P _i ′ ″ are logically added using the fourth OR element, according to the second time step t2 at 3 nA ≠ 3 nV in each binary digit, they generate a pulse of code addition modulo two $$Q_i=\left({\overline{Bi\cdot P}}_{i-\mathrm{one}}\right)\cdot \left(Bi\cdot P_{i-\mathrm{one}}\right)\cdot \mathrm{AT}\mathrm{At}\text{3}$$

connect it to the inputs of AND elements generating impulses of setting the trigger Ai to "0" or "1", here $${\overline{Bi\cdot P}}_{i-\mathrm{one}}=\overline{P}i\text{'}\text{'}\text{'}\text{'}$$

auxiliary transfer potential of the i-th discharge of VU 3 - the input for controlling the execution of addition modulo two, the result of the operation modulo two in the i-th digit is obtained according to the relation $$Si=\left(Ai+\overline{Q}i\right)v\left(\overline{A}i\oplus Qi\right)$$

and carry out by supplying the VP to the third control input, while the sign of register A is assigned to the sign of the sum, the subtraction operation at 3 nA ≠ 3 nV is completed, the result is stored in register A in direct code; at 3 nA = 3 nV, t1 and t2 give an inverse code $$\overline{B}i$$

to the inputs of the elements of the formation of Pi and Si, due to the supply of a high potential to the second input control output of the inverse code $$\overline{B}$$

, by t2, the presence or absence of the transfer potential Pn developed in the highest discharge of the device is also determined at Pn = 1, which corresponds to $$\left|A\right|>\left|B\right|$$

perform EO addition of the code module $$\left|A\right|$$

with inverse code module $$\overline{\left|B\right|}$$

, or a transfer signal from the least significant bit, for which, in each bit, an addition pulse is generated modulo two $$Qi=\left(Biv{P}_{i-\mathrm{one}}\right)\overline{\text{Pi ''}}$$

, which is connected to the inputs of the fourth and fifth elements AND, generating pulses of setting Ai to "0" or "1", in addition, the potential Pn = 1 is connected to the inputs of the elements AND, OR, forming a transfer in the first discharge of the device, which corresponds to the addition of a unit in the said discharge, the result of the operation of addition modulo two in the i-th discharge is performed according to the relation $$Si=\left(\overline{A}i\oplus Qi\right)v\left(Ai\oplus \overline{Qi}\right)$$

and carry out the supply of high potential VP to the third control input, while the sign of the code of register A is assigned to the sum, the operation is completed, the result is stored in register A in direct code; for Pn = 0, which takes place for $$\left|A\right|<\left|B\right|$$

or $$\left|A\right|=\left|B\right|$$

, by t2 perform the addition operation modulo two, according to the relation $$Si=\left(\overline{A}i\oplus Q_{i-\mathrm{one}}\right)v\left(Ai\oplus Qi\right)$$

invert the trigger of the sign of register A, set the trigger for indicating the inverse code of register A Tr 3 to “1”; according to the third time cycle t3, the triggers of register A are inverted and set to “0” Tr 3, at $$\left|A\right|=\mathrm{eleven}...\mathrm{one}$$

also set to “0” trigger 3 nA, the operation of subtracting two codes with the same signs is completed, the result is stored in register A in a direct code. 3. A method of performing an EVO of logical multiplication, characterized in that the first and second factors are stored in registers A and B, respectively, to perform the operation, generate high potentials at the first fourth and fifth inputs of the control for performing computational operations: issuing a direct Bi code, generating a simulation transfer potential and operations of logical multiplication of VU 1, VU 4 and VU 5, and also give an executive impulse to perform the addition operation modulo two by VU 3 and generate a pulse from the output of the third element And, which through the fourth element And and the second element DOES NOT enter the zero input of the trigger Ai and sets it to “0”, which corresponds to the result of the operation of logical multiplication in the i-th digit, the operation is performed in two time clocks, taking into account the reception of the second factor in register triggers B, the result is stored in register A. 4. A method for performing an EVO inversion of the register code A, characterized in that t1 form the simulation potential of transfers in all digits by applying a high potential to the fourth control input, apply a high potential to the third control input by performing the addition operation modulo two and generate each discharge signal Q _i according to the relation $$Q_i={\overline{P}}_i\text{'}\text{'}\text{'}\text{'}\cdot P_{i-\mathrm{one}}\text{'}\text{'}\cdot \mathrm{AT}\mathrm{At}\text{3}$$

, which is connected to the inputs of AND elements generating the impulse of setting the trigger Ai to "1" or "0", i.e. controlling the inversion of the mentioned trigger, in this case, if the trigger Ai stores the code "1", then Q _i passes to its zero input, if Ai stores the code "0", then Q _i passes to a single input, thus inverting the register code A. 5. A method for performing an EVO comparison of modules of two codes, characterized in that, according to the first time step t1, the module of the second code is received in register B, coming from the information inputs of the IW, an inverse code of register triggers is issued $$\overline{B}$$

to the inputs of the elements of the formation of transfers Pi and the sum of Si of each discharge, form the simulation potential of the transfer of IPP in all discharges due to the supply of a high potential to the fourth WU, at the same time form the real bitwise and through transfers in those discharges in which Ai · Bi = 1 and Bi · P _i-1 = 1, said potentials transfers PP logically formed on the fourth element, or the second time slot t2, after removal of the PPI with the fourth slave form real translations in all bits device assayed PP formed in the senior m discharge adder Pn, produce a signal when Pn = 1 $$\left|A\right|>\left|B\right|$$

, at Pn = 0, and set Tr 3 to "1", generate a signal $$\left|A\right|<\left|B\right|$$

or $$\left|A\right|=\left|B\right|$$

and perform the addition of modules of codes A and $$\overline{B}$$

, i.e. $$\left|A\right|+\left|\overline{B}\right|$$

; according to the third time step t3, the signal from the output of the eleventh element And, the control unit for computing operations BUVO, the inputs of which are connected to the outputs of all triggers A, is analyzed, in the presence of a high potential from the output of the said element And generate a signal $$\left|A\right|=\left|B\right|$$

, the execution of the operation is completed. 6. A device for performing elementary computing operations of addition, subtraction, logical multiplication, inversion of the code of register A and comparison of modules of two codes, comprising a device for performing computational operations (UVO) and a control unit for performing operations (BUVO), n - bit trigger registers A and B, schemes for the formation of the transfer potentials Pi and the sum Si in each bit, based on RS-triggers and logical elements AND, OR, NOT, characterized in that each binary bit of the UVBO contains the first and second RS-triggers Ai and Bi, respectively, while the information input of the i-th discharge (ИBi) is connected to the unit input of the second trigger Bi, the unit and zero outputs of which are connected to the first inputs of the first and second elements And, the second inputs of these elements are connected to the first control output direct code Bi and the second input control the issuance of the inverse code $$\overline{B}i$$

accordingly, the outputs of the mentioned AND elements through the first OR element are connected to the first inputs of the third and seventh OR elements, And accordingly, the second inputs of these elements are connected to the output of the fourth OR element of the i-1st discharge, the output of the third OR element is connected to the first inputs of the eighth and the third element AND, the second input of the eighth element AND is connected to the output of the sixth element And, the outputs of the eighth and seventh elements And are connected to the inputs of the fourth element OR, the output of which is the output of the transfer potential from the i-th row, the output of the seventh AND element is connected to the input of the first element NOT, the output of which is connected to the third input of the third AND element, its output is connected to the first inputs of the fourth and fifth elements AND, the second inputs of which are connected to the input and output of the fourth element NOT, the outputs of the fourth and of the fifth AND element through the second and third elements are NOT connected to the zero and single inputs of the first RS trigger, respectively, the output of the fourth AND element is connected to the first input of the second OR element, the single output of the first RS trigger is connected to the second the second input of the second OR element, the output of which is connected to the second input of the sixth element AND, the second input of which is connected to the output of the third element NOT, the third input of the module two addition control is connected to the second input of the third element AND, the fourth input of the control connected to the third input of the fourth OR element, the fifth input of the logical multiplication operation control is connected to the third input of the second OR element; a BUVO operation control unit containing the first and second sign digits of the registers A and B, the third trigger of the indication of the inverse code of the register A, the information input of the register sign B, the first input of the operation control of the addition of the VUOS, the second input of the operation of subtracting the VUOV, the third input of the operation control logical multiplication VUOLU, fourth input control operation of the inversion of VUOI, fifth input control operation of the comparison of code modules $$\left|A\right|$$

and $$\left|B\right|$$

VUSM, the first, second and third time clocks t1, t2, t3 and logical elements AND, OR, NOT, while the information input of the register sign B is connected to the single input of the second trigger, the unit and zero outputs of which are connected to the first inputs of the first and second elements And, the second inputs of which are connected to the unit and zero outputs of the first trigger, the outputs of the mentioned AND elements are connected to the inputs of the first OR element, the output of which is connected to the input of the first element NOT and with the first inputs of the fourth and fifth AND elements, the output of the first the element is NOT connected to the first inputs of the third and sixth elements AND, the second inputs of the third and fourth elements AND are connected to the HLA, the outputs of the third and fourth elements AND are connected to the inputs of the third and second elements OR, respectively, the output of the second element OR is the first control input of the WU direct code B, the output of the third element OR is the second WU issuing an inverse code $$\overline{\left|B\right|}$$

and connected to the first input of the ninth element AND, the second inputs of the fifth and sixth elements AND are connected to the VUOV by performing a subtraction operation, the outputs of the said elements AND are connected to the input of the third and second elements OR, the output of the fourth element OR of the oldest discharge of the device (UVO) Pn through the second the element is NOT connected to the second input of the seventh element And, the output of which through the ninth element And is connected to the counting input of the first trigger and to the unit input of the third trigger, the outputs of the logical elements And 6 of each discharge connected to the inputs of the eleventh element AND BUVO, the output of which is connected to the first input of the tenth and thirteenth elements AND, and the output of the tenth element And is connected to the input of the fifth element OR, the second input of the fifth element OR is connected to the output of the ninth element AND, the output of the fifth OR element is connected to the zero input of the first trigger, the second input of the tenth element And is connected to the input of the third time cycle t3 and to the zero input of the third trigger, the single output of the third trigger is connected to the first input of the twelfth element And, the second its input is connected to the bus of the third time cycle t3, the output of the twelfth element AND is connected to the inputs of the fourth and sixth elements OR, the outputs of which are the control input for creating the simulation transfer potential and the third WU by performing the addition operation modulo 2, the bus of the first time cycle t1 is connected to the second the input of the sixth OR element, the bus of the second time cycle t2 is connected to the first input of the fourth OR element and to the first inputs of the eighth and seventh elements AND, the second inputs of the mentioned elements AND are connected inens with the yield of the transfer potential formed in the highest discharge Pn, and with its inverse value $$\overline{P}n$$

accordingly, the signal from the output of the seventh element And is a sign $$\left|A\right|<\left|B\right|$$

or $$\left|A\right|=\left|B\right|$$

, the output signal of the eighth element And is a sign $$\left|A\right|>\left|B\right|$$

, the first input of the thirteenth element And is connected to the input of the third time cycle t3, its second input is connected to the output of the eleventh element And, the signal from the output of the thirteenth element And is a sign $$\left|A\right|=\left|B\right|$$

, the output of the fourth OR element is the third control input for the operation of addition modulo two UVO, the control input for the operation of logical multiplication is connected to the input of the sixth element OR BUVO and then to the fourth VU by the simulation potential of the transfer of air defense, through the second element of the BUVO it is connected to the third and first WU made by EO addition modulo two and WU direct register code B, in addition, the WU operation of logical multiplication is connected to the input of the tenth element OR UVBO, the input control the comparison operation odules codes $$\left|A\right|$$

and $$\left|B\right|$$

connected to the third input of the third OR element.

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