RU2641218C1

RU2641218C1 - Methods of executing computer operations (co) and device of their implementation

Info

Publication number: RU2641218C1
Application number: RU2016147472A
Authority: RU
Inventors: Татьяна Алексеевна Малышева
Original assignee: Татьяна Алексеевна Малышева
Priority date: 2016-12-02
Filing date: 2016-12-02
Publication date: 2018-01-16

Abstract

FIELD: physics.SUBSTANCE: each binary digit of the device contains four AND elements, four OR elements, one NOT element, three information inputs, two information outputs, three control inputs.EFFECT: increasing the speed of execution of the addition operation and expanding the functionality of the device by performing logical addition and logical multiplication operations with minimal equipment costs.4 cl, 1 dwg

Description

Изобретение относится к области вычислительной техники и может быть использовано в процессорных устройствах ЭВМ и устройствах цифровой автоматики. Известны способы и устройства выполнения вычислительных операций сложения (ОС), логического сложения (ОЛС) и логического умножения (ОЛУ). Упомянутые способы и устройство рассмотрены в книге М.А. Карцева «Арифметика цифровых машин», издательство "Наука", 1969 г. Стр. 147-156, рис. 2-8, 2-9, стр. 552-554. Общим недостатком выполнения ОС является необходимость формирования сигнала переноса и распространение его от младших разрядов до самого старшего разряда. В том случае, если в первом разряде слагаемые A₁=B₁=1, вырабатывается поразрядный сигнал переноса, равный Pi'=A₁B₁, который распространяется до n-го разряда, если слагаемые всех старших разрядов равны Ai V Bi=1, то максимальная временная задержка переноса будет равна Тз=2nτ (τ - задержка переключения элемента И, ИЛИ; n - число разрядов суммирующего устройства (СУ)), что определяет время выполнения ОС, при прочих равных условиях. Для снижения времени распространения сигнала переноса применяются различные схемы ускорения формирования переноса, но это требует дополнительных затрат оборудования, повышения энергопотребления и дополнительных финансовых расходов. Наиболее близким прототипом предлагаемого устройства является сумматор комбинационного типа, схема которого приведена в упомянутой книге М.А. Карцева, стр. 152, рис. 2-8. По принципу работы и затратам электронного оборудования прототип и предлагаемое СУ совпадают. Но быстродействие прототипа зависит от числа двоичных разрядов, а предлагаемое устройство не зависит от этого показателя, и максимальное время задержки переноса всегда равно длительности первого временного такта t1, что делает быстродействие СУ независимым от числа двоичных разрядов. Кроме того, предложенные способы и устройство обеспечивают расширение функциональных возможностей предлагаемого СУ за счет выполнения ОЛС и ОЛУ при минимальных затратах дополнительного оборудования.The invention relates to the field of computer technology and can be used in processor computer devices and digital automation devices. Known methods and devices for performing computational operations of addition (OS), logical addition (OLS) and logical multiplication (OLU). The mentioned methods and device are discussed in the book of M.A. Kartseva "Arithmetic of digital machines", publishing house "Science", 1969 p. 147-156, fig. 2-8, 2-9, pp. 552-554. A common drawback of running the OS is the need to generate a transfer signal and propagate it from the least significant bits to the most significant bit. In the case where the terms A ₁ = B ₁ = 1 in the first digit, a bit-wise transfer signal is generated equal to Pi '= A ₁ B ₁ , which propagates to the nth digit, if the terms of all the highest digits are Ai V Bi = 1 , then the maximum time delay of the transfer will be T3 = 2nτ (τ is the switching delay of the AND, OR element; n is the number of bits of the summing device (CS)), which determines the execution time of the OS, all other things being equal. To reduce the propagation time of the transfer signal, various schemes are used to accelerate the transfer formation, but this requires additional equipment costs, increased energy consumption and additional financial costs. The closest prototype of the proposed device is a combinational type adder, the circuit of which is given in the mentioned book by M.A. Kartseva, p. 152, fig. 2-8. According to the principle of operation and costs of electronic equipment, the prototype and the proposed SU coincide. But the speed of the prototype depends on the number of binary bits, and the proposed device does not depend on this indicator, and the maximum transfer delay time is always equal to the duration of the first time cycle t1, which makes the speed of the control system independent of the number of binary bits. In addition, the proposed methods and device provide an extension of the functionality of the proposed SU due to the implementation of OLS and OLU with minimal additional equipment.

Для реализации способов выполнения ВО предложено устройство, каждый разряд которого построен на основе четырех элементов И, четырех элементов ИЛИ, одного элемента НЕ и трех входов управления (ВУ) выполнением элементарных операций формирования имитационного потенциала переноса ВУ1 и входами ВУ2, 3 выполнением операции логического сложения и логического умножения, трех информационных входов Ai, Bi, Pi-1 и двух информационных выходов Pi, Si.To implement the methods of executing a VO, a device is proposed, each discharge of which is built on the basis of four AND elements, four OR elements, one NOT element and three control inputs (VU) by performing elementary operations of creating a simulation transfer potential of VU1 and VU2, 3 inputs by performing a logical addition operation and logical multiplication, three information inputs Ai, Bi, Pi-1 and two information outputs Pi, Si.

Для пояснения работы устройства при выполнении ВО на фиг. 1 приведена функциональная схема одного разряда СУ. На фиг. 1 приняты следующие обозначения: элементы И 1-4, элемент НЕ 5, элементы ИЛИ 6-9, первый - третий информационные входы (ИВ) 10-12, первый и второй информационные выходы (ИВых) 13, 14, первый вход управления ВУ1 формированием имитационного потенциала переноса (ИПП) 15, второй ВУ2 выполнением ОЛС 16, третий ВУ3 выполнением ОЛУ 17.To explain the operation of the device when performing VO in FIG. 1 shows a functional diagram of one discharge of SU. In FIG. 1 the following designations are accepted: elements AND 1-4, element NOT 5, elements OR 6-9, first - third information inputs (II) 10-12, first and second information outputs (II) 13, 14, first input of control VU1 formation simulation transfer potential (IPP) 15, the second VU2 by performing OLS 16, the third VU3 by performing OLU 17.

Устройство выполнено следующим образом. Информационные входы 10 и 11 соединены с входами И1 и ИЛИ6. Вход 12 соединен с ИЛИ 8, 7, И4. Выход И1 соединен с входами И4, ИЛИ7. Первый ВУ 15 подключен к входу ИЛИ7, выход которого соединен с И2. Выход 13 является первым информационным выходом Pi, выработанным в i-м разряде. Вход 16 подключен к входу И2. Вход 17 соединен с входом ИЛИ1. Выход И2 через НЕ5 соединен с И3. Выход ИЛИ8 связан с вторым входом И3, выход которого подключен к входу ИЛИ9. Выходы И3, 4 соединены с входами ИЛИ9, выход 14 является вторым информационным выходом Si.The device is as follows. Information inputs 10 and 11 are connected to inputs I1 and OR6. Input 12 is connected to OR 8, 7, AND4. Output I1 is connected to inputs I4, OR7. The first WU 15 is connected to the input OR7, the output of which is connected to And2. Output 13 is the first information output Pi generated in the i-th digit. Input 16 is connected to input I2. Input 17 is connected to input OR1. The output of I2 through HE5 is connected to I3. The output of OR8 is connected to the second input of I3, the output of which is connected to the input of OR9. The outputs I3, 4 are connected to the inputs OR9, the output 14 is the second information output Si.

Рассмотрим выполнение ВО. В исходном состоянии до начала выполнения ВО на ИВ 10-12 и ИВых 13, 14 отсутствуют высокие потенциалы (ВП). На ВУ 16 присутствует ВП, который разрешает работу И2, при наличии ВП на остальных входах упомянутого элемента.Consider the implementation of VO. In the initial state, prior to the commencement of VO execution, on IW 10-12 and IW 13, 14 there are no high potentials (VP). At WU 16 there is a VP that allows I2 to work, if there is a VP at the other inputs of the mentioned element.

1. Выполнение ОС. Операция выполняется за два временных такта t1 и t2. По t1 на ИВ10, 11 поступают ВП с единичных выходов триггеров n-разрядных регистров А и В (на фиг. 1 регистры не приводятся). В случае Ai=Bi=1 на выходе И1 формируется ВП поразрядного сигнала переноса i-го разряда Pi', на выходе ИЛИ6 также будет сформирован ВП при Ai V Bi=1. Упомянутые сигналы вырабатывают на выходе И2 потенциал переноса (ПП) в старший разряд. Одновременно ВП с И2 через НЕ5 запретит работу И3. Если в i-й разряд по входу 12 поступит сигнал переноса из i-1-го разряда, то на выходе 14 будет сформирован результат суммы i-го разряда Si=1. Потенциал переноса по выходу 13 будет проходить через все старшие разряды СУ, если в этих разрядах Ai V Bi=1, при этом максимальная временная задержка ПП при его прохождении из первого разряда в самый старший разряд будет равна Тз=2nτ (τ - задержка одного элемента И (ИЛИ), n - число разрядов СУ). Для исключения Тз в предлагаемом устройстве введен первый ВУ1 формированием имитационным потенциалам переноса, подключенный к третьему входу ИЛИ7. Это позволяет исключить время задержки формирования ПП при выполнении ОС. Таким образом, по t1 будут сформированы имитационные потенциалы переносов в тех разрядах, в которых Ai=Bi=1, и имитационные потенциалы переноса в каждом разряде, кроме тех разрядов, в которых Ai=Bi=0. По t2, после снятия ВП с первого ВУ15 формированием ИПП, в каждом разряде СУ останутся только реальные потенциалы переносов и реальные результаты суммирования двоичных кодов двух n-разрядных регистров А и В согласно соотношениям: Pi = AiBi v [Pi-1(Ai v Bi)]=1…1.1,

здесь Pi, Si - потенциалы переноса и суммы, выработанные в i-м разряде;

- инверсное значение Pi; Pi-1 - потенциал переноса, выработанный в i-1-м разряде, результат выполнения ОС выдают из суммирующего устройства с выходов элементов ИЛИ9 на вторые информационные выходы Si 14.1. Running the OS. The operation is performed in two time steps t1 and t2. By t1 on VI10, 11, VPs come from the single outputs of the triggers of n-bit registers A and B (the registers are not shown in Fig. 1). In the case of Ai = Bi = 1, the output of the bitwise transfer signal of the ith discharge Pi 'is formed at the output And1, and the output at the output of the OR6 will also be formed at Ai V Bi = 1. Mentioned signals generate output potential I2 transfer potential (PP) in the senior discharge. At the same time, VPs with I2 through HE5 will prohibit the operation of I3. If the transfer signal from the i-1st discharge arrives at the i-th digit at input 12, then the result of the sum of the i-th discharge Si = 1 will be generated at output 14. The transfer potential at output 13 will pass through all the higher-order bits of the CS if Ai V Bi = 1 in these bits, while the maximum time delay of the PP when it passes from the first bit to the most significant bit will be T3 = 2nτ (τ is the delay of one element AND (OR), n is the number of bits of SU). To exclude T3, the first VU1 is introduced in the proposed device by forming simulation transfer potentials connected to the third input OR7. This allows you to exclude the delay time of the formation of PP when performing the OS. Thus, along t1, simulated transfer potentials will be formed in those discharges in which Ai = Bi = 1, and simulation transport potentials in each discharge, except for those discharges in which Ai = Bi = 0. According to t2, after the VP is removed from the first VU15 by the formation of the IPP, in each discharge of the control system there will remain only real carry potentials and real results of summing the binary codes of two n-bit registers A and B according to the relations: Pi = AiBi v [Pi-1 (Ai v Bi )] = 1 ... 1.1,

here Pi, Si are the transfer potentials and the sums worked out in the ith discharge;

- inverse value of Pi; Pi-1 - the transfer potential developed in the i-1st category, the result of the OS is issued from the summing device from the outputs of the OR9 elements to the second information outputs Si 14.

2. Выполнение ОЛС. Операция выполняется за один временной такт t1. По первому такту принимают в каждый разряд СУ по входам 10 и 11 слагаемые Ai и Bi. Снимают ВП с ВУ16, чем запрещают работу И2, при этом на выходе НЕ5 будет ВП, разрешающий прохождение Ai v Bi=1 с ИВ 10, 11 по цепи элементов ИЛИ6, 8, И3, ИЛИ9 на второй информационный выход Si14. На этом выполнение операции заканчивают.2. Performing OLS. The operation is performed in one time cycle t1. At the first step, the terms Ai and Bi are taken into each discharge of the control system at inputs 10 and 11. The VP is removed from VU16, which prohibits the operation of I2, and at the output of HE5 there will be a VP allowing the passage of Ai v Bi = 1 from 10, 11 through the circuit of the elements OR6, 8, I3, OR9 to the second information output Si14. This completes the operation.

3. Выполнение ОЛУ. Операция выполняется за один временной такт t1. По этому такту принимают по входам 10 и 11 первый и второй сомножители Ai и Bi. Подают одновременно ВП на входы 15 и 17, при этом на выходе 13 будет высокий потенциал, который через третий информационный вход 12 поступит на вход И4 старшего разряда. Если на входы 10 и 11 i-го разряда поступили коды "1", то с выхода И1, через И4 первого старшего разряда ИЛИ9, на второй информационный выход 14 поступит ВП, что соответствует результату ОЛУ, равному "1". При всех других значениях сомножителей, поступивших на входы 10 и 11, на выходе будет отсутствовать ВП, т.е. результат ОЛУ будет равен "0". На этом операцию завершают.3. The implementation of OLU. The operation is performed in one time cycle t1. According to this clock, the first and second factors Ai and Bi are taken at inputs 10 and 11. At the same time, the VPs are supplied to the inputs 15 and 17, while the output 13 will have a high potential, which through the third information input 12 will go to the input I4 of the highest category. If the codes “1” are received at the inputs of the 10th and 11th bits of the i-th category, then from the output I1, through the I4 of the first high-order bit OR9, the VP will go to the second information output 14, which corresponds to the OLU result equal to “1”. For all other values of the factors received at inputs 10 and 11, there will be no VP at the output, i.e. the result of the OLU will be "0". This completes the operation.

Таким образом, предложенные способы и устройство их реализации позволяют выполнять ОС без временных задержек ПП, что обеспечивает повышение быстродействия СУ, расширить функциональные возможности за счет выполнения ОЛС и ОЛУ при минимальных затратах аппаратурных средств (20 входов логических элементов против 17 у прототипа).Thus, the proposed methods and device for their implementation allow you to run the OS without time delays of the software, which improves the performance of the control system, expand the functionality by performing OLS and OLU with minimal hardware (20 inputs of logic elements versus 17 for the prototype).

Claims

1. The method of performing the operation of adding the OS of two n-bit codes based on the use of combinational-type combiner equipment, containing in each binary digit the first - fourth AND elements, the first - fourth OR elements, one NOT element, the first - third information inputs of the information source, which receive signals from the outputs of the triggers of the i-th discharge Ai, Bi and the transfer signal from the i-1-th discharge Pi-1, respectively, while Ai and Bi are connected to the inputs of the first elements AND, OR, the third information input Pi-1 is connected to the inputs of the third, second element OR, and the fourth AND element, the first input of the second OR element is connected to the output of the first AND element and to the second input of the fourth AND element, the outputs of the first and second OR elements are connected to the second and first inputs of the second AND element, the output of the first OR element is also connected to the input the third OR element, the output of which is connected to the first input of the third AND element, the output of the second AND element is the first information output Pi and through the first element is NOT connected to the second input of the third AND element, the outputs of the third and fourth And elements are connected to the inputs of the fourth OR element, the output of which is the second information output Si, characterized in that the device includes the first input of the control 1VU generating the simulation transfer potential of the IPP connected to the third inputs of the second elements OR of each discharge, t1 for 1VU The VP that forms the simulation transfer P'i = 1 and the simulation sum S'i = 1 in all digits, except for the digits in which Ai = Bi = 0, t2 remove the VP from 1 VU, due to which in each discharge the VCs are simultaneously formed real result You Si and Pi, that the real sum of two n-bits, this completes the operation of adding two n-bit numbers.

2. The way to perform the operations of logical addition of the OLS of two n-bit codes based on the use of combiner type combiner equipment containing the first to fourth AND elements, the first to the fourth OR elements, the first NOT element, the first to the third information inputs of the IW, to which the signals from the outputs of the triggers of the i-th digits Ai, Bi and the transfer signal from the i-1st digits Pi-1, respectively, receive the first and second inputs Ai, Bi are connected to the inputs of the first elements AND, OR, the third information input generated in m in the upper discharge Pi-1, connected to the inputs of the second and third OR elements and the fourth AND element, the output of the first AND element is connected to the first input of the second OR element, the output of which is connected to the first input of the second AND element, the output of the first OR element is connected to the second input of the second AND element to the input of the third OR element, the output of the second AND element through the first element is NOT connected to the second input of the third AND element, the first input of which is connected to the output of the third OR element, the outputs of the third and fourth elements AND are connected to odes of the fourth OR element, the output of which is the second information output Si, characterized in that in each bit of the device a second control input is input 2VU OLS, prohibiting the operation of the second element And in all bits of the control system simultaneously, while 2VU is connected to the third input of the second element And whose output through the first element is NOT connected to the second input of the third AND element, which allows information signals Ai and Bi along the circuit of the first and third OR elements, the third AND element and the fourth OR element Si be the second data output which is the result of a RL.

3. The method of performing the logical multiplication operation of the OLU based on the equipment of the combinational type adder SU containing in each category the first - fourth AND elements, the first - fourth OR elements, the first NOT element, the first - the third information inputs of the signal generator, to which the signals from the outputs of the triggers the i-th discharge Ai, Bi and the transfer signal from the i-1-th discharge Pi-1, respectively, while the information inputs Ai and Bi are connected to the inputs of the first elements AND, OR, the third information input Pi-1 is connected to the inputs of the third and second elements of IL and with the input of the fourth AND element, the outputs of the first and second OR elements are connected to the first and second inputs of the second AND element, the output of the second AND element through the first element is NOT connected to the input of the third AND element, the output of the third AND element is connected to the input of the fourth OR element, the output which is the second information output of the device Si, characterized in that in each bit of the device is introduced the first input of the control 1VU development of the simulation potential of the transfer of IPP, which is connected through the second OR element to the first input one of the second AND element, the third control input of the 3BU OLU is introduced, connected to the third input of the first OR element, the operation is performed in one time cycle t1, according to which the potentials Ai and Bi are supplied to the first and second information inputs, with Ai = Bi = 1 s the output of the first element And at the second input of the fourth element And receives the VP, at the same time 1VU and 3VU also serves VP, due to which at the output of the second element And in all digits form a simulated transfer potential IPP, which will go to the inputs of the fourth elements And, from the output of which x VP via the fourth OR gate is fed to the second information output Si, in this implementation OLO terminated.

4. A device for implementing the computational operations of adding OS, operations of logical addition of OLS and operations of logical multiplication of OLU, made on the basis of equipment of a combinational type adder SU, containing in each binary digit the first - fourth AND elements, the first - fourth OR elements, the first NOT element, the first - the third information inputs of the IV, which receive signals from the outputs of the triggers Ai, Bi and transfer signals from the i-1st discharge Pi-1, respectively, each discharge contains information outputs Pi and Si, while the inputs Ai and Bi with connected to the inputs of the first and second elements AND, OR, the input Pi-1 is connected to the inputs of the third and second elements OR and to the input of the fourth element And, the output of the first element And is connected to the first input of the second OR element and the second input of the fourth element And, the outputs of the second and the first OR element is connected to the inputs of the second AND element, the output of the first OR element is also connected to the input of the third OR element, the output of the second AND element is the first information transfer output generated in the i-th digit Pi, the output of the second And element is through the first element is NOT connected to the second input of the third AND element, the first input of this AND element is connected to the output of the third OR element, the outputs of the third and fourth elements AND are connected to the inputs of the fourth OR element, the output of which is the second information output Si, characterized in that each the device’s discharge, the first input of 1VU control is introduced by the formation of the IPP transfer simulation potential, designed to exclude time delays of carry signals generated in the lower bits, the mentioned 1VU in each the discharge is connected to the third input of the second OR element, the second 2VU is introduced by performing OLS, which prohibits the transfer of the transfer potential to the senior bit, connected to the third input of the second AND element, the first and second inputs of which are connected to the outputs of the second and first OR elements, the output of the second AND element through the first element is NOT connected to the second input of the third AND element, the third input of the 3VU control is executed by performing OLU, the mentioned 3VU is connected to the third input of the first OR element.