RU2628179C1 - Device for dividing modular numbers - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: device for dividing modular numbers contains a clock pulse input, a global reset input, a dividend input, a divisor input, an OR element, a positional characteristic calculation unit, an approximation series refinement unit, a quotient derivation unit, and a quotient derivation output. In this case, the positional characteristics calculation unit contains a dividend register, n dividend inverters, n storage registers of module p_i, where i =1,…, n, n storage registers of coefficient k_i, n dividend integrators, n multipliers of the negative dividend, n multipliers of the positive divisible, an integrator of the value F(A), an integrator of the value F (-A), a storage register of value F (-A), a storage register of value F(A), a divisor register, n divisor inverters, n storage registers of module p_i, n storage registers of coefficient k_i, n divisor integrators, n multipliers of the negative divisor, n multipliers of the positive divisor, an integrator of value F(B), an integrator of value F (-B), a storage register of value F (-B), a storage register of value F (B), a XOR element, a dividend multiplexer, a divisor multiplexer, a comparison unit. The approximation series refinement unit contains a shift register, a counter, a storage register F (|A|), a minuend storage register, a minuend selection multiplexer, an inverter, a memory of degrees "2" in the residue number system, an integrator, next minuend selection multiplexer, NOT element, AND element. The quotient derivation unit consists of an OR element, a delay element, a holding register, n storage registers of the residue in modulo p_i, n integrators in modulo p_i, n demultiplexers in modulo p_i, n storage registers of the sum in modulo p_i, n inverters, n storage registers of the module p_i, n integrators, n storage registers of the reciprocal value of the sum in modulo n of multiplexers of sum selection, sign holding register, sum storage register in the residue number system, a storage register of value "1", a storage register of value "-1", multiplexer of dividend and divisor absolute value equality, multiplexer of quotient derivation, a quotient storage register.

EFFECT: providing the possibility of division with negative numbers represented in the residue number system.

4 dwg

Description

The invention relates to computing modular systems and is intended to perform the division of numbers represented in the system of residual classes (RNS).

In the RNS, an integer is represented as the remainder of the division into a set of modules, and arithmetic operations on the numbers are replaced by operations on the remainders. The operations are performed in parallel without inter-bit transfers, which allows for very fast addition, subtraction and multiplication. However, the division operation is time-consuming and requires the development of new computing architectures and hardware implementations.

Known neural network of the main division of modular numbers (patent pa invention RU No. 2400813, published September 27, 2010). The disadvantage of this device is the large amount of equipment and the inability to work with negative numbers. The well-known neural network is intended for dividing modular numbers in the case when a positive integer pairwise prime with the RNS modules p ₁ , p ₂ , ..., p _n , or a positive integer representing the product of numbers pairwise prime with p is used as a divider _i . To fulfill this condition, it becomes necessary to find an approximate divisor by using a generalized positional number system (OPSS). To find an approximate divider, additional equipment and time are needed.

A device is known for the main division of modular numbers in the format of a system of residual classes (patent for invention RU No. 2559772, published on 08/10/2015). The disadvantage of this device is the large amount of equipment and the need to transfer numbers from the main RNS to the auxiliary RNS.

Closest to this device, selected as a prototype, is a device for the main division of modular numbers (patent for invention RU No. 2559771, published 08/10/2015), containing the inputs of the dividend and divider (indicated in the prototype as input buses of the dividend and divider), which feed the dividend directly, and the divisor through the multiplication circuit, or through the multiplexer to the input of the modular number comparison circuit (in this invention, the function of the comparison circuit is performed by the positional characteristics calculator), the outputs of which the computational model is a <b, a > b or a = b, where a is the dividend, b is the divisor; the control outputs of the comparison circuit a <b, a > b are connected to a control circuit whose outputs are connected to the address inputs of the multiplexer, control inputs of the counter, shift and storage registers, adders private, divider and subtractor, as well as one of the key inputs, the second inputs which are connected to the output of the memory, the inputs of which are connected to the shift register, and the output a = b of the comparison circuit is connected to the input of the adder private, putting “one” in it, and the information outputs are connected to the circuits of the dividend and divider adders, the outputs are of which are connected to the left shift register, the output of which is connected to the counter for determining the highest degree of the approximate series of the private, the output of the counter is connected to the address inputs of the memory, the outputs of which through the key circuit and the ban provide the input of the adder of the private degree of a member of the series included in the specified term of the private and the input of the multiplication circuit of the highest degree of the series by the divider, the output of which through the multiplexer is connected to the comparison circuit, the outputs of which are connected to the adders of the dividend and divider; the output of the adder of the divider is connected to the input of the shift register to the right, the output of which is connected to the circuit of the subtractor, the output of the adder of the dividend is connected to the second input of the output, the output of the subtractor is connected to the storage register of the remainder when subtracting the number of quotients from the dividend, the output of which is connected through the adder of the dividend to the subtracter, the output of which is connected to the prohibition circuit, the outputs of which are connected to the balance storage register when subtracting the quotients of the number of quotients from the dividend and the quotient adder circuit.

The disadvantage of this invention is the limited functionality associated with the inability to work with negative numbers.

The technical result is the expansion of functionality, namely the ability to perform division with negative numbers represented in the system of residual classes.

, регистр хранения уменьшаемого, мультиплексор выбора уменьшаемого, инвертор блока уточнения аппроксимационного ряда, память хранения степеней «2» в СОК, сумматор блока уточнения аппроксимационного ряда, мультиплексор выбора следующего уменьшаемого, элемент НЕ, элемент И, причем первый вход регистра сдвига соединен с четвертым выходом блока вычисления позиционных характеристик, второй и третий входы связаны со входом тактового импульса и выходом элемента ИЛИ соответственно, четвертый вход соединен с первым выходом счетчика, второй и третий входы которого связаны со входом тактового импульса и выходом элемента ИЛИ соответственно, второй выход является вторым выходом блока уточнения аппроксимационного ряда и соединен с седьмым входом блока вывода частного, первый выход счетчика подключен также к управляющему входу мультиплексора выбора уменьшаемого, второй вход которого соединен с выходом регистра хранения

, второй и третий входы которого связаны со входом тактового импульса и выходом элемента ИЛИ соответственно, первый вход соединен с пятым выходом блока вычисления позиционных характеристик, первый вход мультиплексора выбора уменьшаемого соединен с выходом регистра хранения уменьшаемого, второй и третий входы которого связаны со входом тактового импульса и выходом элемента ИЛИ соответственно, первый вход подключен к выходу мультиплексора выбора следующего уменьшаемого, первый вход которого соединен с выходом мультиплексора выбора уменьшаемого, который одновременно соединен с первым входом сумматор блока, уточнения аппроксимационного ряда, второй вход которого соединен с выходом инвертора блока уточнения аппроксимационного ряда, вход которого соединен со вторым выходом регистра сдвига, второй вход мультиплексора выбора следующего уменьшаемого соединен с первым выходом сумматора блока уточнения аппроксимационного ряда, второй выход которого подключен одновременно к управляющему входу мультиплексора выбора следующего уменьшаемого и входу элемента НЕ, выход которого подключен ко второму входу элемента И, первый вход которого соединен с выходом памяти хранения степеней «2» в СОК, а выход соединен с шестым входом блока вывода частного, состоящего из элемента ИЛИ блока вывода частного, элемента задержки, удерживающего регистра, n регистров хранения остатка по модулю p_i, n сумматоров по модулю p_i, n мультиплексоров по модулю p_i, n регистров хранения суммы по модулю p_i, n инверторов блока вывода частного, n регистров хранения модуля p_i, n сумматоров блока вывода частного, n регистров хранения обратного значения суммы по модулю p_i, n мультиплексоров выбора суммы, удерживающий регистр знака, регистр хранения суммы в СОК, регистр хранения значения «1», регистр хранения значения «-1», мультиплексор равенства абсолютных величии делимого и делителя, мультиплексор вывода частного, регистр хранения частного, при этом первый выход блока уточнения аппроксимационного ряда соединен с первым входом регистра хранения остатка по модулю p₁, второй и третий входы которого связаны со входом тактового импульса и выходом элемента ИЛИ соответственно, а выход соединен с первым входом сумматора по модулю р₁, выход которого соединен с информационным входом демультиплексора по модулю р₁, управляющий вход которого подключен ко второму выходу блока уточнения аппроксимационного ряда, а второй выход соединен со вторым входом сумматора по модулю p₁, первый выход подключен одновременно ко входу 1-го инвертора, блока вывода частного и первому входу регистра хранения суммы по модулю р₁, второй и третий входы которого связаны со входом тактового импульса и выходом элемента ИЛИ соответственно, выход соединен с первым входом 1-го мультиплексора выбора суммы, второй вход которого соединен с выходом регистра хранения обратного значения суммы по модулю p₁, второй и третий входы которого связаны со входом тактового импульса и выходом элемента ИЛИ соответственно, первый вход соединен с выходом 1-го сумматора блока вывода частного, на третий вход которого постоянно подается логическая единица, второй вход соединен с выходом регистра хранения модуля р₁, первый вход соединен с выходом 1-го инвертора блока вывода частного, первый выход блока уточнения аппроксимационного ряда соединен с первым входом регистра хранения остатка по модулю р₂, второй и третий входы которого связаны со входом тактового импульса и выходом элемента ИЛИ соответственно, а выход соединен с первым входом сумматора по модулю p₂, выход которого соединен с информационным входом демультиплексора по модулю p₂, управляющий вход которого подключен ко второму выходу блока уточнения аппроксимационного ряда, а второй выход соединен со вторым входом сумматора по модулю p₂, первый выход подключен одновременно ко входу 2-го инвертора блока вывода частного и первому входу регистра хранения суммы по модулю р₂, второй и третий входы которого связаны со входом тактового импульса и выходом элемента ИЛИ соответственно, выход соединен с первым входом 2-го мультиплексора выбора суммы, второй вход которого соединен с выходом регистра хранения обратного значения суммы по модулю p₂, второй и третий входы которого связаны со входом тактового импульса и выходом элемента ИЛИ соответственно, первый вход соединен с выходом 2-го сумматора блока вывода частного, на третий вход которого постоянно подается логическая единица, второй вход соединен с выходом регистра хранения модуля р₂, первый вход соединен с выходом 2-го инвертора блока вывода частного, аналогично первый выход блока уточнения аппроксимационного ряда соединен с первыми входами регистров хранения остатка по модулю p_i, и так далее, наконец, первый выход блока уточнения аппроксимационного ряда соединен с первым входом регистра хранения остатка по модулю p_n, второй и третий входы которого связаны со входом тактового импульса и выходом элемента ИЛИ соответственно, а выход соединен с первым входом сумматора по модулю p_n, выход которого соединен с информационным входом демультиплексора по модулю p_n, управляющий вход которого подключен ко второму выходу блока уточнения аппроксимационного ряда, а второй выход соединен со вторым входом сумматора по модулю p_n, первый выход подключен одновременно ко входу n-го инвертора блока вывода частного и первому входу регистра хранения суммы по модулю p_n, второй и третий входы которого связаны со входом тактового импульса и выходом элемента ИЛИ соответственно, выход соединен с первым входом n-го мультиплексора выбора суммы, второй вход которого соединен с выходом регистра хранения обратного значения суммы по модулю p_n, второй и третий входы которого связаны со входом тактового импульса и выходом элемента ИЛИ соответственно, первый вход соединен с выходом n-го сумматора блока вывода частного, на третий вход которого постоянно подается логическая единица, второй вход соединен с выходом регистра хранения модуля p_n, первый вход соединен с выходом n-го инвертора блока вывода частного, первый выход блока вычисления позиционных характеристик соединен с первым входом удерживающего регистра знака, второй и третий входы которого связаны со входом тактового импульса и выходом элемента ИЛИ соответственно, выход одновременно подключен к управляющим входам мультиплексоров выбора суммы и управляющему входу мультиплексора равенства абсолютных величин делимого и делителя, первый вход которого соединен с выходом регистра хранения значения второй вход подключен к регистру хранения значения «1», а выход к первому входу мультиплексора выбора частного, второй вход которого подключен к выходу регистра хранения суммы в СОК, n+1-й и n+2-й входы которого связаны со входом тактового импульса и выходом элемента ИЛИ соответственно, а входы с 1-го по n-й соединены с выходами мультиплексоров выбор f суммы с 1-го по n-й соответственно, управляющий вход мультиплексора вывода частного соединен с выходом удерживающего регистра, второй и третий входы которого связаны со входом тактового импульса и выходом элемента ИЛИ соответственно, первый вход соединен со вторым выходом блока сравнения, который одновременно подключен ко второму входу элемента ИЛИ блока вывода частного, первый вход которого соединен с первым выходом блока сравнения, а выход соединен со входом элемента задержки, выход которого соединен со вторым входом элемента ИЛИ, выход мультиплексора вывода частного соединен с первым входом регистра хранения частного, второй и третий входы которого связаны со входом тактового импульса и выходом элемента ИЛИ соответственно, а выход соединен с выходом вывода частного.This technical result is achieved by the fact that in the device for dividing modular numbers, containing the inputs of the dividend and the divider, the output of the output of the quotient, the unit for calculating the positional characteristics, the shift register, counter, memory storage degrees "2" in the system of residual classes (RNC), and the first output the shift register is connected simultaneously with the first input of the counter and the first input of the memory of storage of degrees "2" in the RNS, the second input of which is connected to the first output of the counter, the inputs of the clock pulse and global reset, OR element, bl ok, approximation row refinement, private output unit, clock input connected to the third input of the positional characteristics calculator, the first input of the approximation row refinement unit and the fifth input of the private output unit, the first output of which is connected to the second input of the OR element, the first input of which is connected to global reset input; the output of the OR element is connected to the fourth input of the positional characteristics calculating unit, the second input of the approximation row refinement unit and the fourth input of the private output unit, the second output of which is the private output output, the sixth and seventh inputs of the private output unit are connected respectively to the first and second outputs of the approximation approximation unit a row, the third and fourth inputs of which are connected to the fifth and fourth outputs of the block for calculating positional characteristics, the first, second and third outputs of which are connected to the first, second and third inputs of the private output unit, and the first and second inputs of the positional characteristic calculating unit are connected to the input of the dividend and the input of the divider, respectively, the positional characteristics unit consisting of a dividend register, a divisor register, n inverters of the dividend unit for calculating positional characteristics, where n is the number of RNS modules, n inverters of the divider of the block for calculating positional characteristics, 2n storage registers of the module p _i; where i = 1, ..., n, 2n registers of storage coefficient k _i , n adders of the divisible unit for calculating the positional characteristics, n adders for the divisor of the unit for calculating the positional characteristics, n first divisible multipliers, n second divisible multipliers, n first divisor multipliers, n second divisor multipliers, the adder of the value F (A), the adder of the value F (-A ), the adder of the value F (B), the adder of the value F (-B), the register for storing the value F (A), the register for storing the value F (-A), the register for storing the value F (B), the register for storing the value F (-B) , XOR element, dividend multiplexer, divider multiplexer and a comparison unit, where the first input of the register of the dividend is connected to the input of the dividend, the second and third inputs are connected to the input of the clock pulse and the output of the OR element, respectively, the 1st output is connected to the input of the 1st inverter of the dividend block for calculating the positional characteristics and the second input 1- th multiplier of positive divisible, the first input of which is connected with the output of the register of storage of coefficient k _one connected simultaneously to the second input of the 1st negative divisible multiplier, the first input of which is connected to the output of the 1st adder of the dividend unit for calculating positional characteristics, the third input of which is constantly supplied with the value of a logical unit, the second input is connected to the output of the 1st inverter of the dividend unit calculating positional characteristics, the first input is connected to the output of the storage register of module p _one , The 2nd output of the dividend register is connected to the input of the 2nd inverter of the dividend unit for calculating positional characteristics and the second input of the 2nd multiplier of the positive dividend, the first input of which is connected to the output of the coefficient storage register k ₂ connected simultaneously to the second input of the 2nd negative divisible multiplier, the first input of which is connected to the output of the 2nd adder of the dividend unit for calculating positional characteristics, the third input of which is constantly supplied with the value of a logical unit, the second input is connected to the output of the 2nd inverter of the dividend block calculating positional characteristics, the first input is connected to the output of the storage register of module p ₂ , similar connections for the rest of the outputs of the dividend register, finally, the nth output of the dividend register is connected to the input of the nth inverter of the dividend unit for calculating positional characteristics and the second input of the nth multiplier of the positive dividend, the first input of which is connected to the output of the coefficient storage register k _n connected simultaneously to the second input of the nth negative divisible multiplier, the first input of which is connected to the output of the nth adder of the dividend unit for calculating positional characteristics, the third input of which is constantly supplied with the value of a logical unit, the second input is connected to the output of the nth inverter of the divisible block calculating positional characteristics, the first input is connected to the output of the storage register of module p _n , the output of the 1st multiplier of the positive dividend is connected to the 1st input of the adder of the value F (A), the output of the 2nd multiplier of the positive dividend is connected to the 1st input of the adder of the value F (A), and so on, finally, the output n- the 1st multiplier of the positive dividend is connected to the nth input of the adder of the value F (A), the output of the 1st multiplier of the negative dividend is connected to the 1st input of the adder of value F (-A), the output of the 2nd multiplier of the negative dividend is connected to the 2nd the input of the adder of the value F (-A), and so on, finally, the output of the nth multiplier of negative cases it is connected to the nth input of the adder of the value F (-A), the first input of the divider register is connected to the input of the divider, the second and third inputs are connected to the input of the clock pulse and the output of the OR element, respectively, the 1st output is connected to the input of the 1st inverter the divider of the block for calculating the positional characteristics and the second input of the 1st multiplier of the positive divider, the first input of which is connected with the output of the storage register of the coefficient k _one connected simultaneously to the second input of the 1st multiplier of the negative divider, the first input of which is connected to the output of the 1st adder of the divider of the positional characteristics calculator, the third input of which is constantly supplied with the value of a logical unit, the second input is connected to the output of the 1st inverter of the divider of the block calculating positional characteristics, the first input is connected to the output of the storage register of the module; the 2nd output of the register of the divider is connected to the input of the 2nd inverter of the divider of the unit for calculating positional characteristics and second the second input of the 2nd multiplier of the positive divider, the first input of which is connected with the output of the coefficient storage register ₂ connected simultaneously to the second input of the 2nd multiplier of the negative divider, the first input of which is connected to the output of the 2nd adder of the divider of the block for calculating positional characteristics, the third input of which is constantly supplied with the value of a logical unit, the second input is connected to the output of the 2nd inverter of the divider of the block calculating positional characteristics, the first input is connected to the output of the storage register of module p ₂ , similar connections to the rest of the outputs of the divider register, finally, the nth output of the divider register is connected to the input of the nth inverter divider of the positional characteristics calculator and the second input of the nth multiplier of the positive divider, the first input of which is connected to the output of the coefficient storage register k _n connected simultaneously to the second input of the nth multiplier of the negative divider, the first input of which is connected to the output of the nth adder of the divider of the block for calculating positional characteristics, the third input of which is constantly supplied with the value of a logical unit, the second input is connected to the output of the nth inverter of the divider of the block calculating positional characteristics, the first input is connected to the output of the storage register of module p _n , the output of the 1st multiplier of the positive divider is connected to the 1st input of the adder of the value F (B), the output of the 2nd multiplier of the positive divider is connected to the 2nd input of the adder of the value F (B), and so on, finally, the output n- the 1st multiplier of the positive divider is connected to the nth input of the adder of the value F (B), the output of the 1st multiplier of the negative divider is connected to the 1st input of the adder of value F (-B), the output of the 2nd multiplier of the negative divider is connected to the 2nd the input of the adder values F (-B), and so on, finally, the output of the nth multiplier of negative div If it is connected to the nth input of the adder of the value F (-B), the output of which is connected to the first input of the storage register of the value F (-B), the second and third inputs of which are connected to the input of the clock pulse and the output of the OR element, respectively, the output is connected to the first the input of the divider multiplexer, the second input of which is connected to the output of the storage register of the value F (B), the second and third inputs of which are connected to the input of the clock pulse and the output of the OR element, respectively, the first input is connected to the first output of the adder of the value F (B), the second output which is simultaneously connected to the second input of the XOR element and the control input of the divider multiplexer, the output of which is the fourth output of the positional characteristics calculating unit and connected to the fourth input of the approximation row refinement unit, and also connected to the second input of the comparison unit, the first input of which is connected to the fifth output of the unit computing positional characteristics and is connected to the third input of the approximation row refinement unit, and is the output of the dividend multiplexer, the control input to is connected to the first input of the XOR element and the second output of the adder of the value F (A), the first output of which is connected to the first input of the storage register of the value F (A), the second and third inputs of which are connected to the input of the clock pulse and the output of the OR element, respectively, and the output connected to the second input of the dividend multiplexer, the first input of which is connected to the output of the value storage register F (-A), the second and third inputs of which are connected to the input of the clock pulse and the output of the OR element, respectively, the first input is connected to the output of the sum Ator values F (-A), XOR element output is the first output of the positional characteristics calculating unit and connected to the first input of the output unit of the private, second and third inputs connected to first and second outputs of the comparator respectively; the approximation row refinement unit contains a shift register, counter, storage register

, the storage register of the decrementable, the multiplexer of the choice of the decremented, the inverter of the refinement unit of the approximation series, the memory of the storage of degrees “2” in the RNS, the adder of the block of refinement of the approximation series, the multiplexer of the choice of the next diminish, the element is NOT, the element AND, and the first input of the shift register is connected to the fourth output unit for calculating positional characteristics, the second and third inputs are connected to the input of the clock pulse and the output of the OR element, respectively, the fourth input is connected to the first output of the counter, the second and the third inputs of which are connected with the input of the clock pulse and the output of the OR element, respectively, the second output is the second output of the approximation row refinement unit and is connected to the seventh input of the private output unit, the first output of the counter is also connected to the control input of the selector multiplexer, the second input of which is connected to the output storage register

, the second and third inputs of which are connected with the input of the clock pulse and the output of the OR element, respectively, the first input is connected to the fifth output of the positional characteristics calculating unit, the first input of the selector of the diminished selection is connected to the output of the storage register of the diminished, the second and third inputs of which are connected to the input of the clock pulse and the output of the OR element, respectively, the first input is connected to the output of the next decremented selection multiplexer, the first input of which is connected to the output of the mind selection multiplexer the second input of which is connected to the first input of the adder of the approximation block refinement, the second input of which is connected to the inverter of the approximation row refinement block, the input of which is connected to the second output of the shift register, the second input of the next reduced multiplexer is connected to the first output of the adder of the approximation approximation block row, the second output of which is connected simultaneously to the control input of the next multiplexer selector to be reduced and the input of the element is NOT, the output is It is connected to the second input of the AND element, the first input of which is connected to the output of the storage memory of degrees “2” in the RNS, and the output is connected to the sixth input of the private output unit, consisting of the OR element of the private output unit, a delay element holding the register, n storage registers remainder modulo p _i , n adders modulo p _i , n multiplexers modulo p _i , n registers of storage of the sum modulo p _i , n inverters of the private output unit, n storage registers of module p _i , n adders of the private output block, n registers for storing the inverse of the sum value modulo p _i , n sum selection multiplexers holding the sign register, the sum storage register in the RNS, the value storage register “1”, the value storage register “-1”, the multiplier of equality of absolute values of the dividend and divisor, the output private multiplexer, the private storage register, while the first the output of the approximation row refinement unit is connected to the first input of the remainder storage register modulo p _one , the second and third inputs of which are connected to the input of the clock pulse and the output of the OR element, respectively, and the output is connected to the first input of the adder modulo p _one the output of which is connected to the information input of the demultiplexer modulo p _one whose control input is connected to the second output of the approximation row refinement unit, and the second output is connected to the second adder input modulo p _one , the first output is connected simultaneously to the input of the 1st inverter, the private output unit and the first input of the sum storage register modulo p _one , the second and third inputs of which are connected to the input of the clock pulse and the output of the OR element, respectively, the output is connected to the first input of the 1st sum selection multiplexer, the second input of which is connected to the output of the storage register of the reciprocal of the sum value modulo p _one , the second and third inputs of which are connected to the input of the clock pulse and the output of the OR element, respectively, the first input is connected to the output of the first adder of the private output unit, the third input of which is constantly supplied with a logical unit, the second input is connected to the output of the storage register of module p _one , the first input is connected to the output of the 1st inverter of the private output unit, the first output of the approximation row refinement unit is connected to the first input of the remainder storage register modulo p ₂ , the second and third inputs of which are connected to the input of the clock pulse and the output of the OR element, respectively, and the output is connected to the first input of the adder modulo p ₂ whose output is connected to the information input of the demultiplexer modulo p ₂ whose control input is connected to the second output of the approximation row refinement unit, and the second output is connected to the second adder input modulo p ₂ , the first output is connected simultaneously to the input of the 2nd inverter of the private output unit and to the first input of the sum storage register modulo p ₂ , the second and third inputs of which are connected to the input of the clock pulse and the output of the OR element, respectively, the output is connected to the first input of the 2nd sum selection multiplexer, the second input of which is connected to the output of the storage register of the reciprocal of the sum value modulo p ₂ , the second and third inputs of which are connected to the input of the clock pulse and the output of the OR element, respectively, the first input is connected to the output of the 2nd adder of the private output unit, the third input of which is continuously supplied with a logical unit, the second input is connected to the output of the storage register of module p ₂ , the first input is connected to the output of the 2nd inverter of the private output unit, similarly, the first output of the approximation row refinement unit is connected to the first inputs of the remainder storage registers modulo p _i and so on, finally, the first output of the approximation row refinement unit is connected to the first input of the remainder storage register modulo p _n , the second and third inputs of which are connected to the input of the clock pulse and the output of the OR element, respectively, and the output is connected to the first input of the adder modulo p _n whose output is connected to the information input of the demultiplexer modulo p _n whose control input is connected to the second output of the approximation row refinement unit, and the second output is connected to the second adder input modulo p _n , the first output is connected simultaneously to the input of the nth inverter of the private output unit and to the first input of the sum storage register modulo p _n , the second and third inputs of which are connected to the input of the clock pulse and the output of the OR element, respectively, the output is connected to the first input of the nth sum selection multiplexer, the second input of which is connected to the output of the storage register of the reciprocal of the sum value modulo p _n , the second and third inputs of which are connected with the input of the clock pulse and the output of the OR element, respectively, the first input is connected to the output of the nth adder of the private output unit, the third input of which is continuously supplied with a logical unit, the second input is connected to the output of the storage register of module p _n , the first input is connected to the output of the nth inverter of the private output unit, the first output of the positional characterization unit is connected to the first input of the character holding register, the second and third inputs of which are connected to the input of the clock pulse and the output of the OR element, respectively, the output is simultaneously connected to the control inputs multiplexers for selecting the sum and the control input of the multiplexer for equality of absolute values of the dividend and the divider, the first input of which is connected to the output of the value storage register; the second input is connected it is accessible to the storage register of the value “1”, and the output to the first input of the private selector multiplexer, the second input of which is connected to the output of the storage register of the sum in the RNS, the n + 1 and n + 2 inputs of which are connected to the clock input and output OR, respectively, and the inputs from the 1st to the nth are connected to the outputs of the multiplexers, the selection f is the sum from the 1st to the nth, respectively, the control input of the private output multiplexer is connected to the output of the holding register, the second and third inputs of which are connected to the input clock pulse and element output LI, respectively, the first input is connected to the second output of the comparison unit, which is simultaneously connected to the second input of the OR element of the private output unit, the first input of which is connected to the first output of the comparison unit, and the output is connected to the input of the delay element, the output of which is connected to the second input of the OR element , the output of the private output multiplexer is connected to the first input of the private storage register, the second and third inputs of which are connected to the input of the clock pulse and the output of the OR element, respectively, and the output is connected to output private output.

This device for dividing modular numbers is illustrated by figures 1-4. The figure 1 shows a General view of the device for dividing modular numbers, which contains the input of the clock pulse 1, the input of the global reset 2, the input of the dividend 3, the input of the divider 4, the element OR 5, the unit for calculating the positional characteristics 6, the refinement unit of the approximation series 7, the output unit private 8 and output output private 9.

The figure 2 shows the positional characteristic computing unit 6, which contains a register of divisible 10, n dividend inverters 11.1-11.n positional computing unit, n storage registers of the module p _i 12.1-12.n, where i = 1, ..., n, n coefficient storage registers k _i 13.1-13.n, n dividend adders 14.1-14.n positional characteristic calculator 6, n negative dividend multipliers 15.1-15.n, n positive dividend multipliers 16.1-16.n, adder F ( A) 17, the adder of the value F (-A) 18, the storage register of the value F (-A) 19, the storage register of the value F (A) 20, reg p divider 21, n 22.1-22.n divisor calculation unit inverters positional characteristics, n registers storing module p _i 23.1-23.n, n registers storing coefficient k _i 24.1-24.n, n adders divider unit 25.1-25.n calculating the positional characteristics 6, n of the multiplier of the negative divider 26.1-26.n, n of the multipliers of the positive divider 27.1-27.n, the adder of the value F (B) 28, the adder of the value F {(- B) 29, the storage register of the value F (- B ) 30, the storage register of the value F (B) 31, the XOR 32 element, the dividend multiplexer 33, the divider multiplexer 34, the comparison unit 35.

38, регистр хранения уменьшаемого 39, мультиплексор выбора уменьшаемого 40, инвертор 41 блока уточнения аппроксимационного ряда 7, память хранения степеней «2» в СОК 42, сумматор 43 блока уточнения аппроксимационного ряда 7, мультиплексор выбора следующего уменьшаемого 44, элемент НЕ 45, элемент И 46.The figure 3 shows the refinement unit of the approximation row 7, which contains a shift register 36, a counter 37, a storage register

38, storage register reduced 39, selection multiplexer 40, inverter 41 of the approximation row refinement unit 7, memory for storing degrees “2” in the RNS 42, adder 43 of the approximation row refinement block 7, the next reducible selector 44, element NOT 45, element 45, element AND 46.

The figure 4 shows a private output unit, consisting of an OR element 47 of a private 8 output unit, a delay element 48, a holding register 49, n balance storage registers modulo p _i 50.1-50.n, n adders modulo p _i 51.1-51. n, n demultiplexers modulo p _i 52.1-52.n, ha of storage registers of the sum modulo p _i 53.1-53.n, n inverters 54.1-54.n of the output unit private 8, n registers of storage of the module p _i 55.1-55. n, n adders 56.1-56.n output unit, the private 8, n registers storing the reciprocal of the sum modulo p _i 57.1-57.n, n multiplexers 58.1-58.n amount selection registers of retaining and mark 59, the amount of storage in the CSB register 60, the register storing "1" 61, storage register value "-1" 62, multiplexer equality greatness absolute dividend and divisor 63, the multiplexer 64 output private, the private storage register 65.

The clock pulse necessary to control the operation of the registers and counters from the input of the clock pulse 1 is fed to the third input of the block, calculating the positional characteristics 6, pa the first input of the refinement block of approximation series 7 and to the fifth input of the private output block 8.

. С выхода элемента ИЛИ 5 сигнал сброса поступает на четвертый вход блока вычисления позиционных характеристик 6, на второй вход блока уточнения аппроксимационного ряда 7 и на четвертый вход блока вывода частного 8.The global reset signal from the input of global reset 2 goes to the first input of the OR element 5, the second input of which from the first output of the output unit of private 8 receives the interrupt signal division, which is formed when

. From the output of the OR element 5, the reset signal is fed to the fourth input of the positional characteristics calculating unit 6, to the second input of the refinement unit of the approximation row 7 and to the fourth input of the private output unit 8.

The values of divisible A and divisor B, presented in the RNC by the modules p ₁ , p ₂ , ..., p _n , come from the input of the divisible 3 and the input of the divider 4 pa the first and second inputs of the block for calculating positional characteristics 6, respectively.

и

происходит определение знаков делимого А и делителя В, которые участвуют в вычислении знака частного Q, который подается с первого выхода блока вычисления позиционных характеристик 6 на первый вход блока вывода частного 8. На основе определения знаков делимого А и делителя В блок вычисления позиционных характеристик 6 выбирает необходимые значения

и

, которые с пятого и четвертого выходов блока вычисления позиционных характеристик 6 соответственно поступают на третий и четвертый входы блока уточнения аппроксимационного ряда 7. Также на основе значений

и

происходит вычисления значений неравенств

и

, которые со второго и третьего выходов блока вычисления позиционных характеристик 6 соответственно поступают на второй и третий входы блока вывода частного 8.For the correct division to be performed, it is necessary to perform calculations on the absolute values, but since it is impossible to determine the sign in the RNS without additional actions, the unit for calculating the positional characteristics 6 finds both F (A) and F (-A), F (B) and F (-B ) In the process of calculating

and

the signs of divisible A and divisor B are determined, which are involved in calculating the quotient of the quotient Q, which is fed from the first output of the positional characteristics calculator 6 to the first input of the quotient 8 output unit. Based on the definition of the divisible A and divisor B characters, the positional calculator 6 selects required values

and

which, from the fifth and fourth outputs of the block for calculating the positional characteristics 6, respectively, are supplied to the third and fourth inputs of the refinement block of the approximation series 7. Also based on the values

and

the inequalities are calculated

and

which, from the second and third outputs of the block for calculating the positional characteristics 6, respectively, are supplied to the second and third inputs of the output unit of the private 8.

The refinement unit of approximation row 7 calculates the powers of “2”, which are included in the representation on the base “2” of the private Q and sends them from the first output of the refinement unit of approximation row 7 to the sixth input of the output unit of private 8. The second output of the refinement unit of approximation row 7 is fed the signal of the end of the shift register 36, which signals that all degrees "2" included in the representation of the private Q are checked. This signal is fed to the seventh input of the private output unit 8.

на первый выход блока вывода частного 8 подается сигнал сброса, который приводит к появлению на выходе вывода частного 9 значения «0». В случае поступления на третий вход блока вывода частного 8 сигнала

па первый выход блока вывода частного 8 подается сигнал сброса, который сбрасывает значения регистров и счетчиков, на выход вывода частного 9 подается значения «±1» в зависимости от значения знака частного с первого входа блока вывода частного 8.The output unit of private 8 summarizes the degrees “2” received at the sixth input and gives them to the second input of the output unit of private 8, which is the output of the output of private 9 and contains the value of private Q. In the case of the input to the second input of the output unit of private 8, the signal

a reset signal is applied to the first output of the private 8 output unit, which leads to the appearance of the value “0” at the output of the private 9 output. In case of receipt of a private 8 signal at the third input of the output unit

pa the first output of the private 8 output block sends a reset signal that resets the values of the registers and counters, the output of the private 9 output receives the value "± 1" depending on the sign of the private from the first input of the private 8 output block.

The value of dividend A from the input of dividend 3 is received at the first input of the register of dividend 10, the second and third inputs of which receive clock signals and a reset signal from the input of clock pulse 1 and the output of the OR element 5, respectively. The values of the residuals for each module a _i = A mod p _i arrive at the corresponding n outputs of the register divisible by 10, where p ₁ , p ₂ , ..., p _i , ..., p _n are the RNS modules.

The remainder a ₁ in the first module from the first output of the register of divisible 10 goes simultaneously to the input of the 1st inverter of divisible 11.1 unit for calculating positional characteristics 6 and the second input of the 1st multiplier of positive divisible 16.1, the inverted value from the output of the 1st inverter of divisible 11.1 the second input of the 1st adder of the divisible 14.1 unit for calculating the positional characteristics 6, the first input of which from the output of the storage register of the module p ₁ 12.1 receives the value of the module p ₁ , and the logical unit is constantly fed to the third input, which corresponds to There is a subtraction operation and obtaining the value - a ₁ . The value from the output of the 1st adder of the divisible 14.1 unit for calculating the positional characteristics 6 is supplied to the first input of the 1st multiplier of the negative divisible 15.1. the second input of which receives the value of the coefficient k ₁ from the register of storage of the coefficient k ₁ 13.1, which is simultaneously fed to the first input of the 1st multiplier of the positive dividend 16.1.

Similar operations occur with each remainder a _i modulo p _i . Finally, the remainder a _n in the nth module from the nth output of the register of divisible 10 is fed simultaneously to the input of the nth inverter of the divisible 11.n unit for calculating positional characteristics 6 and the second input of the nth multiplier of the positive divisible 16.n, inverted value from the output of the nth inverter of the dividend 11.n goes to the second input of the nth adder of the dividend 14.n of the block for calculating positional characteristics 6, the first input of which from the output of the storage register of the module p _n 12.n receives the value of the module p _n , and the third input is constantly fed a logical unit, which corresponds to exists a subtraction operation and obtaining values - a _{n ..} The value output from the n-th adder of the dividend calculation unit 14.n positional characteristics 6 is supplied to a first input of n-th multiplier negative dividend 15.n, the second input of which the value of the coefficient k _n from the register of storage of the coefficient k _n 13.n, which is simultaneously fed to the first input of the nth multiplier of positive divisible 16.n.

на выход мультиплексора делимого 33, которое поступает на пятый выход блока вычисления позиционных характеристик 6 и на первый вход блока сравнения 35.Further, the values from the multipliers of the negative dividend 15.1-15.n are fed to the adder of the value F (-A) 18, from where the data are fed to the first input of the storage register of the value F (-A) 19, the second and third inputs of which receive clock signals and a reset signal where the data comes from at the first input of the divisible 33 multiplexer; the values from the multipliers of the positive dividend 16.1-16.n are fed to the adder of the value F (A) 17, from the first output of which the data are fed to the first input of the storage register of the value F (A) 20, the second and third inputs of which receive clock signals and a reset signal , and from the output, the data goes to the second input of the divisible 33 multiplexer; from the second output of the adder of the value F (A) 17, the sign value is supplied to the control input of the dividend 33 multiplexer and the first input of the XOR 32 element. Depending on the sign of F (A), the dividend 33 multiplexer supplies the value from the first or second input

the output of the divisible 33 multiplexer, which is fed to the fifth output of the positional characteristics calculating unit 6 and to the first input of the comparison unit 35.

The value of the divider B from the input of the divider 4 is fed to the first input of the register of the divider 21, the second and third inputs of which receive clock signals and a reset signal. The values of the residuals for each module b _i = В mod p _i go to the corresponding n outputs of the register of the divider 21, where p ₁ , p ₂ , ..., p _n are the modules of the RNS.

The remainder b ₁ in the first module from the first output of the register of the divider 21 is fed simultaneously to the input of the 1st inverter of the divider 22.1 of the block for calculating the positional characteristics 6 and the second input of the 1st multiplier of the positive divider 27.1, the inverted value from the output of the 1st inverter of the divider 22.1 positional characteristics 6 is supplied to a second input of the 1st adder divisor calculation unit 25.1 positional characteristics 6, in which the first input from the output of storage register module ₁ 23.1 p value p ₁ enters the module, and a third input position stantly supplied logical unit that corresponds to the operation of subtraction and obtaining the value -b _1. The value from the output of the 1st adder of the divider 25.1 of the block for calculating the positional characteristics 6 is supplied to the first input of the 1st multiplier of the negative divider 26.1, the second input of which receives the coefficient k ₁ from the storage register of the coefficient k ₁ 24.1, which is simultaneously fed to the first input 1st multiplier of the positive divisor 27.1.

Similar operations occur with each b _i residue modulo p _i. Finally, the remainder b _n in the nth module from the nth output of the register of the divider 21 is simultaneously input to the nth inverter of the divider 22.n of the positional characteristics calculator 6 and the second input of the nth multiplier of the positive divider 27.n, the inverted value output from the n-th inverter divisor calculation unit 22.n positional characteristics 6 is supplied to a second input n-th adder divisor calculation unit 25.n positional characteristics 6, to a first input of which the output p _n 23.n module storage register receives modulus p _n, and a third input position stantly supplied logical unit that corresponds to the operation of subtraction and obtaining values - b _n. The value from the output of the n-th adder of the divider 25.n of the block for calculating the positional characteristics 6 is supplied to the first input of the n-th multiplier of the negative divider 26.n, the second input of which receives the coefficient k _n from the storage register of the coefficient k _n 24.n, which simultaneously fed to the first input of the nth multiplier of the positive divisor 27.n.

на выход мультиплексора делителя 34, которое поступает на четвертый выход блока вычисления позиционных характеристик 6 и на второй вход блока, сравнения 35.Further, the values from the multipliers of the negative divider 26.1-26.n are fed to the adder of the value F (- B) 29, from where the data are fed to the first input of the storage register of the value F (- B) 30, the second and third inputs of which receive clock signals and a reset signal where the data comes from at the first input of the multiplexer divider 34; the values from the multipliers of the positive divider 27.1-27.n are fed to the adder of the value F (B) 28, from the first output of which the data are fed to the first input of the storage register of the value F (B) 31, the second and third inputs of which receive clock signals and a reset signal , and from the output, the data goes to the second input of the divisible 34 multiplexer; from the second output of the adder of the value F (B) 28, the sign value is supplied to the control input of the divider 34 multiplexer and the second input of the XOR 32 element. Depending on the sign of F (B), the divider 34 multiplexer supplies the value from the first or second input

the output of the multiplexer divider 34, which is fed to the fourth output of the unit for calculating positional characteristics 6 and to the second input of the unit, comparison 35.

Based on the values received at the first and second inputs, the XOR 32 element outputs the value of the private Q, which from the first output of the block for calculating the positional characteristics 6 goes to the first input of the block, the output of the private 8.

и

, поступившие па первый и второй входы блока сравнения 35 соответственно, сравниваются и в случае равенства на второй выход блока сравнения 35, который является третьим выходом блока вычисления позиционных характеристик 6, подается значение

. В случае, когда

на первый выход блока сравнения 35, который является вторым выходом блока вычисления позиционных характеристик 6, подается значение

.Values

and

received on the first and second inputs of the comparison unit 35, respectively, are compared and in case of equality to the second output of the comparison unit 35, which is the third output of the unit for calculating the positional characteristics 6, the value

. In the case when

to the first output of the comparison unit 35, which is the second output of the positional characteristic calculating unit 6, a value is supplied

.

, на второй и третий входы поступают тактовые сигналы и сигнал сброса, на четвертый вход поступают сигналы сдвига влево с первого выхода счетчика 37. При поступлении на первый вход регистр сдвига 36 значения

регистр сдвига 36 начинает сдвигать значение

вправо, посылая с первого выхода сигнал сдвига на первый вход памяти хранения степеней «2» в СОК 42 и на первый вход счетчика 37, на второй и третий входы которого поступают тактовые сигналы и сигнал сброса. Сдвиг вправо происходит до появления в крайнем левом разряде «1», что соответствует наивысшей степени вхождения «2» в двоичное представление частного Q, после чего счетчик 37 начинает обратный отсчет, отправляя с первого выхода сигналы сдвига влево на второй вход памяти хранения степеней «2» в СОК 42, на управляющий вход мультиплексора выбора уменьшаемого 40 и на четвертый вход регистр сдвига 36, который начинает со второго выхода посылать значение

на вход инвертора 41 блока уточнения аппроксимационного ряда 7, выход которого соединен со вторым входом сумматора 43 блока уточнения аппроксимационного ряда 7. При окончании обратного отсчета счетчиком 37 на втором выходе формируется сигнал окончания работы регистра сдвига 36.At the first input of the shift register 36 from the fourth output of the unit for calculating the positional characteristics 6 receives the value

, the second and third inputs receive clock signals and a reset signal, the fourth input receives left shift signals from the first output of the counter 37. When received at the first input, shift register 36 values

shift register 36 begins to shift the value

to the right, sending a shift signal from the first output to the first input of the memory of storage of degrees “2” in the RNS 42 and to the first input of the counter 37, the second and third inputs of which receive clock signals and a reset signal. A shift to the right occurs until “1” appears in the leftmost digit, which corresponds to the highest degree of occurrence of “2” in the binary representation of quotient Q, after which counter 37 starts the countdown, sending left shift signals from the first output to the second input of the storage of degrees “2” "In the SOK 42, to the control input of the selector of the selectable 40 and the fourth input shift register 36, which starts to send a value from the second output

to the input of the inverter 41 of the refinement unit of the approximation row 7, the output of which is connected to the second input of the adder 43 of the refinement unit of the approximation row 7. At the end of the countdown, the counter 37 generates a signal to the end of the shift register 36 at the second output.

поступает на первый вход регистра хранения

38, на второй и третий входы которого поступают тактовые сигналы и сигнал сброса, выход которого соединен со вторым входом мультиплексора выбора, уменьшаемого 40, первый вход которого соединен с выходом регистра хранения уменьшаемого 39, на второй и третий входы которого поступают тактовые сигналы и сигнал сброса. Выход мультиплексора выбора уменьшаемого 40 соединен с первым входом мультиплексора выбора следующего уменьшаемого 44 и первым входом сумматора 43 блока уточнения аппроксимационного ряда 7, второй выход которого соединен с управляющим входом мультиплексора выбора следующего уменьшаемого 44 и входом элемента НЕ 45. Первый выход сумматора 43 блока уточнения аппроксимационного ряда. 7 соединен со вторым входом мультиплексора выбора следующего уменьшаемого 44, выход которого соединен со входом регистра хранения уменьшаемого 39.Value

goes to the first input of the storage register

38, the second and third inputs of which receive clock signals and a reset signal, the output of which is connected to the second input of the selector, decrementable 40, the first input of which is connected to the output of the storage register decremented 39, the second and third inputs of which receive clock signals and the reset signal . The output of the selectable redux 40 multiplier is connected to the first input of the next selectable 44 selector multiplexer and the first input of the adder 43 of the approximation row refinement unit 7, the second output of which is connected to the control input of the next reduce 44 selector multiplexer and the input of the element NOT 45. The first output of the adder 43 of the approximation approximation block row. 7 is connected to the second input of the next decremented selector 44, the output of which is connected to the input of the decrementable storage register 39.

Under the action of the signals from the first input, the storage of degrees “2” in the RNS 42 starts calculating the highest degree “2” included in the binary representation Q, and under the action of the left shift signal, from the second input it starts sending values of degrees 2 to the first input of the And element 46, represented in the JUICE. At the second input of the AND element 46, a signal is received from the output of the element NOT 45, and the output is the first output of the refinement unit of the approximation series 7 and is connected to the sixth input of the private output unit 8.

поступает на первый вход элемента ИЛИ 47 блока вывода частного 8. С третьего выхода блока вычисления позиционных характеристик 6 сигнал

поступает на второй вход элемента ИЛИ 47 блока вывода частного 8 и первый вход удерживающего регистра 49, на второй и третий входы которого поступают тактовые сигналы и сигнал сброса, а с выхода сигнал подается на управляющий вход мультиплексора вывода частного 64. С выхода элемента ИЛИ 47 сигнал поступает на элемент задержки 48, откуда подается на первый выход блока вывода частного 8.From the second output of the block for calculating positional characteristics 6 signal

arrives at the first input of the OR element 47 of the output unit of private 8. From the third output of the unit for calculating positional characteristics 6, the signal

goes to the second input of the OR element 47 of the output unit of private 8 and the first input of the holding register 49, the second and third inputs of which receive the clock and reset signal, and the output signal is fed to the control input of the multiplexer of the output of the private 64. From the output of the OR element 47, the signal arrives at the delay element 48, from where it is fed to the first output of the private output unit 8.

From the first output of the refinement block of the approximation series 7 of degree “2”, included in the binary representation of the private Q and represented in the RNC for each module p _i , are fed to the first inputs of the corresponding remainder storage registers modulo p _i 50.1-50.n.

The remainder of degree “2” modulo p _{1 is} fed to the first input of the remainder register of the remainder modulo p ₁ 50.1, the second and third inputs of which receive clock signals and a reset signal. The value from the output of the remainder storage register modulo p ₁ 50.1 is supplied to the first adder input modulo p ₁ 51.1. The sum received by the adder modulo p ₁ 51.1 is fed to the information input of the demultiplexer modulo p ₁ 52.1, to the control input of which from the second output of the refinement unit of approximation series 7 the signal ends the shift register 36. If the signal ends the shift register 36 to the control the demultiplexer input modulo p ₁ 52.1 does not arrive, then the demultiplexer modulo p ₁ 52.1 supplies the value from the output of the adder modulo p ₁ 51.1 to the second input of the adder modulo p ₁ 51.1. In the event that the control input of the demultiplexer modulo p ₁ 52.1 appears, the signal from the shift register 36 ends the value of the sum from the adder modulo p ₁ 51.1 is fed to the input of the 1st inverter 54.1 of the private output unit 8 and the first input of the storage register modulo p ₁ 53.1 , the second and third inputs of which receive clock signals and a reset signal. From the output of the storage register of the sum modulo p ₁ 53.1, the signal is supplied to the first input of the 1st multiplexer for selecting the sum 58.1. From the output of the 1st inverter 54.1 of the private 8 output unit, the signal is fed to the first input of the 1st adder 56.1 of the private 8 output unit, the second input of which receives the module value from the module storage register p ₁ 55.1, and the logical unit signal is constantly fed to the third input . From the output of the 1st adder 56.1 of the private 8 output unit, the signal is fed to the first input of the inverse value storage register modulo p ₁ 57.1, the second and third inputs of which receive clock signals and a reset signal. From the output of the storage register of the reciprocal of the value of the sum modulo p ₁ 57.1, the signal is fed to the second input of the 1st sum selection multiplexer 58.1 from where the signal is fed to the 1st input of the storage register of the sum in JUICE 60 depending on the sign of the private Q that comes from the first output unit for calculating positional characteristics 6 to the first input of the holding register of sign 59, to the second and third input of which clock signals and a reset signal are received, and from the output the signal goes to the control inputs of the selection multiplexers of the sum 58.1-58.n and to the control input q multiplexer of equality of absolute values of the dividend and divisor 63.

Similarly, calculations occur for all modules p _i .

Finally, the remainder of degree “2” modulo p _{n is} fed to the first input of the remainder register of the remainder modulo p _n 50.n, the second and third inputs of which receive clock signals and a reset signal. The value from the output of the remainder storage register modulo p _n 50.n is supplied to the first adder input modulo p _n 51.n. The sum received by the adder modulo p _n 51.n is fed to the information input of the demultiplexer modulo p _n 52.n, to the control input of which from the second output of the approximation row refinement unit 7 the shift register 36 ends the signal. If the register ends the signal shift 36 to the control input of the demultiplexer modulo p _n 52.n is not received, then the demultiplexer modulo p _n 52.n supplies the value from the output of the adder modulo p _n 51.n. pa the second adder input modulo p _n 51.n. In the case of the appearance at the control input of the demultiplexer modulo p _n 52.n the signal of the end of the shift register 36, the value of the sum from the adder modulo p _n 51.n is fed to the input of the nth inverter 54.n. private output unit 8 and the first input of the sum storage register modulo p _n 53.n to the second and third inputs of which clock signals and a reset signal are received. From the output of the storage register of the sum modulo p _n 53.n, the signal is supplied to the first input of the nth multiplexer for selecting the sum 58.n. From the output of the nth inverter 54.n of the private 8 output unit, the signal goes to the first input of the nth adder 56.n of the private 8 output unit, the second input of which receives the module value from the module storage register p _n 55.n, and to the third the input is constantly fed a signal of a logical unit. From the output of the nth adder 56.n of the private 8 output unit, the signal is fed to the first input of the inverse value storage register modulo p _n 57.n, the second and third inputs of which receive clock signals and a reset signal. From the output of the storage register of the inverse of the value of the sum modulo p _n 57.n, the signal goes to the second input of the nth sum selection multiplexer 58.n from where the signal goes to the nth input of the storage register of the sum in the RNS 60 depending on the sign of the private Q, which comes from the output of the holding register of the sign 59.

Upon receipt of the private Q sign from the output of the holding register of the sign 59 to the control input, the multiplexer for equality of absolute values of the dividend and the divisor 63, depending on the sign, the output receives the value “1” from the first input, which is stored in the RNS, which is stored in the storage register of the value “1” 61 or from the second input, the value "-1" represented in the RNS, which is stored in the storage register of the value "-1" 62.

поступает на управляющий вход мультиплексора вывода частного 64, на первый вход поступает в зависимости от знака частного Q значение «1» или с мультиплексора равенства абсолютных величии делимого и делителя 63, а па второй вход сигнал с регистра хранения суммы в СОК 60. С выхода мультиплексора вывода частного 64 значение поступает на первый вход регистра хранения частного 65, на второй и третий входы которого поступают тактовые сигналы и сигнал сброса, а на выход регистра хранения частного 65, который является вторым выходом блока вывода частного 8 и выходом вывода частного 9, поступает значение частного, представленное в СОК.From the output of the holding register 49 signal

it goes to the control input of the private 64 output multiplexer, the first input receives the value “1” depending on the quotient of the private Q, or from the multiplexer of equality of absolute magnitude of the dividend and the divisor 63, and the second input receives the signal from the storage register of the sum in the RNS 60. From the output of the multiplexer of the output of private 64, the value goes to the first input of the private storage register 65, the second and third inputs of which receive clock signals and a reset signal, and to the output of the private storage register 65, which is the second output of the private about 8 and the output of the output of private 9, the value of the private, presented in the JUICE, comes in.

. Для записи чисел будем использовать как двоичное представление, так и десятичную запись, если это не изменит суть вычислений. Поскольку модулей СОК четыре, то в предлагаемом устройстве n=4. Коэффициенты, записанные в регистры хранения коэффициентов k_i 13.1-13.4, 24.1-24.4 равныConsider an example of the implementation of a modular division device for a system of residual classes {2,3,5,7} with an accuracy of N = 20. The dynamic range of this RNS P = 210, in this case, the numbers satisfying the inequality will be fed to the inputs of divisible 3 and divider 4

. To write numbers, we will use both binary representation and decimal notation, if this does not change the essence of the calculations. Since there are four SOK modules, then in the proposed device n = 4. The coefficients recorded in the registers of coefficients k _i 13.1-13.4, 24.1-24.4 are equal

,

,

,

,

,

,

.

.

Before starting work, the input of global reset 2 receives a reset signal, which leads all the registers, counters, etc. in bullet condition. Let the value A = 1 = (1,1,1,1) be fed to the input of divisible 3, and the value B = 1 = (1,1,1,1) be fed to the input of the divisor 4. At the first clock, these values of the dividend and divider are recorded in the registers of the dividend 10 and divider 21 of the unit for calculating the positional characteristics 6, respectively.

On the second clock, the remainder a ₁ = 1 in the first module from the 1st output of the register of divisible 10 goes simultaneously to the input of the 1st inverter of the divisible 11.1 unit for calculating positional characteristics 6 and the second input of the 1st multiplier of the positive divisible 16.1. The inverted value from the output of the 1st inverter of the divisible 11.1 unit for calculating the positional characteristics 6 is supplied to the second input of the 1st adder of the divisible 14.1 unit for calculating the positional characteristics 6, the first input of which from the storage register of the module p ₁ 12.1 receives the value of the module "2", and the logical unit is constantly fed to the third input, which corresponds to the subtraction operation and obtaining the value “1”. The value from the output of the 1st adder of the dividend 14.1 of the block for calculating the positional characteristics 6 is supplied to the first input of the 1st multiplier of the negative dividend 15.1, the second input of which receives the coefficient value "1000 0000 0000 0000 0000" from the register of coefficient k ₁ 13.1, which is simultaneously served on the first input of the 1st multiplier of the positive dividend 16.1. The values of the 1 multipliers of the negative dividend 15.1 and the positive dividend 16.1 are "1000 0000 0000 0000 0000".

The remainder a ₂ = 1 in the second module from the 2nd output of the register of divisible 10 goes simultaneously to the input of the 2nd inverter of the divisible 11.2 unit for calculating positional characteristics 6 and the second input of the 2nd multiplier of the positive divisible 16.2. The inverted value from the output of the 2nd inverter of the divisible 11.2 unit for calculating the positional characteristics 6 goes to the second input of the 2nd adder of the divisible 14.2 unit for calculating the positional characteristics 6, the first input of which from the storage register of the module p ₂ 12.2 receives the value of the module "3", and the logical unit is constantly fed to the third input, which corresponds to the subtraction operation and obtaining the value “2”. The value from the output of the 2nd adder of the divisible 14.2 unit for calculating the positional characteristics 6 is supplied to the first input of the 2nd multiplier of the negative divisible 15.2, the second input of which receives the coefficient value "0101 0101 0101 0101 0101" from the register of coefficient k ₂ 13.2, which is simultaneously the first input of the 2nd multiplier of positive divisible 16.2 is also fed. Then the value at the output of the 2nd multiplier of the positive dividend 16.2 is "0101 0101 0101 0101 0101", and the output of the 2nd multiplier of the negative dividend 15.2 is "1010 1010 1010 1010 1010".

The remainder a ₃ = 1 in the third module from the 3rd output of the register of divisible 10 enters simultaneously the input of the 3rd inverter of the divisible 11.3 unit for calculating positional characteristics 6 and the second input of the 3rd multiplier of the positive divisible 16.3. The inverted value from the output of the 3rd inverter of the divisible 11.3 unit for calculating the positional characteristics 6 is supplied to the second input of the 3rd adder of the divisible 14.3 unit for calculating the positional characteristics 6, the first input of which from the storage register of the module p ₃ 12.3 receives the value of the module “5”, and the logical unit is constantly fed to the third input, which corresponds to the subtraction operation and obtaining the value “4”. The value from the output of the 3rd adder of the divisible 14.3 unit for calculating the positional characteristics 6 is supplied to the first input of the 3rd multiplier of the negative divisible 15.3, the second input of which receives the coefficient value "1001 1001 1001 1001 1001" from the register of the coefficient k ₃ 13.3, which is simultaneously served on the first input of the 3rd multiplier of the positive dividend 16.3. Then the value at the output of the 3rd multiplier of the positive dividend 16.3 is “1001 1001 1001 1001 1001”, and the output of the 3rd multiplier of the negative dividend 15.3 is “0110 0110 0110 0110 0100”.

The remainder a ₄ = 1 in the fourth module from the 4th output of the register of divisible 10 enters simultaneously the input of the 4th inverter of the divisible 11.4 unit for calculating positional characteristics 6 and the second input of the 4th multiplier of the positive divisible 16.4. The inverted value from the output of the 4th inverter of the divisible 11.4 unit for calculating the positional characteristics 6 is supplied to the second input of the 4th adder of the divisible 14.4 unit for calculating the positional characteristics 6, the first input of which from the storage register of the module p ₄ 12.4 receives the value of the module “7”, and the logical unit is constantly fed to the third input, which corresponds to the subtraction operation and obtaining the value “6”. The value from the output of the 4th adder of the dividend 14.4 of the block for calculating the positional characteristics 6 is supplied to the first input of the 4th multiplier of the negative dividend 15.4, the second input of which receives the coefficient value "1001 0010 0100 1001 0010" from the storage register of the coefficient k ₄ 13.4, which is simultaneously served on the first input of the 4th multiplier of the positive dividend 16.4. Then the value at the output of the 4th multiplier of positive dividend 16.4 is "1001 0010 0100 1001 0010", and the output of the 4th multiplier of negative divisible 15.4 is "0110 1101 1011 0110 1100".

The values of the multipliers of the negative dividend 15.1-15.4 go to the adder of the value F (-A) 18, from where the value "1111 1110 1100 0111 1010" is fed to the storage register of the value F (-A) 19; the values from the multipliers of the positive dividend 16.1-16.4 go to the adder of the value F (A) 17, from the first output of which the value "0000 0001 0011 1000 0000" is fed to the first input of the storage register of the value F (A) 20; from the second output of the adder of the value F (A) 17, the value of the sign "0" is fed to the control input of the divisor 33 multiplexer and the first input of the XOR 32 element.

The remainder b ₁ = 1 in the first module from the 1st output of the register of the divider 21 is fed simultaneously to the input of the 1st inverter of the divider 22.1 of the block for calculating positional characteristics 6 and the second input of the 1st multiplier of the positive divider 27.1. The inverted value from the output of the 1st inverter of the divider 22.1 of the block for calculating the positional characteristics 6 goes to the second input of the 1st adder of the divider 25.1 of the block for calculating the positional characteristics 6, the first input of which from the storage register of the module p ₁ 23.1 receives the value of the module "2", and the logical unit is constantly fed to the third input, which corresponds to the subtraction operation and obtaining the value “1”. The value from the output of the 1st adder of the divider 25.1 of the block for calculating the positional characteristics 6 is supplied to the first input of the 1st multiplier of the negative divider 26.1, the second input of which receives the coefficient value "1000 0000 0000 0000 0000" from the register of the coefficient k ₁ 24.1. which is simultaneously fed to the first input of the 1st multiplier of the positive divisor 27.1. The values of the 1 multipliers of the negative divisor 26.1 and the positive divisor 27.1 are "1000 0000 0000 0000 0000".

The remainder b ₂ = 1 in the second module from the 2nd output of the register of the divider 21 is fed simultaneously to the input of the 2nd inverter of the divider 22.2 of the block for calculating positional characteristics 6 and the second input of the 2nd multiplier of the positive divider 27.2. The inverted value from the output of the 2nd inverter of the divider 22.2 of the block for calculating the positional characteristics 6 goes to the second input of the 2nd adder of the divider 25.2 of the block for calculating the positional characteristics 6, the first input of which from the storage register of the module p ₂ 23.2 receives the value of the module "3", and the logical unit is constantly fed to the third input, which corresponds to the subtraction operation and obtaining the value “2”. The value from the output of the 2nd adder of the divider 25.2 of the block for calculating the positional characteristics 6 is supplied to the first input of the 2nd multiplier of the negative divider 26.2, the second input of which receives the coefficient value "0101 0101 0101 0101 0101" from the register of coefficient k ₂ 24.2, which is simultaneously served on the first input of the 2nd multiplier of the positive divider 27.2. Then the value at the output of the 2nd multiplier of the positive divider 27.2 is "0101 0101 0101 0101 0101", and the output of the 2nd multiplier of the negative divider 26.2 is "1010 1010 1010 1010 1010".

The remainder b ₃ = 1 in the third module from the 3rd output of the register of the divider 21 is fed simultaneously to the input of the 3rd inverter of the divider 22.3 of the block for calculating positional characteristics 6 and the second input of the 3rd multiplier of the positive divider 27.3. Inverted output value. Of the 3rd inverter of the divider 22.3 of the unit, calculating the positional characteristics 6 is supplied to the second input of the 3rd adder of the divider 25.3 of the unit of calculating the positional characteristics 6, the first input of which from the storage register of the module p ₃ 23.3 receives the value of the module "5", and the third input a logical unit is constantly supplied, which corresponds to the subtraction operation and obtaining the value "4". The value from the output of the 3rd adder of the divider 25.3 of the block for calculating the positional characteristics 6 is fed to the first input of the 3rd multiplier of the negative divider 26.3, the second input of which receives the coefficient value "1001 1001 1001 1001 1001" from the register of coefficient k ₃ 24.3, which is simultaneously served on the first input of the 3rd multiplier of the positive divisor 27.3. Then the value at the output of the 3rd multiplier of the positive divisor 27.3 is “1001 1001 1001 1001 1001”, and the output of the 3rd multiplier of the negative divisor 26.3 is “0110 0110 0110 0110 0100”.

The remainder b ₄ = 1 in the fourth module from the 3rd output of the register of the divider 21 enters simultaneously the input of the 4th inverter of the divider 22.4 of the block for calculating the positional characteristics 6 and the second input of the 4th multiplier of the positive divider 27.4. The inverted value from the output of the 4th inverter of the divider 22.4 of the unit, calculating the positional characteristics 6 is supplied to the second input of the 4th adder of the divider 25.4 of the unit for calculating the positional characteristics 6, the first input of which from the storage register of the module p ₄ 23.4 receives the value of the module "7", and the logical unit is constantly fed to the third input, which corresponds to the subtraction operation and obtaining the value “6”. The value from the output of the 4th adder of the divider 25.4 of the block for calculating the positional characteristics 6 is supplied to the first input of the 4th multiplier of the negative divider 26.4, the second input of which receives the coefficient value "1001 0010 0100 1001 0010" from the register of the coefficient k ₄ 24.4, which is simultaneously served on the first input of the 4th multiplier of the positive divider 27.4. Then the value at the output of the 4th multiplier of the positive divider 27.4 is "1001 0010 0100 1001 0010", and the output of the 4th multiplier of the negative divider 26.4 is "0110 1101 1011 0110 1100".

The values of the multipliers of the negative divider 26.1-26.4 go to the adder of the value F (-B) 29, from where the value "1111 1110 1100 0111 1010" is fed to the storage register of the value F (-B) 30; the values from the multipliers of the positive divider 27.1-27.4 are fed to the adder of the value F (B) 28, from the first output of which the value "0000 0001 0011 1000 0000" is fed to the first input of the storage register of the value F (B) 31; from the second output of the adder of the value F (B) 28, the value of the sign “0” goes to the control input of the multiplexer of the divider 34 and the second input of the XOR element 35, where the sign value equal to “0” is generated and fed to the first input of the output unit of private 8, where to the first input of the holding register of the sign 59.

38, который является третьим входом блока уточнения аппроксимационного ряда 7.On the third step, the data from the storage register of the value F (-A) 19 is supplied to the first input of the divisible 33 multiplexer; the data of the storage register of the value F (A) 20 is supplied to the second input of the divisible 33 multiplexer; from the second output of the adder of the value F (A) 17, the value of the sign "0" is fed to the control input of the dividend multiplexer 33, therefore, the output from the dividend multiplexer 33 is supplied with the value from the storage register of the value F (A) 20 equal to "0000 0001 0011 1000 0000" which is fed to the first input of the comparison unit 35 and from the fifth output of the unit for calculating positional characteristics 6 to the first input of the storage register

38, which is the third input of the refinement unit of the approximation row 7.

Data from the output of the storage register of the value F (-B) 30 is supplied to the first input of the multiplexer of the divider 34; data from the output of the storage register of the value F (B) 31 is supplied to the second input of the multiplexer of the divider 34; from the second output of the adder of the value F (B) 28, the sign value is supplied to the control input of the divider 34 multiplexer. Since the sign F (B) is “0”, the divider 34 multiplexer supplies the value F (B) from the second input to the output of the divider 34 multiplexer. which arrives at the second input of the comparison unit 35 and from the fourth output of the unit for calculating positional characteristics 6 to the first input, the shift register 36 of the refinement unit of the approximation series 7.

, на второй выход подается значение логической единицы, а на первый выход, поскольку

, подается значение логического нуля, которые поступают на элемент ИЛИ 47 блока вывода частного 8 и затем на элемент задержки 48. Значение со второго выхода блока сравнения 35 подается также на первый вход удерживающего регистра 49.The values of F (A) and F (B) are compared in comparison block 35, and since

, the logical unit value is supplied to the second output, and to the first output, since

, the value of logical zero is supplied, which are fed to the OR element 47 of the private output unit 8 and then to the delay element 48. The value from the second output of the comparison unit 35 is also supplied to the first input of the holding register 49.

, поступает на управляющий вход мультиплексора вывода частного 64, на выход которого отправляется значение с первого входа, который подключен к выходу мультиплексора равенства абсолютных величин делимого и делителя 63. Таким образом, значение «1» с выхода мультиплексора вывода частного 65 поступает на вход регистра хранения частного 64.At the fourth step, the value of the sign “0” from the output of the holding register of the sign 59 goes to the control input of the multiplexer for equality of absolute values of the dividend and the divisor 63, to the output of which from the output of the storage register of the value “1” 61 the value “1” is presented, presented in the RNS. Logical unit from the holding register 49, indicating

, is fed to the control input of the output multiplexer of private 64, the output of which is sent from the first input, which is connected to the output of the multiplexer of equality of absolute values of the dividend and the divisor 63. Thus, the value "1" from the output of the output multiplexer of private 65 is fed to the input of the storage register private 64.

On the fifth step, the value “1” from the output of the private storage register 64 goes to the output of the private 9 output, and the reset signal from the delay element 48 goes to the OR element 5, from where it goes to the registers and counters, transferring them to the initial state. The division is over.

Consider Example 2. Take A = 98 = {0.2.3.0} and B = -2 = {0,1,3,5}. At the first clock, the values of divisible A and divisor B go to the first inputs of the registers of divisible 10 and divisor 21, respectively.

On the second clock, the remainder a ₁ = 0 in the first module from the 1st output of the dividend register 10 simultaneously enters the input of the 1st inverter of dividend 11.1 of the block for calculating positional characteristics 6 and the second input of the 1st multiplier of positive dividend 16.1, the inverted value from output 1 inverter -th divisible 11.1 positional characteristics calculation unit 6 is supplied to a second input of the 1st adder divisible 14.1 positional characteristics calculation unit 6, to a first input of which a storage modulus register 12.1 p ₁ enters the value "2" of the module, and the third Rin d is constantly supplied to logical unit that corresponds to the operation of subtraction and reception of "0". The value from the output of the 1st adder of the dividend 14.1 of the block for calculating the positional characteristics 6 is supplied to the first input of the 1st multiplier of the negative dividend 15.1, the second input of which receives the coefficient value "1000 0000 0000 0000 0000" from the register of coefficient k ₁ 13.1, which is simultaneously served on the first input of the 1st multiplier of the positive divider 16.1. The values of the 1 multipliers of the negative dividend 15.1 and the positive dividend 16.1 are "0000 0000 0000 0000 0000".

The remainder a ₂ = 2 in the second module from the 2nd output of the register of divisible 10 goes simultaneously to the input of the 2nd inverter of the divisible 11.2 unit for calculating the positional characteristics 6 and the second input of the 2nd multiplier of the positive dividend 16.2. The inverted value from the output of the 2nd inverter of the divisible 11.2 unit for calculating the positional characteristics 6 is supplied to the second input of the 2nd adder of the divisible 14.2 unit for calculating the positional characteristics 6, the first input of which from the storage register of the module p ₂ 12.2 receives the value of the module "3", and the logical unit is constantly fed to the third input, which corresponds to the subtraction operation and obtaining the value “1”. The value from the output of the 2nd adder of the divisible 14.2 unit for calculating the positional characteristics 6 is supplied to the first input of the 2nd multiplier of the negative divisible 15.2, the second input of which receives the coefficient value "0101 0101 0101 0101 0101" from the register of coefficient k ₂ 13.2, which is simultaneously served on the first input of the 2nd multiplier of the positive divider 16.2. Then the value at the output of the 2nd multiplier of the positive divisor 16.2 is “1010 1010 1010 1010 1010”, and the output of the 2nd multiplier of the negative divisor 15.2 is “0101 0101 0101 0101 0101”.

The remainder a ₃ = 3 in the third module from the 3rd output of the register of divisible 10 enters simultaneously the input of the 3rd inverter of the divisible 11.3 unit for calculating positional characteristics 6 and the second input of the 3rd multiplier of the positive divisible 16.3. The inverted value from the output of the 3rd inverter of the divisible 11.3 unit for calculating the positional characteristics 6 is supplied to the second input of the 3rd adder of the divisible 14.3 unit for calculating the positional characteristics 6, the first input of which from the storage register of the module p ₃ 12.3 receives the value of the module “5”, and the logical unit is constantly fed to the third input, which corresponds to the subtraction operation and obtaining the value “2”. The value from the output of the 3rd adder of the divisible 14.3 unit for calculating the positional characteristics 6 is supplied to the first input of the 3rd multiplier of the negative divisible 15.3, the second input of which receives the coefficient value "1001 1001 1001 1001 1001" from the register of the coefficient k ₃ 13.3, which is simultaneously served on the first input of the 3rd multiplier of the positive divider 16.3. Then the value at the output of the 3rd multiplier of the positive divisor 16.3 is "1100 1100 1100 1100 1011", and the output of the 3rd multiplier of the negative divisor 15.3 is "0011 0011 0011 0011 0010".

The remainder a ₄ = 0 in the fourth module from the 4th output of the register of divisible 10 enters simultaneously the input of the 4th inverter of the divisible 11.4 unit for calculating positional characteristics 6 and the second input of the 4th multiplier of the positive divisible 16.4. The inverted value from the output of the 4th inverter of the dividend 11.4 unit for calculating the positional characteristics 6 is supplied to the second input of the 4th adder of the dividend 14.4 unit for calculating the positional characteristics 6, the first input of which from the storage register of the module p ₄ 12.4 receives the value of the module “7”, and the logical unit is constantly fed to the third input, which corresponds to the subtraction operation and obtaining the value “0”. The value from the output of the 4th adder of the dividend 14.4 of the block for calculating the positional characteristics 6 is supplied to the first input of the 4th multiplier of the negative dividend 15.4, the second input of which receives the coefficient value "1001 0010 0100 1001 0010" from the storage register of the coefficient k ₄ 13.4, which is simultaneously served on the first input of the 4th multiplier of the positive divider 16.4. The values of the 4 multipliers of the negative dividend 15.4 and the positive dividend 16.4 are "0000 0000 0000 0000 0000".

The values of the multipliers of the negative dividend 15.1-15.4 go to the adder of the value F (-A) 18, from where the value "1000 1000 1000 1000 0111" is fed to the storage register of the value F (-A) 19; the values from the multipliers of the positive dividend 16.1-16.4 go to the adder of the value F (A) 17, from the first output of which the value "0111 0111 0111 01111 0101" is fed to the first input of the storage register of the value F (A) 20; from the second output of the adder of the value F (A) 17, the value of the sign "0" is fed to the control input of the divisor 33 multiplexer and the first input of the XOR 32 element.

The remainder b ₁ = 0 in the first module from the 1st output, register dividend 21 is fed simultaneously to the input of the 1st inverter divider 22.1 of the block for calculating positional characteristics 6 and the second input of the 1st multiplier of the positive divider 27.1. The inverted value from the output of the 1st inverter of the divider 22.1 of the block for calculating the positional characteristics 6 goes to the second input of the 1st adder of the divider 25.1 of the block for calculating the positional characteristics 6, the first input of which from the storage register of the module p ₁ 23.1 receives the value of the module "2", and the logical unit is constantly fed to the third input, which corresponds to the subtraction operation and obtaining the value “0”. The value from the output of the 1st adder of the divider 25.1 of the block for calculating the positional characteristics 6 is supplied to the first input of the 1st multiplier of the negative divider 26.1, the second input of which receives the coefficient value "1000 0000 0000 0000 0000" from the register of coefficient k ₁ 24.1, which is simultaneously served on the first input of the 1st multiplier of the positive divider 27.1. The values of 1 multipliers of negative dividend 26.1 and positive dividend 27.1 are equal to "0000 0000 0000 0000 0000".

The remainder b ₂ = 1 in the second module from the 2nd output of the register divisible by 21 is fed simultaneously to the input of the 2nd inverter of the divider 22.2 of the block for calculating positional characteristics 6 and the second input of the 2nd multiplier of the positive divider 27.2. The inverted value from the output of the 2nd inverter of the divider 22.2 of the block for calculating the positional characteristics 6 is supplied to the second input of the 2nd adder of the divider 25.2 of the block for calculating the positional characteristics 6, the first input of which from the storage register of the module p ₂ 23.2 receives the value of the module "3", and the logical unit is constantly fed to the third input, which corresponds to the subtraction operation and obtaining the value “2”. The value from the output of the 2nd adder of the divider 25.2 of the block for calculating the positional characteristics 6 is supplied to the first input of the 2nd multiplier of the negative divider 26.2, the second input of which receives the coefficient value "0101 0101 0101 0101 0101" from the register of coefficient k ₂ 24.2, which is simultaneously served on the first input of the 2nd multiplier of the positive divider 27.2. Then the value at the output of the 2nd multiplier of the positive divider 27.2 is "0101 0101 0101 0101 0101", and the output of the 2nd multiplier of the negative divider 26.2 is "1010 1010 1010 1010 1010".

The remainder b ₃ = 3 in the third module from the 3rd output of the register of dividend 21 is fed simultaneously to the input of the 3rd inverter of the divider 22.3 of the block, calculating the positional characteristics 6 and the second input of the 3rd multiplier of the positive divider 27.3. The inverted value from the output of the 3rd inverter of the divider 22.3 of the positional characteristics calculator 6 is supplied to the second input of the 3rd adder of the divider 25.3 of the positional characteristics calculator 6, the first input of which from the storage register of module p ₃ 23.3 receives the value of module “5”, and the logical unit is constantly fed to the third input, which corresponds to the subtraction operation and obtaining the value “2”. The value from the output of the 3rd adder of the divider 25.3 of the block for calculating the positional characteristics 6 is supplied to the first input of the 3rd multiplier of the negative divider 26.3, the second input of which receives the coefficient value "1001 1001 1001 1001 1001" from the register of the coefficient k ₃ 24.3, which is simultaneously served on the first input of the 3rd multiplier of the positive divisor 27.3. Then the value at the output of the 3rd multiplier of the positive divisor 27.3 is "1100 1100 1100 1100 1011", and the output of the 3rd multiplier of the negative divisor 26.3 is "0011 0011 0011 0011 0010".

The remainder b ₄ = 5 in the fourth module from the 4th output of the register of dividend 21 is fed simultaneously to the input of the 4th inverter of the divider 22.4 of the block for calculating positional characteristics 6 and the second input of the 4th multiplier of the positive divider 27.4. The inverted value from the output of the 4th inverter of the divider 22.4 of the unit, calculating the positional characteristics 6 is supplied to the second input of the 4th adder of the divider 25.4 of the unit for calculating the positional characteristics 6, the first input of which from the storage register of the module p ₄ 23.4 receives the value of the module "7", and the logical unit is constantly fed to the third input, which corresponds to the subtraction operation and obtaining the value “2”. The value from the output of the 4th adder of the divider 25.4 of the block for calculating the positional characteristics 6 is supplied to the first input of the 4th multiplier of the negative divider 26.4, the second input of which receives the coefficient value "1001 0010 0100 1001 0010" from the register of the coefficient k ₄ 24.4, which is simultaneously served on the first input of the 4th multiplier of the positive divider 27.4. Then the value at the output of the 4th multiplier of the positive divisor 27.4 is "1101 1011 0110 1101 1010", and the output of the 4th multiplier of the negative divisor 26.4 is "0010 0100 1001 0010 0100".

The values of the multipliers of the negative divisor 26.1-26.4 are fed to the adder of the value F (- B) 29, from where the value "0000 0010 0111 0000 0000" is fed to the storage register of the value F (- B) 30; the values from the multipliers of the positive divider 27.1-27.4 are fed to the adder of the value F (B) 28, from the first output of which the value "1111 1101 1000 1111 1010" is fed to the first input of the storage register of the value F (B) 31; from the second output of the adder of the value F (B) 28, the value of the sign “1” goes to the control input of the multiplexer of the divider 34 and the second input of the XOR 32 element, where the sign value equal to “1” is generated and fed to the first input of the private output unit, where it goes to first entry of the holding register of the sign 59.

38 блока уточнения аппроксимационного ряда 7.On the third step, data from the storage register of the value F (-A) 19 is supplied to the first input of the divisible 33 multiplexer; the data of the storage register of the value F (A) 20 is supplied to the second input of the dividend multiplexer 33: from the second output of the adder of the value F (A) 17, the sign “0” is fed to the control input of the dividend 33 multiplexer, therefore, the value from the register is output to the dividend 33 multiplexer storing the value of F (A) 20, equal to "0111 0111 0111 0111 0101", which is fed to the first input of the comparison unit 35 and from the fifth output of the unit for calculating positional characteristics 6 to the first input of the storage register

38 block refinement approximation series 7.

Data from the output of the storage register of the value F (- B) 30 is supplied to the first input of the multiplexer of the divider 34; data from the output of the storage register of the value F (B) 31 is fed to the second input of the multiplexer of the divider 34: from the second output of the adder of the value F (B) 28, the sign value is fed to the control input of the multiplexer of the divider 34. Since the sign F (B) is "1", the divider multiplexer 34 supplies from the first input a value F (-B) equal to “0000 0010 0111 0000 0000” to the output of the divider 34 multiplexer, which is fed to the second input of the comparison unit 35 and from the fourth output of the positional characteristics calculator 6 to the first input of the register shift 36 approximation refinement unit range 7.

и

сравниваются в блоке сравнения 35, и на первый второй выходы

и

подается значение логического пуля, которые поступают на элемент ИЛИ 47 блока вывода частного 8 и затем на элемент задержки 48. Значение со второго выхода блока сравнения 35 подается также па первый вход удерживающего регистра 49.Values

and

are compared in the block comparison 35, and the first second outputs

and

the value of the logical bullet is supplied, which are fed to the OR element 47 of the private output unit 8 and then to the delay element 48. The value from the second output of the comparison unit 35 is also fed to the first input of the holding register 49.

At the fourth step, the sign “1” of the private Q from the output of the holding register of the sign 59 goes to the control input of the multiplexer for equality of the absolute values of the dividend and the divisor 63 to the output of which from the second input the value “-1” is presented, which is stored in the RNC, which is stored in the value storage register "-1" 62. Since the output of the holding register 49 to the control input of the multiplexer output private 64 receives a logical zero, it is expected the value from the second input, which is currently not defined.

вправо, посылая с первого выхода сигналы сдвига на первый вход памяти хранения степеней «2» в СОК 42 и на первый вход счетчика 37. После сдвигов значение регистра сдвига будет равно «1001 1100 0000 0000 0000». Значение памяти хранения степеней «2» в СОК 42 будет адресовано к степени «2⁵». Значение счетчика 37 равно «6». Значение «0111 0111 0111 0111 0101» с регистра хранения

38 через второй вход мультиплексора выбора уменьшаемого 40 поступает на первый вход мультиплексора выбора следующего уменьшаемого 44, откуда поступает на первый вход регистра хранения уменьшаемого 39.On the fourth and ninth clock, shift register 36 begins to shift the value

to the right, sending the shift signals from the first output to the first input of the storage of degrees “2” in the RNS 42 and to the first input of the counter 37. After the shifts, the value of the shift register will be “1001 1100 0000 0000 0000”. The value of the storage memory of the degrees “2” in the SOK 42 will be addressed to the degree “2 ⁵ ”. The value of counter 37 is "6". Value "0111 0111 0111 0111 0101" from the storage register

38 through the second input of the selector of the decremented 40 is fed to the first input of the multiplexer of the choice of the next decremented 44, from where it goes to the first input of the register of the reduction of 39.

On the tenth step, the counter 37 from the first output sends a left shift signal and decreases the value to 5. The left shift signal is fed to the shift register 36, the output of which is supplied with the value “0100 1110 0000 0000 0000”, which is supplied through the inverter 41 of the refinement unit of approximation row 7 to the second input of the adder 43 of the refinement unit of the approximation row 7, the first input of which from the storage register of the decremented 39 through the multiplexer of the selection of the decremented 40 receives the value "0111 0111 0111 0111 0101". The adder is calculating

and the value "0010 1001 0111 0111 0101" is output.

Since the result is positive, the value “0” is supplied to the second output of the adder 43 of the refinement unit of the approximation row 7, which simultaneously goes to the control input of the next selectable 44 selector and to the input of the element NOT 45, from the output of which the value “1” is fed to the second input element And 46. Under the influence of the left shift signal from the output of the storage memory of degrees "2" in the RNS 42, the value "2 ⁵ " is supplied to the first input of the element And 46. From the output of element And 46, the values of residues “2 ⁵ ” by the modules are fed to the corresponding first inputs of the remainder storage registers modulo p ₁ , p ₂ , p ₃ , p ₄ 50.1-50.4.

From the output of the multiplexer for selecting the next decremented 44, the value "0010 1001 0111 0111 0101" is sent to the storage register of the decremented 39.

At the eleventh step, the counter 37 from the first output sends a left shift signal and decreases the value to “4”. The left shift signal is fed to the shift register 36, the output of which is supplied with the value “0010 0111 0000 0000 0000”, which through the inverter 41 of the refinement unit of the approximation series 7 is fed to the second input of the adder 43 of the refinement unit of the approximation series 7, the first input of which is from the storage register decremented 39 through the multiplexer selection of decreasing 40 receives the value "0010 1001 0111 0111 0101". In the adder 43 of the refinement unit of the approximation series 7, the calculation

and the value “0000 0010 0111 0111 0101” is output.

Since the result is positive, the value “0” is supplied to the second output of the adder 43 of the refinement unit of the approximation row 7. which simultaneously enters the control input of the next selectable 44 selection multiplexer and to the input of the element NOT 45, from the output of which the value “1” is supplied to the second input of the And 46 element. From the output of the next selectable 44 selectable 44 multiplexer, the value “0000 0010 0111 0111 0101” goes to decremented storage register 39. Under the action of the left shift signal from the output of the storage memory of degrees “2” in the RNS 42, the value “2 ⁴ ” is supplied to the first input of the AND element 46. From the output of element And 46, the values of the residues “2 ⁴ ” by the modules are fed to the corresponding first inputs of the balance storage registers modulo p ₁ , p ₂ , p ₃ , p ₄ 50.1-50.4.

From the outputs of the remainder storage registers modulo p ₁ , p ₂ , p ₃ , p ₄ 50.1-50.4, the remainders of the value "2 ⁵ " are fed to the first inputs of the corresponding adders modulo p ₁ , p ₂ , p ₃ , p ₄ 51.1-51.4.

On the twelfth step, the counter 37 from the first output sends a shift signal to the left and reduces the value to "3". The left shift signal is supplied to the shift register 36, the output of which is supplied with the value “0001 0011 1000 0000 0000”, which through the inverter 41 of the refinement unit of the approximation series 7 is fed to the second input of the adder 43 of the refinement unit of the approximation series 7, the first input of which is from the storage register decremented 39 through the multiplexer selection of decreasing 40 receives the value "0000 0010 0111 0111 0101". In the adder 43 of the refinement unit of the approximation series 7, the calculation

and the output receives the value "1110 1110 1111 0111 0101".

Since the result is negative, the value “1” is supplied to the second output of the adder 43 of the approximation row refinement unit, which simultaneously goes to the control input of the next selectable 44 decrementor and to the input of the element NOT 45, from the output of which the value “0” is fed to the second input of the element And 46. From the output of the next decremented 44 selection multiplexer, the value “0000 0010 0111 0111 0101” goes to the decremented storage register 39. Under the action of the left shift signal from the output of the storage of degrees “2” in the RNS 42, the first the course of the And 46 element is given the value “2 ³ ” From the output of element And 46, the values “0” are received at the first inputs of the remainder storage registers modulo p ₁ , p ₂ , p ₃ , p ₄ 50.1-50.4.

From the outputs of the remainder storage registers modulo p ₁ , p ₂ , p ₃ , p ₄ 50.1-50.4, the remainders of the value "2 ⁴ " are fed to the first inputs of the corresponding adders modulo p ₁ , p ₂ , p ₃ , p ₄ 51.1-51.4, where the calculation occurs (2 ⁵ +2 ⁴ ) mod p _i , where i = 1,2,3,4.

On the thirteenth step, the counter 37 from the first output sends a left shift signal and decreases the value to “2”. The left shift signal is fed to the shift register 36, the output of which is supplied with the value “0000 1001 1100 0000 0000”, which, through the inverter 41 of the refinement unit of the approximation series 7, is fed to the second input of the adder 43 of the refinement unit of the approximation series 7, the first input of which is from the storage register decrementable 39 through the multiplexer selection of decreasing 40 receives the value "0000 0010 0111 0111 0101". In the adder 43 of the refinement unit of the approximation series 7, the calculation

and the output receives the value "1111 1000 1011 0111 0101".

Since the result is negative, the value “1” is supplied to the second output of the adder 43 of the refinement unit of the approximation row 7. which simultaneously arrives at the control input of the next selectable 44 selection multiplexer and at the input of the element NOT 45, from the output of which the value “0” is supplied to the second input of the And 46 element. From the output of the next selectable 44 selectable 44 multiplexer, the value “0000 0010 0111 0111 0101” goes to decremented storage register 39. Under the action of the left shift signal from the output of the storage of degrees “2” in the RNS 42, the value “2 ² ” is supplied to the first input of the AND element 46. From the output of element AND 46, the values “0” are received at the first inputs of the remainder storage registers modulo p ₁ , p ₂ , p ₃ , p ₄ 50.1-50.4.

From the outputs of the remainder storage registers modulo p ₁ , p ₂ , p ₃ , p ₄ 50.1-50.4, the remainders of the value "0" are fed to the first inputs of the corresponding adders modulo p ₁ , p ₂ , p ₃ , p ₄ 51.1-51.4, where the calculation is (2 ⁵ +2 ⁴ +0) mod p _i , where i = 1,2,3,4.

On the fourteenth step, the counter 37 from the first output sends a shift signal to the left and decreases the value to "1". The left shift signal is fed to the shift register 36, the output of which is supplied with the value “0000 0100 1110 0000 0000”, which, through the inverter 41 of the refinement unit of the approximation series 7, is fed to the second input of the adder 43 of the refinement unit of the approximation series 7, the first input of which is from the storage register decrementable 39 through the multiplexer selection of decreasing 40 receives the value "0000 0010 0111 0111 0101". In the adder 43 of the refinement unit of the approximation row 7, the calculation

and the output receives the value "1111 1101 1001 0111 0101".

Since the result is negative, the value “1” is supplied to the second output of the adder 43 of the refinement unit of the approximation row 7. which simultaneously enters the control input of the next selectable 44 selection multiplexer and to the input of the element NOT 45, from the output of which the value “0” is supplied to the second input of the And 46 element. From the output of the next selectable 44 selectable 44 multiplexer, the value “0000 0010 0111 0111 0101” goes to decremented storage register 39. Under the action of the left shift signal from the output of the storage memory of degrees “2”, the value “2 ¹ ” is supplied to the first input of AND element 46 in the RNC. From the output, element And 46, the values “0” are received at the first inputs of the remainder storage registers modulo p ₁ , p ₂ , p ₃ , p ₄ 50.1-50.4.

From the outputs of the remainder storage registers modulo p ₁ , p ₂ , p ₃ , p ₄ 50.1-50.4, the remainders of the value “0” are fed to the first inputs of the corresponding adders modulo p ₁ , p ₂ , p ₃ , p ₄ 51.1-51.4, where the calculation occurs (2 ⁵ +2 ⁴ + 0 + 0) mod p _i , where i = 1,2,3,4.

On the fifteenth step, the counter 37 from the first output sends a shift signal to the left and decreases the value to "0". The left shift signal is fed to the shift register 36, the output of which is set to “0000 0010 0111 0000 0000”, which, through the inverter 41 of the refinement unit of the approximation series 7, is fed to the second input of the adder 43 of the refinement unit of the approximation series 7, the first input of which is from the storage register decrementable 39 through the multiplexer selection of decreasing 40 receives the value "0000 0010 0111 0111 0101". In the adder 43 of the refinement unit of the approximation series 7, the calculation

and the value “0000 0000 0000 0111 0101” is output.

Since the result is positive, then the value “0” is supplied to the second output of the adder 43 of the refinement unit of the approximation row 7, which simultaneously goes to the control input of the next selectable 44 decrementor and to the input of the element NOT 45, from the output of which the value “1” is fed to the second input element 46. From the output of the next decremented 44 multiplexer, the value “0000 0000 0000 0111 0101” goes to the decremented storage register 39. Under the influence of the left shift signal, the output of the degree “2” storage memory in the RNS 42 is on the first input element And 46 is the value "2 ⁰ ". From the output of element And 46, the values of the residues “2 ⁰ ” by modules are fed to the first inputs of the remainder storage registers modulo p ₁ , p ₂ , p ₃ , p ₄ 50.1-50.4.

From the outputs of the remainder storage registers modulo p ₁ , p ₂ , p ₃ , p ₄ 50.1-50.4, the remainders of the value “0” are fed to the first inputs of the corresponding adders modulo p ₁ , p ₂ , p ₃ , p ₄ 51.1-51.4, where the calculation is (2 ⁵ +2 ⁴ + 0 + 0 + 0) mod p _i , where i = 1,2,3,4.

At the sixteenth cycle, from the outputs of the remainder storage registers modulo p ₁ , p ₂ , p ₃ , p ₄ 50.1-50.4, the remainders of the value “2 ⁰ ” are fed to the first inputs of the corresponding adders modulo p ₁ , p ₂ , p ₃ , p ₄ 51.1 -51.4 where the calculation takes place

(2 ⁵ +2 ⁴ + 0 + 0 + 0 + 2 ⁰ ) mod p _i = 49 mod p _i .

where i = 1,2,3,4.

The counter 37 from the second output sends a signal to the end of the shift register 36, which is fed to the control inputs of the demultiplexers modulo p ₁ , p ₂ , p ₃ , p ₄ 52.1-52.4 and the values of the sums from the outputs of the corresponding adders modulo p ₁ , p ₂ , p ₃ , p ₄ 51.1-51.4 go to the inputs of the corresponding inverters 54.1-54.4 of the output unit private 8 and the first inputs of the storage registers of the sum modulo p ₁ , p ₂ , p ₃ , p ₄ 53.1-53.4. From the output of the inverters 54.1-54.4 of the private 8 output unit, the signals are fed to the first inputs of the adders 56.1-56.4 of the private 8 output unit, the second inputs of which receive the module values from the module storage registers p ₁ , p ₂ , p ₃ , p ₄ 55.1-55.4. From the outputs of the adders 56.1-56.4 of the private 8 output unit, the values are supplied to the first inputs of the storage registers of the inverse of the sum value modulo p ₁ , p ₂ , p ₃ , p ₄ 57.1-57.4.

At the seventeenth cycle, from the output of the storage register of the sum modulo p ₁ 53.1, the value “1” goes to the first input of the 1st multiplexer for selecting the sum 58.1. From the output of the storage register of the reciprocal of the value of the sum modulo p ₁ 57.1, the value “1” goes to the second input of the 1st multiplexer for selecting the sum 58.1, to the control input of which from the holding register of sign 59 a private sign is set, which is equal to “1”. Thus, from the output of the 1st sum selection multiplexer 58.1, the value from the storage register of the inverse of the sum value modulo p ₁ 57.1 is received at the 1st input of the sum storage register.

From the output of the storage register of the sum modulo p ₂ 53.2, the value "1" is supplied to the first input of the 2nd multiplexer for selecting the sum 58.2. From the output of the storage register of the reciprocal of the value of the sum modulo p ₂ 57.2, the value "2" is supplied to the second input of the 2nd multiplexer for selecting the sum 58.2, to the control input of which from the holding register of sign 59 a private sign is set, which is equal to "1". Thus, from the output of the 2nd sum selection multiplexer 58.2 to the 2nd input of the sum storage register, the value in the SOK 60 receives the value from the storage register of the reciprocal of the sum value modulo p ₂ 57.2.

From the output of the storage register of the sum modulo p ₃ 53.3, the value "4" is supplied to the first input of the 3rd multiplexer for selecting the sum 58.3. From the output of the register of storage of the reciprocal of the value of the sum modulo p ₃ 57.3, the value “1” is supplied to the second input of the 3rd multiplexer for selecting the sum 58.3, to the control input of which from the holding register of sign 59 a quotient is given, which is equal to “1”. Thus, from the output of the 3rd sum selection multiplexer 58.3, the value from the storage register of the reciprocal of the sum value modulo p ₃ 57.3 is received at the 3rd input of the sum storage register.

From the output of the storage register of the sum modulo p ₄ 53.4, the value "0" is supplied to the first input of the 4th multiplexer for selecting the sum 58.4. From the output of the register of storage of the reciprocal of the value of the sum modulo p ₄ 57.4, the value "0" is supplied to the second input of the 4th multiplexer for selecting the sum 58.4, to the control input of which from the holding register of sign 59 a private sign is set, which is equal to "1". Thus, from the output of the 4th sum selection multiplexer 58.4, the value from the storage register of the reciprocal of the sum value modulo p ₄ 57.4 is received at the 4th input of the sum storage register in SOK 60.

Thus, the value storage {1, 2, 1, 0} is stored in the storage register of the amount in the CRS 60, which corresponds to the value “-49”.

On the eighteenth cycle, the value in the storage register of the amount in the RNS 60 is fed to the second input of the private 64 output multiplexer, the control input of which from the holding register 49 receives the value of the logical bullet. From the output of the private 64 output multiplexer, the value {1, 2, 1, 0} of the amount storage register in the SOK 60 is fed to the private storage register 65.

At the nineteenth clock, the quotient from the private storage register 65 is fed to the output of the private 8. output. The division is completed.

Claims (1)

A modular number division device comprising divisor and divider inputs, a private output output, a positional characteristic calculator, a shift register, a counter, a degree storage memory “2” in a residual class system (RNC), the first shift register output being connected simultaneously with the first counter input and the first input of the storage memory of degrees “2” in the RNS, the second input of which is connected to the first output of the counter, characterized in that the inputs of a clock pulse and global reset, an OR element, an approximation refinement block are introduced into it a series output, a private output unit, a clock input is connected to the third input of the positional characteristics calculating unit, with the first input of the approximation row refinement unit and the fifth input of a private output unit, the first output of which is connected to the second input of the OR element, the first input of which is connected to the input of the global discharge; the output of the OR element is connected to the fourth input of the positional characteristics calculating unit, the second input of the approximation row refinement unit and the fourth input of the private output unit, the second output of which is the private output output, the sixth and seventh inputs of the private output unit are connected respectively to the first and second outputs of the approximation approximation unit a row, the third and fourth inputs of which are connected to the fifth and fourth outputs of the block for calculating positional characteristics, the first, second and third outputs of which are connected to the first, second and third inputs of the private output unit, and the first and second inputs of the positional characteristic calculating unit are connected to the input of the dividend and the input of the divider, respectively, the positional characteristics unit consisting of a dividend register, a divisor register, n inverters of the dividend unit for calculating positional characteristics, where n is the number of RNS modules, n inverters of the divider of the block for calculating positional characteristics, 2n storage registers of the module p _i , where i = 1, ..., n, 2n registers of storage of coefficient k _i , n adders of the divisible unit for calculating the positional characteristics, n adders for the divisor of the unit for calculating the positional characteristics, n first divisible multipliers, n second divisible multipliers, n first divisor multipliers, n second divisor multipliers, adder of the value F (A), adder of the value F (-A ), the adder of the value F (B), the adder of the value F (-B), the register for storing the value F (A), the register for storing the value F (-A), the register for storing the value F (B), the register for storing the value F (-B) , XOR element, dividend multiplexer, divider multiplexer and blo comparison, where the first input of the register of the dividend is connected to the input of the dividend, the second and third inputs are connected to the input of the clock pulse and the output of the OR element, respectively, the 1st output is connected to the input of the 1st inverter of the dividend unit for calculating positional characteristics and the second input of the 1st a positive divisible multiplier whose first input is connected to the output of the coefficient k storage register _one connected simultaneously to the second input of the 1st negative divisible multiplier, the first input of which is connected to the output of the 1st adder of the dividend unit for calculating positional characteristics, the third input of which is constantly supplied with the value of a logical unit, the second input is connected to the output of the 1st inverter of the dividend unit calculating positional characteristics, the first input is connected to the output of the storage register of module p _one , The 2nd output of the dividend register is connected to the input of the 2nd inverter of the dividend unit for calculating positional characteristics and the second input of the 2nd multiplier of the positive dividend, the first input of which is connected to the output of the coefficient storage register k ₂ connected simultaneously to the second input of the 2nd negative divisible multiplier, the first input of which is connected to the output of the 2nd adder of the dividend unit for calculating positional characteristics, the third input of which is constantly supplied with the value of a logical unit, the second input is connected to the output of the 2nd inverter of the dividend block calculating positional characteristics, the first input is connected to the output of the storage register of module p ₂ , similar connections for the rest of the outputs of the dividend register, finally, the nth output of the dividend register is connected to the input of the nth inverter of the dividend unit for calculating positional characteristics and the second input of the nth multiplier of the positive dividend, the first input of which is connected to the output of the coefficient storage register k _n connected simultaneously to the second input of the nth negative divisible multiplier, the first input of which is connected to the output of the nth adder of the dividend unit for calculating positional characteristics, the third input of which is constantly supplied with the value of a logical unit, the second input is connected to the output of the nth inverter of the divisible block calculating positional characteristics, the first input is connected to the output of the storage register of module p _n , the output of the 1st multiplier of the positive dividend is connected to the 1st input of the adder of the value F (A), the output of the 2nd multiplier of the positive dividend is connected to the 1st input of the adder of the value F (A), and so on, finally, the output n- the 1st multiplier of the positive dividend is connected to the nth input of the adder of the value F (A), the output of the 1st multiplier of the negative dividend is connected to the 1st input of the adder of value F (-A), the output of the 2nd multiplier of the negative dividend is connected to the 2nd the input of the adder of the value F (-A), and so on, finally, the output of the nth negative multiplier is divided the second is connected to the nth input of the adder of the value F (-A), the first input of the divider register is connected to the input of the divider, the second and third inputs are connected to the input of the clock pulse and the output of the OR element, respectively, the 1st output is connected to the input of the 1st inverter the divider of the block for calculating the positional characteristics and the second input of the 1st multiplier of the positive divider, the first input of which is connected with the output of the storage register _one connected simultaneously to the second input of the 1st multiplier of the negative divider, the first input of which is connected to the output of the 1st adder of the divider of the positional characteristics calculator, the third input of which is constantly supplied with the value of a logical unit, the second input is connected to the output of the 1st inverter of the divider of the block calculating positional characteristics, the first input is connected to the output of the storage register of module p _one , The 2nd output of the divider register is connected to the input of the 2nd inverter of the divider of the block for calculating positional characteristics and the second input of the 2nd multiplier of the positive divider, the first input of which is connected to the output of the register of storage of the coefficient k ₂ connected simultaneously to the second input of the 2nd multiplier of the negative divider, the first input of which is connected to the output of the 2nd adder of the divider of the block for calculating positional characteristics, the third input of which is constantly supplied with the value of a logical unit, the second input is connected to the output of the 2nd inverter of the divider of the block calculating positional characteristics, the first input is connected to the output of the storage register of module p ₂ , similar connections to the rest of the outputs of the divider register, finally, the nth output of the divider register is connected to the input of the nth inverter divider of the positional characteristics calculator and the second input of the nth multiplier of the positive divider, the first input of which is connected to the output of the coefficient storage register k _n connected simultaneously to the second input of the nth multiplier of the negative divider, the first input of which is connected to the output of the nth adder of the divider of the block for calculating positional characteristics, the third input of which is constantly supplied with the value of a logical unit, the second input is connected to the output of the nth inverter of the divider of the block calculating positional characteristics, the first input is connected to the output of the storage register of module p _n , the output of the 1st multiplier of the positive divider is connected to the 1st input of the adder of the value F (B), the output of the 2nd multiplier of the positive divider is connected to the 2nd input of the adder of the value F (B), and so on, finally, the output n- the 1st multiplier of the positive divider is connected to the nth input of the adder of the value F (B), the output of the 1st multiplier of the negative divider is connected to the 1st input of the adder of value F (-B), the output of the 2nd multiplier of the negative divider is connected to the 2nd the input of the adder values F (-B), and so on, finally, the output of the nth negative multiplier divides For connected to the nth input of the adder, the values of F (-B), the output of which is connected to the first input of the storage register of the value F (-B), the second and third inputs of which are connected to the input of the clock pulse and the output of the OR element, respectively, the output is connected to the first the input of the divider multiplexer, the second input of which is connected to the output of the storage register of the value F (B), the second and third inputs of which are connected to the input of the clock pulse and the output of the OR element, respectively, the first input is connected to the first output of the adder, the values of F (B), the second output to It is simultaneously connected to the second input of the XOR element and the control input of the divider multiplexer, the output of which is the fourth output of the positional characteristics calculating unit and is connected to the fourth input of the approximation row refinement unit, and is also connected to the second input of the comparison unit, the first input of which is connected to the fifth output of the unit calculation of positional characteristics and is connected to the third input of the approximation row refinement unit, and is the output of the dividend multiplexer, the control input of the cat It is connected to the first input of the XOR element and the second output of the adder of the value F (A), the first output of which is connected to the first input of the storage register of the value F (A), the second and third inputs of which are connected to the input of the clock pulse and the output of the OR element, respectively, and the output connected to the second input of the dividend multiplexer, the first input of which is connected to the output of the value storage register F (-A), the second and third inputs of which are connected to the input of the clock pulse and the output of the OR element, respectively, the first input is connected to the output of the sums ora of the value F (-A), the output of the XOR element is the first output of the positional characteristics calculating unit and is connected to the first input of the private output unit, the second and third inputs of which are connected to the first and second outputs of the comparison unit, respectively; the approximation row refinement unit contains a shift register, a counter, a storage register F (| A |), a decrement storage register, a reduction multiplexer, an approximation row refinement inverter, degrees “2” storage unit in the RNC, an adder of the approximation row refinement block, a selection multiplexer the next decremented element is NOT, the element AND, wherein the first input of the shift register is connected to the fourth output of the positional characteristic calculating unit, the second and third inputs are connected to the input of the clock pulse and the outputs the house of the OR element, respectively, the fourth input is connected to the first output of the counter, the second and third inputs of which are connected to the input of the clock pulse and the output of the OR element, respectively, the second output is the second output of the refinement unit of the approximation series and connected to the seventh input of the private output unit, the first output of the counter it is also connected to the control input of the reduction selector multiplexer, the second input of which is connected to the output of the storage register F (| A |), the second and third inputs of which are connected to the clock input pulse and the output of the OR element, respectively, the first input is connected to the fifth output of the positional characteristics calculator, the first input of the selector to be reduced is connected to the output of the storage register to be reduced, the second and third inputs of which are connected to the input of the clock pulse and the output of the OR element, respectively, the first input is connected to the output of the next decremented selection multiplexer, the first input of which is connected to the output of the decremented selection multiplexer, which is simultaneously connected to the first input of the sums the torus of the approximation row refinement unit, the second input of which is connected to the inverter of the approximation series refinement unit, the input of which is connected to the second output of the shift register, the second input of the next reduction multiplexer is connected to the first output of the adder of the approximation row refinement unit, the second output of which is connected simultaneously to the control the input of the multiplexer for selecting the next one to be reduced and the input of the element is NOT, the output of which is connected to the second input of the element AND, the first input of which о is connected to the output of the storage memory of degrees “2” in the RNS, and the output is connected to the sixth input of the private output unit, consisting of an OR element of the private output unit, a delay element holding the register, n remainder storage registers modulo p _i , n adders modulo p _i , n demultiplexers modulo p _i , n registers of storage of the sum modulo p _i , n inverters of the private output unit, n storage registers of module p _i , n adders of the private output block, n registers for storing the inverse of the sum value modulo p _i , n sum selection multiplexers holding the sign register, the sum storage register in the RNS, the value storage register “1”, the value storage register “-1”, the multiplier of equality of absolute values of the dividend and divisor, the output private multiplexer, the private storage register, while the first the output of the approximation row refinement unit is connected to the first input of the remainder storage register modulo p _one , the second and third inputs of which are connected to the input of the clock pulse and the output of the OR element, respectively, and the output is connected to the first input of the adder modulo p _one the output of which is connected to the information input of the demultiplexer modulo p _one whose control input is connected to the second output of the approximation row refinement unit, and the second output is connected to the second adder input modulo p _one , the first output is connected simultaneously to the input of the 1st inverter of the private output unit and the first input of the sum storage register modulo p _one , the second and third inputs of which are connected to the input of the clock pulse and the output of the OR element, respectively, the output is connected to the first input of the 1st sum selection multiplexer, the second input of which is connected to the output of the storage register of the reciprocal of the sum value modulo p _one , the second and third inputs of which are connected with the input of the clock pulse and the output of the OR element, respectively, the first input is connected to the output of the 1st adder of the private output unit, the third input of which is continuously supplied with a logical unit, the second input is connected to the output of the storage register of module p _one , the first input is connected to the output of the 1st inverter of the private output unit, the first output of the approximation row refinement unit is connected to the first input of the remainder storage register modulo p ₂ , the second and third inputs of which are connected to the input of the clock pulse and the output of the OR element, respectively, and the output is connected to the first input of the adder modulo p ₂ the output of which is connected to the information input of the demultiplexer modulo p ₂ whose control input is connected to the second output of the approximation row refinement unit, and the second output is connected to the second adder input modulo p ₂ , the first output is connected simultaneously to the input of the 2nd inverter of the private output unit and to the first input of the sum storage register modulo p ₂ , the second and third inputs of which are connected to the input of the clock pulse and the output of the OR element, respectively, the output is connected to the first input of the 2nd sum selection multiplexer, the second input of which is connected to the output of the storage register of the reciprocal of the sum value modulo p ₂ , the second and third inputs of which are connected with the input of the clock pulse and the output of the OR element, respectively, the first input is connected to the output of the 2nd adder of the private output unit, the third input of which is continuously supplied with a logical unit, the second input is connected to the output of the storage register of module p ₂ , the first input is connected to the output of the 2nd inverter of the private output unit, similarly, the first output of the approximation row refinement unit is connected to the first inputs of the remainder storage registers modulo p _i and so on, finally, the first output of the approximation row refinement unit is connected to the first input of the remainder storage register modulo p _n , the second and third inputs of which are connected to the input of the clock pulse and the output of the OR element, respectively, and the output is connected to the first input of the adder modulo p _n whose output is connected to the information input of the demultiplexer modulo p _n whose control input is connected to the second output of the approximation row refinement unit, and the second output is connected to the second adder input modulo p _n , the first output is connected simultaneously to the input of the nth inverter of the private output unit and to the first input of the sum storage register modulo p _n , the second and third inputs of which are connected to the input of the clock pulse and the output of the OR element, respectively, the output is connected to the first input of the nth sum selection multiplexer, the second input of which is connected to the output of the storage register of the reciprocal of the sum value modulo p _n , the second and third inputs of which are connected to the input of the clock pulse and the output of the OR element, respectively, the first input is connected to the output of the nth adder of the private output unit, the third input of which is continuously supplied with a logical unit, the second input is connected to the output of the storage register of module p _n , the first input is connected to the output of the nth inverter of the private output unit, the first output of the positional characterization unit is connected to the first input of the character holding register, the second and third inputs of which are connected to the input of the clock pulse and the output of the OR element, respectively, the output is simultaneously connected to the control inputs multiplexers for selecting the sum and the control input of the multiplexer for equality of absolute magnitude of the dividend and the divisor, the first input of which is connected to the output of the storage register of the value "-1", the second input is It is connected to the storage register of the value “1”, and the output to the first input of the private selector multiplexer, the second input of which is connected to the output of the storage register of the sum in the RNS, n + 1 and n + 2 inputs of which are connected to the clock input and output OR element, respectively, and the inputs from the 1st to the nth are connected to the outputs of the sum selection multiplexers from the 1st to the nth, respectively, the control input of the private output multiplexer is connected to the output of the holding register, the second and third inputs of which are connected to the clock input pulse and output eleme OR, respectively, the first input is connected to the second output of the comparison unit, which is simultaneously connected to the second input of the OR element of the private output unit, the first input of which is connected to the first output of the comparison unit, and the output is connected to the input of the delay element, the output of which is connected to the second input of the element OR, the output of the private output multiplexer is connected to the first input of the private storage register, the second and third inputs of which are connected to the input of the clock pulse and the output of the OR element, respectively, and the output is connected n with output private output.

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