RU2546998C2 - Method of comparative test for reliability of batches of integrated circuits - Google Patents

Abstract

FIELD: testing technology.

SUBSTANCE: invention relates to microelectronics, namely to methods of ensuring quality and reliability of semiconductor integrated circuits (ICs). Essence: the equal number of products (at least 10 per a batch) is randomly selected from IC batches and the value of the informative parameter is measured. Then for each IC of all samples, five ESR of one and five ESR of other polarity with potential maximum allowed by specifications is supplied. The following IC terminals should be exposed to effect of ESR: power - a common point, input - power, output - power, input - output. Then the value of the informative parameter is measured. Then all ICs are stored under normal conditions for 72 hours. The value of the informative parameter is measured. Thermal annealing of all ICs is carried out at a temperature T=100°C. The value of the informative parameter is measured. Then the values of Δ₁, Δ₂, Δ₃ for each IC are determined. From the values of Δ₁, Δ₂, Δ₃ the relative reliability of the IC bathes is determined.

EFFECT: ensuring quality and reliability of semiconductor integrated circuits.

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Description

The invention relates to microelectronics, and in particular to methods for ensuring the quality and reliability of semiconductor integrated circuits (ICs), and can be used to comparatively evaluate the reliability of batches of ICs both in the production process and during input control at the manufacturer of electronic equipment.

There is a method of comparatively evaluating the reliability of batches of semiconductor products (PPI) [1], according to which PPI is subjected to mechanical and ESD effects at values that are maximum permissible in TU, and comparison of batches of PPI for reliability is carried out by comparing the minimum, average and maximum values informative parameter before and after tests.

The method used is a comparative assessment of the reliability of IS batches [2], according to which, on arbitrary IS samples from batches, dynamic parameters are measured before and after exposure to five electrostatic discharges of different polarity (ESD), which are maximum permissible according to technical conditions (TU ), and temperature annealing at the permissible maximum crystal temperature, and ESD is supplied to each of the pairs of IC outputs: input - common point, output - common point, power - common point, input-output, number of cycles Procedure ESR and temperature annealing is not less than three, the number of failed ICs conclude comparative reliability IP parties.

The disadvantage of this method is the complexity of the tests. The invention is aimed at eliminating this drawback.

The proposed method of comparative tests for the reliability of IS batches is based on measuring the informative parameter X in the initial state, after exposure to the IS of five ESD pulses of both polarities with a potential that is maximum permissible according to TU, after storage for 72 hours under normal conditions (atmospheric pressure, temperature T = 22 ± 5 ° C), after thermal annealing at a temperature of T _anne = 100 ° C for 2 hours and a comparison of three values: Δ ₁ = X _beg -X _ESR , Δ ₂ = X _ESR -X _xp , Δ ₃ = X _xp -X _otzh , where X _beg - the value of the informative parameter at the beginning of measurements (in the initial state), X _ESR is the value of the informative parameter after exposure to ESR, X _xp is the value of the informative parameter after storage for 72 hours, X _anne is the value of the informative parameter after thermal annealing at a temperature of T = 100 ° C.

The method is as follows: from batches of IP (the number of batches is unlimited, the IP should be of the same type), the same number of products (at least 10 from each batch) is selected by random sampling and the value of the informative parameter is measured. Then, for each IC of all samples, five ESD of one and five ESD of the other polarity are fed with the potential maximum permissible in terms of specifications. The following IP conclusions should be exposed to ESD: power - common point, input - power, output - power, input-output. Then measure the value of the informative parameter. Further, all IPs are stored under normal conditions for 72 hours. The value of the informative parameter is measured. Thermal annealing of all ICs is carried out at a temperature of T = 100 ° C. The value of the informative parameter is measured. Next, for each IP, the values of Δ ₁ , Δ ₂ , Δ _{3 are found} . The values of Δ ₁ , Δ ₂ , Δ ₃ judge the comparative reliability of the batches of IP.

. На каждой ИС было измерено значение шумового напряжения $$\overline{U_{ШНАЧ}^2}$$

по выводам питание - общая точка (выводы 14-7). Измерение НЧШ проводилось при токе 7,5 мА, с полосой частот 200 Гц, при центральной частоте 1000 Гц. Затем ИС подвергались воздействию ЭСР потенциалом 200 В. Воздействие проводилось следующим образом. ЭСР подавался на следующие выводы ИС: питание - общая точка (выводы 14-7), вход - питание (выводы 2-14), выход - питание (выводы 1-14), вход-выход (выводы 1-2). Сначала подавалось пять ЭСР одной полярности, затем пять ЭСР другой полярности. После этого замеряли среднеквадратичное значение напряжения НЧШ после ЭСР $$\overline{U_{ШЭСР}^2}$$

. Далее ИС хранились в нормальных условиях в течение 72 часов. Замеряли среднеквадратичное значение напряжения НЧШ после хранения $$\overline{U_{ШХР}^2}$$

. Провели термический отжиг всех ИС при температуре Т=100°С. Замеряли среднеквадратичное значение напряжения НЧШ после ЭСР $$\overline{U_{ШОТЖ}^2}$$

. Далее Для каждой ИС нашли значения величин $${\Delta }_1=\overline{U_{ШНАЧ}^2}-\overline{U_{ШЭСР}^2}$$

, $${\Delta }_2=\overline{U_{ШЭСР}^2}-\overline{U_{ШХР}^2}$$

, $${\Delta }_3=\overline{U_{ШХР}^2}-\overline{U_{ШОТЖ}^2}$$

. Результаты измерения величин среднеквадратичного значения напряжения НЧШ, а также значения величин Δ₁, Δ₂, Δ₃ представлены в таблице 1 (для выборки из партии 1) и в таблице 2 (для выборки из партии 2).The method was tested on samples of two batches of IS type K155LE1 (four logical elements 2OR-NOT, made by TTL technology with oxide insulation of pockets). From each batch of IPs, 10 IPs were selected by random sampling. As an informative parameter, the rms value of the low-frequency noise voltage (LFN) was chosen $$\overline{U_W^2}$$

. The noise voltage value was measured on each IC. $$\overline{U_{WN\mathrm{BUT}H}^2}$$

according to the conclusions, the power is a common point (conclusions 14-7). The LF measurement was carried out at a current of 7.5 mA, with a frequency band of 200 Hz, at a center frequency of 1000 Hz. Then, the IPs were exposed to ESDs with a potential of 200 V. The impact was carried out as follows. ESD was supplied to the following IS outputs: power — common point (pins 14–7), input – power (pins 2–14), output – power (pins 1–14), input – output (pins 1-2). First, five ESDs of one polarity were supplied, then five ESDs of another polarity. After that, the rms voltage of the LFN was measured after ESD $$\overline{U_{WE\mathrm{FROM}R}^2}$$

. Further, the ISs were stored under normal conditions for 72 hours. Measured the rms voltage of the low-frequency voltage after storage $$\overline{U_{WXR}^2}$$

. Conducted thermal annealing of all ICs at a temperature of T = 100 ° C. Measured the rms voltage of the low-frequency voltage after ESD $$\overline{U_{W\mathrm{ABOUT}TF}^2}$$

. Further, for each IP, the values of $${\Delta }_{\mathrm{one}}=\overline{U_{WN\mathrm{BUT}H}^2}-\overline{U_{WE\mathrm{FROM}R}^2}$$

, $${\Delta }_2=\overline{U_{WE\mathrm{FROM}R}^2}-\overline{U_{WXR}^2}$$

, $${\Delta }_3=\overline{U_{WXR}^2}-\overline{U_{W\mathrm{ABOUT}TF}^2}$$

. The results of measuring the values of the rms voltage of the LFN, as well as the values of Δ ₁ , Δ ₂ , Δ _{3 are} presented in table 1 (for sampling from lot 1) and in table 2 (for sampling from lot 2).

Table 1 Test results for a sample of the batch 1

, мкВ² $$\overline{U_{WN\mathrm{BUT}H}^2}$$

μV ² $$\overline{U_{WE\mathrm{FROM}R}^2}$$

μV ² $$\overline{U_{WXR}^2}$$

μV ² $$\overline{U_{W\mathrm{ABOUT}TF}^2}$$

μV ² IP number Δ ₁ Δ ₂ Δ ₃ one 14.48 14.61 14.46 14.48 -0.13 0.15 -0.02 2 14.19 14.30 14.29 14.26 -0.11 0.01 0,03 3 14.81 14.9 14.88 14.86 -0.09 0.02 0.02 four 14.68 14.76 14.79 14.79 -0.08 -0.03 0 5 14,4 14.65 14.41 14.34 -0.25 0.24 0,07 6 14.68 14.76 14.7 14.72 -0.08 0.06 -0.02 7 14.27 14.34 14.34 14.39 -0.07 0 -0.05 8 14.43 14.69 14.38 14.47 -0.26 0.31 -0.09 9 14.52 14.60 14.58 14.56 -0.08 0.02 0.02 10 14.48 14.64 14.64 14.66 -0.16 0 -0.02

table 2 Test results for a sample from batch 2

, мкВ² $$\overline{U_{WN\mathrm{BUT}H}^2}$$

μV ² $$\overline{U_{WE\mathrm{FROM}R}^2}$$

μV ² $$\overline{U_{WXR}^2}$$

μV ² $$\overline{U_{W\mathrm{ABOUT}TF}^2}$$

μV ² IP number Δ ₁ Δ ₂ Δ ₃ one 14.23 14.48 14.32 14.33 -0.25 0.16 -0.01 2 14.28 15.07 14,99 14.45 -0.79 0.08 -0.54 3 14.15 14.29 14.30 14.26 -0.14 -0.01 0.04 four 14.11 14.48 14.48 14.22 -0.37 0 0.26 5 14.18 14.31 14.22 14.24 -0.13 0.09 -0.02 6 14.22 14.37 14.30 14.29 -0.15 0,07 0.01 7 14,4 14.65 14.66 14.59 -0.25 -0.01 0,07 8 14.29 14.32 14.30 14.29 -0.03 0.02 0.01 9 14.46 14.59 14.46 14.40 -0.13 0.13 0.06 10 14.21 14.35 14.34 14.36 -0.14 0.01 -0.02

From the tables it can be seen that for each IC the values Δ ₁ , Δ ₂ , Δ ₃ can have both negative and positive values, and Δ _{1 is} always negative. Values Δ ₂ , Δ ₃ can be both positive and negative. In the first sample, the total number of negative values of Δ ₂ and Δ _{3 is} nine (we consider zero for a negative value). In the second sample, the total number of negative values of Δ ₂ and Δ _{3 are} seven. Thus, the total number of negative values of Δ ₁ , Δ ₂ , Δ ₃ in the first sample is greater than in the second. Based on this, we conclude that the second batch is more reliable than the first.

Information sources

1. RF patent No. 2381514, G01R 31/26, publ. 02/10/2010.

2. RF patent No. 2386975, G01R 31/26, publ. 04/20/2010.

Claims (1)

The method of comparative tests for the reliability of batches of integrated circuits, according to which, on arbitrary identical samples from batches comprising at least 10 integrated circuits, the rms value of the low-frequency noise voltage is measured before and after exposure to five polarities by ESD of both polarities with the maximum permissible potential according to the technical specifications, to the conclusions “power - common point”, “input - power”, “output - power”, after storage under normal conditions for 72 hours and after temperature o Gigue for 2 hours at a temperature of 100 ° C, characterized in that after measuring for each IP find the values of Δ ₁ = X -X _{nach ESR,} Δ ₂ = X -X _{ESR hr,} Δ ₃ = X -X _{hr ann,} where X _beg is the rms value of the low-frequency noise voltage before exposure to ESD, X _ESR is the rms value of the low-frequency noise voltage after exposure to ESD, X _xr is the rms voltage of the low-frequency noise after storage for 72 hours, X _otzh is the rms voltage of the low-frequency noise after thermal otzh ha at a temperature T = 100 ° C, the ratio of the total number of negative values of Δ _1, Δ _2, Δ ₃ for comparative samples judged reliability IP parties.