RU2543313C2 - Current mirror with lower output voltage - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: current mirror with lower output voltage contains the first and the second input MOS transistors, connected in series between a power bus and a current mirror input, and the first and the second output MOS transistors, connected in series between the power bus and current mirror output. Sources and isolation pockets of the input MOS transistors are connected to the power bus. Gates of all the transistors and isolation pockets of the output MOS transistors are connected to the current mirror input.

EFFECT: higher current transmission accuracy, while keeping high output resistance and low output voltage.

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Description

Technical field

The invention relates to the field of radio engineering and electronics and can be used as a current source or a high-impedance load of an amplifier in the structure of analog microcircuits and blocks for various functional purposes.

State of the art

The development of modern microelectronics is accompanied by a decrease in the size of chip elements and a decrease in the supply voltage. At the same time, the output resistance of transistors and the gain of analog blocks are reduced in CMOS chips.

The traditional way to increase the gain is the sequential (cascode) inclusion of MOS transistors with the supply to their gates of a different bias voltage [1,2]. However, when the transistors are casually turned on, the minimum output voltage on the transistors connected in series increases, which limits the dynamic range of the output signal.

A technical solution is known [3], where two stages are used in the input circuit of the current mirror for independent bias of transistor gates in the output circuit. In this case, the voltage difference across the gates of the MOS transistors in the output circuit is determined by the difference in the width of the transistors (w) in two stages of the input circuit (Fig. 1).

The disadvantages of this technical solution include the high input voltage; an increase in the number of elements in the circuit, as well as a decrease in the accuracy of current transfer from the input circuit of the current mirror to the output due to the different modes of operation of transistors.

Disclosure of invention

The task of the invention is to lower the minimum output voltage of the current mirror while maintaining a high output resistance. The technical result that allows you to complete the task is to reduce the supply voltage or increase the dynamic range of the output signal of the analog block of the current mirror due to the use in the cascode circuit of MOS transistors with different threshold voltage.

According to the invention, this technical result is achieved due to the fact that in the current mirror with a reduced output voltage (Fig. 2), including the first (1) and second (2) input MOS transistors connected in series between the power bus (3) and the current input mirrors (4), as well as the first (5) and second (6) output MOS transistors connected in series between the power bus (3) and the output of the current mirror (7); the sources and isolating "pockets" of the first input (1) and first output (5) MOS transistors are connected to the power bus (3); the gates of all MOS transistors and insulating pockets of the second input (2) and second output (6) MOS transistors are connected to the input of the current mirror.

The first output (5) and first input (1) MOS transistors are implemented topologically as a block of parallel-connected sections of minimum width (w), while their threshold voltage increases.

Additionally, the difference in threshold voltages of MOS transistors increases due to the use of insulating “pockets” with a high level of doping.

The increased output resistance of the current mirror is achieved by increasing the voltage at the drain of the first output MOS transistor (5) to the level of transition to the shallow region of the output current-voltage characteristic. The value of this voltage is equal to the difference between the gate-source voltages of the first (5) and second (6) output MOS transistors. This voltage difference is the sum of the difference in threshold voltages, the influence of the positive bias of the insulating pocket, and a twice higher current density in the first output MOS transistor (5).

Brief Description of the Drawings

Figure 1 presents a diagram of a current mirror with a reduced output voltage based on the same MOS transistors (w is the minimum width of the used MOS transistors).

Figure 2 presents a diagram of a current mirror with a reduced output voltage based on MOS transistors with different threshold voltages (w is the minimum width of the used MOS transistors).

The implementation of the invention

The main objective of the invention is to reduce the number of elements in the circuit and increase the accuracy of the current transmission of the current mirror while maintaining a high output resistance and low output voltage.

The problem is solved in that in the circuit of the cascode current mirror MOS transistors with different threshold voltages are used [4]. The first input (1) and first output (5) MOS transistors have an increased threshold voltage modulo, and the second input (2) and second output (6) MOS transistors have a reduced threshold voltage modulo.

The input first (1) and second (2) transistors are connected in series between the power bus (3) and the input of the current mirror (4). The output first (5) and second (6) transistors are connected in series between the power bus (3) and the output of the current mirror (7). The sources and insulating pockets of the first output (5) and first input (1) transistors are connected to the power bus (3). The gates of all MOS transistors and insulating pockets of the second input (2) and second output (6) transistors are connected to the input of the current mirror (4). This inclusion reduces the gate-source voltage of the second input (2) and second output (6) MOS transistors and increases the drain-source voltage of the first input (1) and first output (5) transistors.

An increase in the magnitude of the threshold voltage of the first input (1) and first output (5) MOS transistors is achieved by their implementation in the form of a block of parallel-connected transistors of the minimum width (w), and a decrease in the threshold voltage by combining the gate electrodes and an insulating "pocket" [4 ]. Topological and circuit changes in the threshold voltage do not require changes in the technology for the production of microcircuits.

An additional increase in the difference in threshold voltages of MOS transistors can be achieved by using insulating “pockets” with different doping levels.

Due to the fact that the threshold voltage of the second input (2) and second output (6) transistors is less in absolute value than the first input (1) and first output (5) transistors, the voltage at the serial connection points of the input and output transistors increases and reaches the level at which the output current-voltage characteristics of the first input (1) and first output (5) transistors go into the region with high resistance.

According to the literature [1], the operating modes of the current mirror with an output voltage of at least 0.1 V are actually used. Therefore, the difference in threshold voltage of MOS transistors should be greater than 0.1 V. The proposed solution allows to reduce the minimum output voltage of the cascode current mirror to 0, 2 V without reducing output impedance.

The technical solution proposed as an invention makes it possible to reduce the supply voltage of analog blocks, including in microcircuits based on nanometer CMOM technologies.

The feasibility of the invention is confirmed by the results of modeling the characteristics of the current mirror using practically proven methods, licensed software (Specter Cadence) and verified element models (Silterra Microelectronics).

[1] S. Chatterjee, K. Pun, N. Stanic ', Y. Tsividis, P Kinget. Analog Circuit Design Techniques at 0.5 V. Springer, 2007.

[2] Enns V.I., Kobzev Yu.M. Designing analog CMOS chips. Developer Quick Reference / Edited by Ph.D. tech. sciences V.I. Anns. - M .: Hot line - Telecom. - 2005 .-- 454 p.: Ill.

[3] P.E. Allen, D.R. Holberg. CMOS Analog Circuit Design. New York, Oxford, Oxford University Press, 1996.

[4] A.M. Walke, N. M. Mohapatra. Effects of Small Geometries on the Performance of Gate First High-k Metal Gate NMOS Transistors. IEEE Transactions on Electron Devices. V. 59, N. 10, 2012.

Claims (3)

1. A current mirror with a reduced output voltage, including the first and second input MOS transistors connected in series between the power bus and the input of the current mirror, as well as the first and second output MOS transistors connected in series between the power bus and the output of the current mirror; the sources and isolating "pockets" of the first input and first output MOS transistors are connected to the power bus, characterized in that the gates of all MOS transistors and the isolating pockets of the second input and second output MOS transistors are connected to the input of the current mirror. 2. The current mirror with a reduced output voltage according to claim 1, characterized in that the first output and first input MOS transistors are structurally implemented as a block of parallel-connected sections of minimum width. 3. The current mirror with a reduced output voltage according to claim 1, characterized in that the difference in threshold voltages of MOS transistors is achieved by using insulating "pockets" with different levels of doping.

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