RU158424U1 - CMOS DIFFERENTIAL AMPLIFIER WITH INCREASED AMPLIFICATION FACTOR - Google Patents

Abstract

CMOS differential amplifier with increased gain, including a current-stabilizing two-terminal device connected between the common bus and the combined sources of the first and second input Ν-ΜΟΠ transistors, the gates of which are connected to the inverting and non-inverting inputs of the differential amplifier, respectively, with the drain of the first (input) Ν- ΜΟΠ the transistor is connected to the source of the (output) Ν-ΜΟΠ transistor, the gate of which is connected to the gate and drain of the fourth (load) R-MOS transistor, the drain is connected to the drain the third (output) R-MOS transistor and the output of the differential amplifier; the drain of the second (input) Ν-ΜΟΠ input transistor is connected to the combined gate and drain of the fourth R-MOS transistor and the gate of the third R-MOS transistor; the sources of the third and fourth R-MOS transistors are connected to the power bus, and the insulating "pockets" of all MOS transistors are connected to the sources of these transistors, characterized in that additional elements are introduced into the circuit: - the sixth (optional) R-MOS transistor connected by a gate with the drain of the second (input) Ν-ΜΟΠ transistor, the source with the bus of positive power supply, and the drain with the combined sources of the input Ν-ΜΟΠ transistors; - the seventh (optional) Ν-ΜΟΠ transistor in the diode connection between the drains of the second Ν-ΜΟΠ t a transistor and a fourth R-MOS transistor.

Description

The utility model relates to the field of radio engineering and electronics. In particular, to integrated circuits based on CMOS technology, and can be used as a device for amplifying analog signals in the structure of analog microcircuits for various functional purposes (for example, in operational amplifiers (op amps), comparators).

The objective of this utility model is to increase the voltage gain of a CMOS differential amplifier by including an additional amplifier transistor in the amplifier circuit. The technical result consists in increasing the gain of the differential amplifier stage by about 5 times without compromising its frequency characteristics. According to a utility model, this technical result is achieved due to the fact that an additional amplifying transistor modulates the current of the differential stage. The symmetric inclusion of transistors in the circuit provides a reduced zero-bias voltage of the differential signal.

Known inventions RU 2469467 (2011), RU 2455758 (2011), RU 2463703 (2011), which contain a number of technical solutions to increase the gain of differential amplifiers. In this case, an increase in the gain of the CMOS amplification stages is usually achieved by increasing the gate length of the MOS transistors or by using a series (cascode) switching on of the amplifying transistors. However, with an increase in the length of the gates, the performance of the amplifier decreases, and the cascode inclusion of transistors increases the minimum supply voltage and requires the introduction of an additional reference voltage block into the circuit.

The closest in technical essence to the prototype of the proposed utility model can be considered the technical solution (Fig. 1) described in the utility model RU 132651.

The objective of the proposed utility model is to increase the voltage gain of a single-stage CMOS differential amplifier. The technical result, which allows to achieve the task, consists in increasing the gain of the differential amplifier stage by 5–6 times without degrading its frequency characteristics by turning on an additional amplifying P-MOS transistor modulating the current of the differential cascade, and an additional compensating N-MOS transistor reducing voltage zero offset of the input differential signal due to voltage equalization at the drains of the input MOS transistors.

According to the proposed utility model, this technical result is achieved due to the fact that in the CMOS differential cascade (Fig. 1) containing a current-stabilizing two-terminal 1 connected between the common bus 2 and the combined sources of the first 3 and second 4 input N-MOS transistors, the gates which are connected to the inverting 5 and non-inverting 6 inputs of the differential amplifier, respectively, moreover, the drain of the first (input) N-MOS transistor 3 is connected to the source of the (output) N-MOS transistor 11, the gate of which is connected to the gate and fourth eye (load) P-MOS transistor, a drain connected to the drain of the third (output) P-MOS transistor 7 and the output of the differential amplifier 8; the drain of the second (input) N-MOS input transistor 4 is connected to the combined gate and drain of the fourth P-MOS transistor 9 and the gate of the third P-MOS transistor 7; the sources of the third 7 and fourth 9 P-MOS transistors are connected to the power bus 10, moreover, the insulating “pockets” of all MOS transistors are connected to the sources of these transistors, additional elements are introduced (Fig. 2):

- the sixth (optional) P-MOS transistor 12 connected by a gate to the drain of the second input N-MOS transistor, the source to the bus of positive power supply, and the drain to the combined sources of the input N-MOS transistors 3, 4;

- the seventh (optional) N-MOS transistor 13 (Fig. 3) in the diode connection between the drains of the second input N-MOS transistor 4 and the fourth P-MOS transistor 9.

In FIG. 1 shows a diagram of a differential amplifier selected as a prototype of the proposed utility model.

In FIG. 2 is a diagram of a CMOS differential amplifier with an additional P-MOS amplifier transistor.

In FIG. 3 shows a diagram of a CMOS differential amplifier with additional: P-MOS amplifying and N-MOS balancing transistors.

In FIG. 4 shows the frequency dependence of the voltage gain for the prototype and the proposed utility model.

The implementation of the utility model is as follows. CMOS differential amplifier with increased gain (Fig. 2), including a current-stabilizing two-terminal 1 connected between a common bus 2 and the combined sources of the first 3 and second 4 input N-MOS transistors, the gates of which are connected to the inverting 5 and non-inverting 6 inputs of the differential amplifier, respectively, moreover, the drain of the first (input) N-MOS transistor 3 is connected to the source of the (output) N-MOS transistor 11, the gate of which is connected to the gate and drain of the fourth (load) P-MOS transistor, the drain under connected to the drain of the third (output) P-MOS transistor 7 and the output of the differential amplifier 8; the drain of the second (input) N-MOS input transistor 4 is connected to the combined gate and drain of the fourth R-MOS transistor 9 and the gate of the third P-MOS transistor 7; the sources of the third 7 and fourth 9 P-MOS transistors are connected to the power bus 10, and the insulating “pockets” of all MOS transistors are connected to the sources of these transistors, contains additional elements:

- the sixth (optional) P-MOS transistor 12 connected by a gate to the drain of the second input N-MOS transistor 4, the source to the bus of positive power supply 10, and the drain to the combined sources of the input N-MOS transistors 3, 4;

- the seventh (optional) N-MOS transistor 13 in the diode connection between the drains of the second N-MOS transistor 4 and the fourth P-MOS transistor 9.

The technical result is achieved due to the fact that: the seventh (additional) balancing N-MOS transistor 13 reduces the bias voltage due to the equalization of the voltages at the drains of the input N-MOS transistors 3, 4 of the differential amplifier; the drain current of the sixth (optional) P-MOS transistor 12 synchronously modulates the entire current of the differential amplifier stage. The overall gain of the differential amplifier increases due to the combined effect of reducing the zero offset and synchronous modulation of the current of the entire cascade.

In FIG. 4 shows the frequency dependence of the gain obtained by modeling for the proposed utility model and technical solution, selected as a prototype. According to the graphs, it can be judged that the voltage gain of the proposed utility model increases by at least four times in comparison with the gain of the prototype. Thus, the proposed circuitry solution of the utility model demonstrates an advantage in voltage gain in comparison with the known differential amplifier.

The feasibility of the utility model is confirmed by simulation results using licensed CAD tools from Cadence Microsystems.

Used Books:

[1] Rakitin V.V. Integrated circuits on CMOS transistors. Textbook - M.: MIPT. - 2007 - 308 s.

[2] Patent for utility model RU No. 132651 "CMOS differential amplifier with high gain"

[3] Anns V.I., Kobzev Yu.M. Designing analog CMOS chips. Developer Quick Reference / Edited by Ph.D. tech. sciences V.I. Anns. - M .: Hot line - Telecom. - 2005 .-- 454 s: ill.

Claims (1)

CMOS differential amplifier with increased gain, including a current-stabilizing two-terminal device connected between the common bus and the combined sources of the first and second input Ν-ΜΟΠ transistors, the gates of which are connected to the inverting and non-inverting inputs of the differential amplifier, respectively, with the drain of the first (input) Ν- ΜΟΠ the transistor is connected to the source of the (output) Ν-ΜΟΠ transistor, the gate of which is connected to the gate and drain of the fourth (load) R-MOS transistor, the drain is connected to the drain the third (output) R-MOS transistor and the output of the differential amplifier; the drain of the second (input) Ν-ΜΟΠ input transistor is connected to the combined gate and drain of the fourth R-MOS transistor and the gate of the third R-MOS transistor; the sources of the third and fourth R-MOS transistors are connected to the power bus, and the insulating "pockets" of all MOS transistors are connected to the sources of these transistors, characterized in that additional elements are introduced into the circuit: - the sixth (optional) R-MOS transistor connected by a gate to the drain of the second (input) Ν-ΜΟΠ transistor, the source to the bus of positive power supply, and the drain to the combined sources of the input Ν-ΜΟΠ transistors; - the seventh (optional) Ν-ΜΟΠ transistor in the diode connection between the drains of the second Ν-ΜΟΠ transistor and the fourth R-MOS transistor.

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