CN115437448B - Current source circuit, reference voltage circuit and chip - Google Patents

Current source circuit, reference voltage circuit and chip Download PDF

Info

Publication number
CN115437448B
CN115437448B CN202211365971.7A CN202211365971A CN115437448B CN 115437448 B CN115437448 B CN 115437448B CN 202211365971 A CN202211365971 A CN 202211365971A CN 115437448 B CN115437448 B CN 115437448B
Authority
CN
China
Prior art keywords
mos
mos transistor
tube
mos tube
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202211365971.7A
Other languages
Chinese (zh)
Other versions
CN115437448A (en
Inventor
束克留
万海军
韩兴成
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suzhou Powerlink Microelectronics Inc
Original Assignee
Suzhou Powerlink Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suzhou Powerlink Microelectronics Inc filed Critical Suzhou Powerlink Microelectronics Inc
Priority to CN202211365971.7A priority Critical patent/CN115437448B/en
Publication of CN115437448A publication Critical patent/CN115437448A/en
Application granted granted Critical
Publication of CN115437448B publication Critical patent/CN115437448B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)

Abstract

The invention discloses a current source circuit, a reference voltage circuit and a chip, wherein the current source circuit comprises: the current mirror unit comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube and a current mirror unit; a first MOS transistor, a second MOS transistor,At least two MOS tubes in the third MOS tube and the fourth MOS tube work in different regions, and at least one MOS tube in the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube is provided with a transistor
Figure 128466DEST_PATH_IMAGE001
The characteristic current. According to the current source circuit, the reference voltage circuit and the chip of the embodiment of the invention, the current source circuit, the reference voltage circuit and the chip can be produced by adopting a unique combination mode of four transistors and assisting a current mirror unit
Figure 778890DEST_PATH_IMAGE001
The characteristic current can generate a reference voltage with a low temperature coefficient on the active resistor by reasonably adjusting parameters, and the current source circuit has a simple structure, only uses a CMOS (complementary metal oxide semiconductor) device, and has the advantages of extremely low power consumption and extremely small area.

Description

Current source circuit, reference voltage circuit and chip
Technical Field
The present invention relates to the field of integrated circuits, and more particularly, to a current source circuit, a reference voltage circuit and a chip.
Background
The voltage reference circuit is widely used in various analog integrated circuits to provide reference voltage or generate reference current for core circuit modules such as amplifiers and converters. In many applications, the low temperature coefficient is a characteristic that the voltage reference needs to possess, and the voltage temperature coefficient is usually in the order of several to tens of ppm.
Although the conventional bandgap reference circuit can meet the requirement of temperature coefficient, there is usually a trade-off between area and power consumption, i.e. meeting low power consumption requires a large resistor and thus occupies a large chip area. In recent years, with the rise of applications of internet of things and sensors, an integrated circuit in a passive sensing node generally needs to maintain extremely low power consumption to meet the requirement of ultra-long standby, and meanwhile, the cost requirement of a single node is severe. Therefore, in such circuits, the requirements for the temperature coefficient and the precision of the reference source are relaxed compared with the conventional application, but the reference source requires the characteristics of extremely low power consumption and small area, so that the conventional bandgap reference source circuit is not suitable for use.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Disclosure of Invention
The invention aims to provide a current source circuit, a reference voltage circuit and a chip, which have the characteristics of extremely low power consumption and extremely small area.
To achieve the above object, an embodiment of the present invention provides a current source circuit, including: the current mirror unit comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube and a current mirror unit.
The source electrode of first MOS pipe and second MOS pipe links to each other and links to each other with earth voltage or mains voltage, the drain electrode of first MOS pipe links to each other with the grid of second MOS pipe, the source electrode of third MOS pipe and the source electrode of fourth MOS pipe, the grid of first MOS pipe links to each other with the drain electrode of third MOS pipe, the grid of third MOS pipe links to each other with the grid of fourth MOS pipe, the grid and the drain electrode of fourth MOS pipe link to each other, current mirror unit links to each other with the drain electrode of second MOS pipe, the drain electrode of fourth MOS pipe and the drain electrode of third MOS pipe, at least two MOS pipes in first MOS pipe, second MOS pipe, third MOS pipe and fourth MOS pipe work in different work areas to form on at least one MOS pipe in first MOS pipe, second MOS pipe, third MOS pipe and fourth MOS pipe and have
Figure 853221DEST_PATH_IMAGE001
The characteristic current->
Figure 290019DEST_PATH_IMAGE002
Refers to the square of the temperature, and u refers to the mobility of the semiconductor carriers as a function of temperature.
In one or more embodiments of the present invention, the current mirror unit includes a fifth MOS transistor, a sixth MOS transistor, and a seventh MOS transistor, gates of the fifth MOS transistor, the sixth MOS transistor, and the seventh MOS transistor are connected, sources of the fifth MOS transistor, the sixth MOS transistor, and the seventh MOS transistor are connected to a ground voltage or a power supply voltage, a drain of the seventh MOS transistor is connected to the gate, a drain of the fifth MOS transistor is connected to a drain of the third MOS transistor, a drain of the sixth MOS transistor is connected to a drain of the fourth MOS transistor, and a drain of the seventh MOS transistor is connected to a drain of the second MOS transistor.
In one or more embodiments of the present invention, a length of the conduction channel of the first MOS transistor is the same as a length of the conduction channel of the second MOS transistor, and/or a length of the conduction channel of the third MOS transistor is the same as a length of the conduction channel of the fourth MOS transistor.
In one or more embodiments of the invention, the first MOS transistor and the second MOS transistor operate in a sub-threshold region, the third MOS transistor operates in a linear region, and the fourth MOS transistor operates in a saturation region.
In one or more embodiments of the present invention, the current source circuit further includes a trimming circuit, where the trimming circuit includes one or more adjusting units, and the adjusting units are connected to the drain and the source of the third MOS transistor.
In one or more embodiments of the present invention, the adjusting unit includes a controllable switch and an adjusting tube, a first end of the controllable switch is connected to a drain of the adjusting tube, a second end of the controllable switch is connected to a drain of the third MOS tube, a source of the adjusting tube is connected to a source of the third MOS tube, if a plurality of adjusting units are provided, gates of the adjusting tubes are connected, or
The adjusting unit comprises an adjusting tube, a source electrode of the adjusting tube is connected with a source electrode of the third MOS tube, a drain electrode of the adjusting tube is connected with a drain electrode of the third MOS tube, and a grid electrode of the adjusting tube is a control end.
The invention also discloses a reference voltage circuit, which comprises the current source circuit, a copying unit and a resistance unit, wherein the copying unit is connected with the current mirror unit to copy
Figure 120571DEST_PATH_IMAGE001
A characteristic current, the replica unit being connected to the resistance unit on a ^ basis>
Figure 35438DEST_PATH_IMAGE001
The characteristic current obtains a reference voltage with a low temperature coefficient on the resistance unit.
In one or more embodiments of the invention, the replica cell includes a ninth MOS transistor, a source of the ninth MOS transistor is connected to a power supply voltage or a ground voltage, and a gate of the ninth MOS transistor is connected to the current mirror cell to replicate
Figure 369467DEST_PATH_IMAGE001
And the drain electrode of the ninth MOS tube is connected with the resistance unit.
In one or more embodiments of the present invention, the resistance unit includes an eighth MOS transistor, a gate and a drain of the eighth MOS transistor are connected and connected to the replica unit, and a source of the eighth MOS transistor is connected to a ground voltage or a power supply voltage.
The invention also discloses a chip comprising the current source or the reference voltage circuit.
Compared with the prior art, the current source circuit, the reference voltage circuit and the chip provided by the embodiment of the invention can be produced by adopting a unique combination of four transistors and matching with the four transistors by a current mirror unit
Figure 977166DEST_PATH_IMAGE001
The characteristic current can generate a reference voltage with a low temperature coefficient on the active resistor by reasonably adjusting parameters, and the current source circuit has a simple structure, only uses a CMOS (complementary metal oxide semiconductor) device, and has the advantages of extremely low power consumption and extremely small area.
Drawings
Fig. 1 is a first circuit schematic of a current source circuit according to an embodiment of the invention.
Fig. 2 is a second circuit schematic of a current source circuit according to an embodiment of the invention.
FIG. 3 is a circuit schematic of a reference voltage circuit according to an embodiment of the present invention.
FIG. 4 is a graph of simulation results of the reference voltage output by the reference voltage circuit as a function of temperature, according to an embodiment of the present invention.
FIG. 5 is a circuit schematic of a reference voltage circuit according to another embodiment of the present invention.
Detailed Description
Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but it should be understood that the scope of the present invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element or component but not the exclusion of any other element or component.
Example 1
As shown in fig. 1, a current source circuit includes: the current mirror unit comprises a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4 and a current mirror unit 10.
In this embodiment, the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4 are all N-channel MOS transistors. The source electrode of the first MOS tube M1 and the second MOS tube M2 are connected and are connected with the ground voltage, the drain electrode of the first MOS tube M1 is connected with the grid electrode of the second MOS tube M2, the source electrode of the third MOS tube M3 and the source electrode of the fourth MOS tube M4, the grid electrode of the first MOS tube M1 is connected with the drain electrode of the third MOS tube M3, the grid electrode of the third MOS tube M3 is connected with the grid electrode of the fourth MOS tube M4, and the grid electrode and the drain electrode of the fourth MOS tube M4 are connected. The current mirror unit 10 is connected to the drain of the second MOS transistor M2, the drain of the fourth MOS transistor M4, and the drain of the third MOS transistor M3, so that at least two MOS transistors of the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4 operate in different operating regions, and thus the current mirror unit is formed on the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4 to have a current mirror function
Figure 295015DEST_PATH_IMAGE001
A characteristic current, wherein>
Figure 13572DEST_PATH_IMAGE001
Refers to the currentIs based on the temperature characteristic of->
Figure 467687DEST_PATH_IMAGE003
Refers to the square of the temperature, and u refers to the mobility of the semiconductor carriers as a function of temperature.
The current mirror unit 10 includes a fifth MOS transistor M5, a sixth MOS transistor M6, and a seventh MOS transistor M7.
In this embodiment, the fifth MOS transistor M5, the sixth MOS transistor M6 and the seventh MOS transistor M7 are P-channel MOS transistors. The grid electrodes of the fifth MOS tube M5, the sixth MOS tube M6 and the seventh MOS tube M7 are connected, the source electrodes of the fifth MOS tube M5, the sixth MOS tube M6 and the seventh MOS tube M7 are connected and are connected with power supply voltage, the drain electrode of the seventh MOS tube M7 is connected with the grid electrode, the drain electrode of the fifth MOS tube M5 is connected with the drain electrode of the third MOS tube M3, the drain electrode of the sixth MOS tube M6 is connected with the drain electrode of the fourth MOS tube M4, and the drain electrode of the seventh MOS tube M7 is connected with the drain electrode of the second MOS tube M2.
Based on the above connection relationship, it can be obtained
Figure 511867DEST_PATH_IMAGE004
，/>
Figure 45573DEST_PATH_IMAGE005
Wherein is present>
Figure 567821DEST_PATH_IMAGE006
Is the voltage between the drain and the source of the third MOS transistor M3>
Figure 142022DEST_PATH_IMAGE007
Is the voltage between the gate and the source of the first MOS transistor M1->
Figure 91524DEST_PATH_IMAGE008
Is the voltage between the gate and the source of the second MOS transistor M2->
Figure 852806DEST_PATH_IMAGE009
Is the voltage between the gate and the source of the third MOS transistor M3,
Figure 444324DEST_PATH_IMAGE010
is the voltage between the gate and the source of the fourth MOS transistor M4.
In the present embodiment, the length of the conduction channel of the first MOS transistor M1 is set to be the same as the length of the conduction channel of the second MOS transistor M2, and the length of the conduction channel of the third MOS transistor M3 is set to be the same as the length of the conduction channel of the fourth MOS transistor M4. The ratio of the width to the length of the conductive channel of the first MOS transistor M1 to the width to the length of the conductive channel of the second MOS transistor M2 is
Figure 607453DEST_PATH_IMAGE011
As can be seen from fig. 1, the sources of the first MOS transistor M1 and the second MOS transistor M2 are connected, so that the first MOS transistor M1 and the second MOS transistor M2 have the same threshold voltage
Figure 727855DEST_PATH_IMAGE012
. The ratio of the width to the length of the conductive channels of the third MOS transistor M3 to the width to the length of the conductive channels of the fourth MOS transistor M4 is->
Figure 507592DEST_PATH_IMAGE013
As can be seen from fig. 1, the sources of the third MOS transistor M3 and the fourth MOS transistor M4 are connected, so that the third MOS transistor M3 and the fourth MOS transistor M4 have the same threshold voltage
Figure 371643DEST_PATH_IMAGE014
。
Under the BSIM model, the operation region of a transistor can be divided into three operation regions, i.e., a sub-threshold region, a linear region, and a saturation region. The first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3 and the fourth MOS transistor M4 can be generated as long as the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3 and the fourth MOS transistor M4 are not all in the same working area
Figure 389278DEST_PATH_IMAGE015
A characteristic current.
The following description will be given by taking a case where the first MOS transistor M1 and the second MOS transistor M2 are in a sub-threshold region, the third MOS transistor M3 is in a linear region, and the fourth MOS transistor M4 is in a saturation region as an example.
At this time, the drain of the first MOS transistor M1 is electrically connected
Figure 211740DEST_PATH_IMAGE016
（1）
Drain current of the second MOS transistor M2
Figure 947615DEST_PATH_IMAGE017
（2）
Drain current of the third MOS transistor M3
Figure 615357DEST_PATH_IMAGE018
（3）
Drain current of fourth MOS transistor M4
Figure 753077DEST_PATH_IMAGE019
（4）
The drain current of the first MOS transistor M1 is caused by setting the proportional relationship among the fifth MOS transistor M5, the sixth MOS transistor M6 and the seventh MOS transistor M7 of the current mirror unit 10
Figure 480862DEST_PATH_IMAGE020
And the drain current of the second MOS tube M2->
Figure 969612DEST_PATH_IMAGE021
Is->
Figure 175465DEST_PATH_IMAGE022
The drain current of the third MOS tube M3 is ^ er>
Figure 433271DEST_PATH_IMAGE023
And the drain current of the fourth MOS tube M4 +>
Figure 331957DEST_PATH_IMAGE024
Is->
Figure 776845DEST_PATH_IMAGE025
Thus, solving equations (1) - (4) can result in:
Figure 51969DEST_PATH_IMAGE026
(5)
wherein the content of the first and second substances,
Figure 164281DEST_PATH_IMAGE027
absolute temperature T, k-wave Alzheimer's constant, q-electron charge level->
Figure 233868DEST_PATH_IMAGE028
Is electron mobility, is->
Figure 431631DEST_PATH_IMAGE029
Is the gate oxide unit area capacitance and n is the sub-threshold gradient factor. Thus->
Figure 244867DEST_PATH_IMAGE030
K is a constant coefficient independent of temperature, and the currents of other branches are equal to ^ and ^>
Figure 477265DEST_PATH_IMAGE031
And (4) in proportion. So that the circuit can generate a signal with->
Figure 452174DEST_PATH_IMAGE032
The characteristic current.
As shown in fig. 2, the current source circuit further includes a trimming circuit 20, and the trimming circuit 20 is connected to the drain and the source of the third MOS transistor M3 to improve the robustness of the current source circuit.
The trimming circuit 20 comprises one or more adjusting units 21, each adjusting unit 21 comprises a controllable switch and an adjusting tube, the first end of each controllable switch is connected with the drain electrode of the corresponding adjusting tube, the second end of each controllable switch is connected with the drain electrode of the corresponding third MOS tube M3, the source electrode of each adjusting tube is connected with the source electrode of the corresponding third MOS tube M3, if the plurality of adjusting units 21 are arranged, the grid electrodes of the plurality of adjusting tubes are connected, and the number of the adjusting tubes connected with the third MOS tubes M3 can be adjusted through the number of the closed controllable switches.
The size of the third MOS transistor M3 after being connected with the regulating tube in parallel is regulated by regulating the number of the regulating tubes connected with the third MOS transistor M3 in parallel, so that the ratio of the width to the length of the third MOS transistor M3 to the fourth MOS transistor M4 is changed
Figure 137233DEST_PATH_IMAGE033
And further, the working area of the MOS tube is adjusted, the situation that the first MOS tube M1, the second MOS tube M2, the third MOS tube M3 and the fourth MOS tube M4 are in the same working area is ensured not to occur, and the robustness of the circuit is improved.
In this embodiment, the adjusting unit 21 may be provided in plural, and the specific number of the adjusting units 21 may be set according to the trimming range required in practice. The corresponding controllable switches are also provided with a plurality of first controllable switches S1, second controllable switches S2 to Nth controllable switches SN; the corresponding adjusting tubes are also provided with a plurality of first adjusting tubes MT0, second adjusting tubes MT1 to Nth adjusting tubes MTN, and the grids of the first adjusting tubes MT0, the second adjusting tubes MT1 to the Nth adjusting tubes MTN are connected with each other to receive control voltage. Since the third MOS transistor M3 is an N-channel MOS transistor, the regulating transistor is also an N-channel MOS transistor. In other embodiments, if the third MOS transistor M3 is a P-channel MOS transistor, the regulating transistor is also a P-channel MOS transistor.
In this embodiment, the width-to-length ratio of each adjusting tube can be set in a binary increasing manner, for example, 1.
In other embodiments, the controllable switches in the regulating unit 21 may be dispensed with. At this time, the source electrode of the regulating tube is connected with the source electrode of the third MOS tube M3, the drain electrode of the regulating tube is connected with the drain electrode of the third MOS tube M3, and the gate electrode of the regulating tube is a control end, so that the number of the regulating tubes connected with the third MOS tube M3 is regulated by providing control voltage to the gate electrodes of the regulating tubes of different numbers.
As shown in fig. 3, this embodiment further discloses a reference voltage circuit, which includes the current source circuit, the reference voltage circuit further includes a replica unit and a resistance unit, the replica unit is connected to the current mirror unit 10 to replicate
Figure 754159DEST_PATH_IMAGE034
A characteristic current, a replica unit connected to the resistance unit on the basis of ^>
Figure 575485DEST_PATH_IMAGE034
The characteristic current obtains a low temperature coefficient of reference voltage VREF at the resistance unit.
In addition, since the current source circuit has a degeneracy point, a start-up circuit needs to be added to ensure that the circuit operates normally.
In this embodiment, the replica unit includes a ninth MOS transistor M9, and the resistance unit includes an eighth MOS transistor M8. In this embodiment, the ninth MOS transistor M9 is a P-channel MOS transistor, and the eighth MOS transistor M8 is an N-channel MOS transistor. The source electrode of the ninth MOS tube M9 is connected with the power supply voltage, and the grid electrode of the ninth MOS tube M9 is connected with the grid electrodes of the fifth MOS tube M5, the sixth MOS tube M6 and the seventh MOS tube M7 to copy
Figure 252454DEST_PATH_IMAGE034
The characteristic current flows to the eighth MOS transistor M8, the drain electrode of the ninth MOS transistor M9 is connected with the drain electrode of the eighth MOS transistor M8, the grid electrode and the drain electrode of the eighth MOS transistor M8 are in short circuit, and the source electrode of the eighth MOS transistor M8 is connected with the ground voltage.
Based on
Figure 424809DEST_PATH_IMAGE034
The characteristic current and the selection of the eighth MOS transistor M8 with a reasonable size can obtain a reference voltage VREF with a low temperature coefficient on a resistance unit formed by the eighth MOS transistor M8 and output the reference voltage VREF from the drain of the eighth MOS transistor M8, the theoretical value of the reference voltage VREF is a value when the threshold voltage of the eighth MOS transistor M8 is extended to absolute zero, the sizes of the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5, the sixth MOS transistor M6, the seventh MOS transistor M7, the eighth MOS transistor M8, and the ninth MOS transistor M9 are set to values given in table 1 by using a typical 65nm CMOS process, a curve of the reference voltage VREF changing with temperature as shown in fig. 4 can be obtained through simulation, as can be seen in fig. 4, the value of the reference voltage VREF is 449.6mV, the voltage temperature coefficient between forty-zero and forty-five twenty-centigrade is 26ppm, and the total current is 70 ppm.
TABLE 1
Figure 314268DEST_PATH_IMAGE035
The embodiment also discloses a chip comprising the current source and/or the reference voltage circuit.
Example 2
As shown in fig. 5, the current source circuit in this embodiment is different from embodiment 1 in that the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4 are P-channel MOS transistors, and the fifth MOS transistor M5, the sixth MOS transistor M6, and the seventh MOS transistor M7 are N-channel MOS transistors.
Specifically, the source electrode of the first MOS transistor M1 and the second MOS transistor M2 are connected and connected to the power supply voltage, the drain electrode of the first MOS transistor M1 is connected to the gate electrode of the second MOS transistor M2, the source electrode of the third MOS transistor M3 and the source electrode of the fourth MOS transistor M4, the gate electrode of the first MOS transistor M1 is connected to the drain electrode of the third MOS transistor M3, the gate electrode of the third MOS transistor M3 is connected to the gate electrode of the fourth MOS transistor M4, and the gate electrode of the fourth MOS transistor M4 is connected to the drain electrode.
The grid of fifth MOS pipe M5, sixth MOS pipe M6 and seventh MOS pipe M7 links to each other, fifth MOS pipe M5, the source electrode of sixth MOS pipe M6 and seventh MOS pipe M7 links to each other and links to each other with the ground voltage, the drain electrode of seventh MOS pipe M7 and grid link to each other, the drain electrode of fifth MOS pipe M5 links to each other with the drain electrode of third MOS pipe M3, the drain electrode of sixth MOS pipe M6 and the drain electrode of fourth MOS pipe M4 link to each other, the drain electrode of seventh MOS pipe M7 and the drain electrode of second MOS pipe M2 link to each other.
The difference between the reference voltage circuit in this embodiment and embodiment 1 is that the ninth MOS transistor M9 corresponds to an N-channel MOS transistor, and the eighth MOS transistor M8 corresponds to a P-channel MOS transistor.
Specifically, the source of the ninth MOS transistor M9 is connected to the ground voltage, and the gate of the ninth MOS transistor M9 is connected to the gates of the fifth MOS transistor M5, the sixth MOS transistor M6 and the seventh MOS transistor to duplicate the signals
Figure 255679DEST_PATH_IMAGE034
The characteristic current, the drain electrode of the ninth MOS tube M9 is connected with the grid electrode and the drain electrode of the eighth MOS tube M8, the source electrode of the eighth MOS tube M8 is connected with the power voltage and based on ^ or ^>
Figure 837970DEST_PATH_IMAGE034
The characteristic current obtains a reference voltage VREF of a low temperature coefficient on the resistance unit formed by the eighth MOS transistor M8 and is output from the drain of the eighth MOS transistor M8.
The embodiment also discloses a chip comprising the current source and/or the reference voltage circuit.
The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the invention and various alternatives and modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.

Claims (10)

1. A current source circuit, comprising: the current mirror unit comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube and a current mirror unit;
the source electrode of the first MOS tube is connected with the source electrode of the second MOS tube and is connected with ground voltage or power voltage, the drain electrode of the first MOS tube is connected with the grid electrode of the second MOS tube, the source electrode of the third MOS tube and the source electrode of the fourth MOS tube, the grid electrode of the first MOS tube is connected with the drain electrode of the third MOS tube, the grid electrode of the fourth MOS tube is connected with the drain electrode of the fourth MOS tube, the current mirror unit is connected with the drain electrode of the second MOS tube, the drain electrode of the fourth MOS tube and the drain electrode of the third MOS tube, the current mirror unit is used for at least enabling the drain current of the first MOS tube to be proportional to the drain current of the second MOS tube and enabling the drain current of the third MOS tube to be proportional to the drain current of the fourth MOS tube, at least two MOS tubes of the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube work in different working areas, and at least one MOS tube of the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube is provided with the working area having the working area
Figure 940816DEST_PATH_IMAGE001
The current of the characteristic is such that,
Figure 195080DEST_PATH_IMAGE002
it is meant the square of the temperature,
Figure 104392DEST_PATH_IMAGE003
refers to the mobility of semiconductor carriers as a function of temperature.
2. The current source circuit according to claim 1, wherein the current mirror unit comprises a fifth MOS transistor, a sixth MOS transistor and a seventh MOS transistor, gates of the fifth MOS transistor, the sixth MOS transistor and the seventh MOS transistor are connected, sources of the fifth MOS transistor, the sixth MOS transistor and the seventh MOS transistor are connected and connected to a ground voltage or a power supply voltage, a drain of the seventh MOS transistor is connected to the gate, a drain of the fifth MOS transistor is connected to a drain of the third MOS transistor, a drain of the sixth MOS transistor is connected to a drain of the fourth MOS transistor, and a drain of the seventh MOS transistor is connected to a drain of the second MOS transistor.
3. The current source circuit of claim 1, wherein a length of the conduction channel of the first MOS transistor is the same as a length of the conduction channel of the second MOS transistor, and/or a length of the conduction channel of the third MOS transistor is the same as a length of the conduction channel of the fourth MOS transistor.
4. The current source circuit of claim 1, wherein the first and second MOS transistors operate in a sub-threshold region, the third MOS transistor operates in a linear region, and the fourth MOS transistor operates in a saturation region.
5. The current source circuit of claim 1, further comprising a trimming circuit comprising one or more adjusting units connected to the drain and source of the third MOS transistor.
6. The current source circuit according to claim 5, wherein the adjusting unit comprises a controllable switch and an adjusting transistor, a first end of the controllable switch is connected to a drain of the adjusting transistor, a second end of the controllable switch is connected to a drain of the third MOS transistor, a source of the adjusting transistor is connected to a source of the third MOS transistor, if a plurality of adjusting units are provided, gates of the adjusting transistors are connected, or
The adjusting unit comprises an adjusting tube, the source electrode of the adjusting tube is connected with the source electrode of the third MOS tube, the drain electrode of the adjusting tube is connected with the drain electrode of the third MOS tube, and the grid electrode of the adjusting tube is a control end.
7. A reference voltage circuit, comprising the current source circuit as claimed in any one of claims 1 to 6, and further comprising a replica unit and a resistance unit, wherein the replica unit is connected with the current mirror unit to replicate
Figure 723593DEST_PATH_IMAGE004
A current of a characteristic, the replica unit being connected to the resistance unit based on
Figure 584101DEST_PATH_IMAGE004
The characteristic current obtains a reference voltage with a low temperature coefficient on the resistance unit.
8. The reference voltage circuit of claim 7 wherein the replica cell comprises a ninth MOS transistor, a source of the ninth MOS transistor being connected to a supply voltage or a ground voltage, a gate of the ninth MOS transistor being connected to the current mirror cell to replicate
Figure 877942DEST_PATH_IMAGE004
And the drain electrode of the ninth MOS tube is connected with the resistance unit.
9. The reference voltage circuit according to claim 7, wherein the resistance unit includes an eighth MOS transistor, a gate and a drain of which are connected and connected to the replica unit, and a source of which is connected to a ground voltage or a power supply voltage.
10. A chip comprising a current supply circuit according to any one of claims 1 to 6 and/or a reference voltage circuit according to any one of claims 7 to 9.
CN202211365971.7A 2022-11-03 2022-11-03 Current source circuit, reference voltage circuit and chip Active CN115437448B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211365971.7A CN115437448B (en) 2022-11-03 2022-11-03 Current source circuit, reference voltage circuit and chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211365971.7A CN115437448B (en) 2022-11-03 2022-11-03 Current source circuit, reference voltage circuit and chip

Publications (2)

Publication Number Publication Date
CN115437448A CN115437448A (en) 2022-12-06
CN115437448B true CN115437448B (en) 2023-03-24

Family

ID=84252337

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211365971.7A Active CN115437448B (en) 2022-11-03 2022-11-03 Current source circuit, reference voltage circuit and chip

Country Status (1)

Country Link
CN (1) CN115437448B (en)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101917187B1 (en) * 2012-05-04 2018-11-09 에스케이하이닉스 주식회사 Reference voltage generator
CN103713684B (en) * 2013-12-18 2016-01-20 深圳先进技术研究院 voltage reference source circuit
CN105974989B (en) * 2016-06-15 2017-10-24 中山大学 A kind of low-power consumption whole CMOS reference source circuit based on subthreshold value
CN106527572B (en) * 2016-12-08 2018-01-09 电子科技大学 A kind of low-power consumption Low Drift Temperature CMOS subthreshold value reference circuits
CN208188713U (en) * 2018-05-30 2018-12-04 丹阳恒芯电子有限公司 A kind of low-voltage and low-power dissipation reference circuit
CN111813177A (en) * 2020-07-17 2020-10-23 广州大学 High-performance CMOS voltage reference source with negative feedback

Also Published As

Publication number Publication date
CN115437448A (en) 2022-12-06

Similar Documents

Publication Publication Date Title
US6737909B2 (en) Integrated circuit current reference
US7164260B2 (en) Bandgap reference circuit with a shared resistive network
EP0643347A1 (en) Self-biased cascode current mirror having high voltage swing and low power consumption
US20080265860A1 (en) Low voltage bandgap reference source
CN111226098B (en) Improved sub-threshold based semiconductor temperature sensor
JP2003283258A (en) Reference voltage source circuit operated on low voltage
JPH0465546B2 (en)
GB2538258A (en) Reference voltages
CN109491433B (en) Reference voltage source circuit structure suitable for image sensor
US4507572A (en) Voltage sensing circuit
CN115437448B (en) Current source circuit, reference voltage circuit and chip
CN114415776A (en) Band-gap reference voltage source circuit and electronic device
CN111752328A (en) Bandgap reference voltage generating circuit
JP3557739B2 (en) Reference voltage generation circuit
JP2013054535A (en) Constant voltage generation circuit
JP2005044051A (en) Reference voltage generating circuit
CN110568902B (en) Reference voltage source circuit
CN113804319A (en) Temperature sensor and integrated circuit
CN109582077B (en) Low-power-consumption power supply start-reset circuit and reference signal circuit
CN113434005A (en) Controllable resistance circuit
Kushima et al. Design of a floating node voltage-controlled linear variable resistor circuit
CN109062305B (en) Reference voltage source circuit
Hirose et al. Ultralow-power temperature-insensitive current reference circuit
CN110855294A (en) Circuit module and digital-to-analog converter
JP2637791B2 (en) Blog programmable reference voltage generator

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant