RU2543065C1 - Phase-based direction-finder - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: result is achieved owing to a certain design of the phase-based direction-finder and use of an adjustment and verification mode with a control generator, propagation of a signal through a directional coupler and antennae to all receiving channels and storing phase correction codes in a frequency range in different operating conditions.

EFFECT: high accuracy of direction-finding in a frequency range in different operating conditions, greater depth of integrated control and high noise-immunity.

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Description

The invention relates to radio engineering and can be used in monitoring systems for the radio engineering situation as part of the complex or as an autonomous device for detecting signals and measuring the direction to the radiation source of this signal.

It is known to construct a phase-measuring device in which when connecting to the inputs of the phase channel of two antennas spaced apart by the size of the base d and to the input of the frequency selection channel of the third antenna, a phase direction finder is formed, capable of measuring the angular position of a plane electromagnetic wave radiation object (V.N. Smirnov, A. A. Tkach. A comparative analysis of the options for constructing a receiving device with frequency conversion. Radio Engineering Issues, General Technical Series, issue 1, M., 2002, pp. 39-50, Fig. 2). It implements a phase direction finding method and a superheterodyne receiver with two frequency transforms.

Such a direction finder has increased noise immunity in the frequency range, but does not have high direction finding accuracy in various operating conditions (climatic influences, etc.) and does not have sufficient noise immunity in the dynamic range.

The aim of the invention is to improve the accuracy of direction finding in the frequency range in various operating conditions, increase the depth of the built-in control of the device and increase the noise immunity in the dynamic range of input signals.

This goal is achieved by the fact that in a phase direction finder containing three high-frequency mixers (UHF), three intermediate-frequency amplifiers (PUPCH), three first-pass bandpass filters (PFPC1), a high-frequency amplifier (UHF), a high-pass filter (PFFF) ), two mixers of intermediate frequency (SMPC), two band-pass filters of the second intermediate frequency (PPFCH2), and the first series microwaves, PUPCH, PPFPCh1, SMPC, PPFPCh2 are connected in series to form the first phase receiving channel, the last carefully connected second UHF, PUPCH, PPFPCh1, SMPCH, PPFPCh2 form the second phase receiving channel, serially connected UHF, PFPCH, third SMHF, PPCF, PFPCH1 form the reference receiving channel, the (N + 1) th antenna, N-2 phase receiving channels in the form of series-connected UHF, PUPCH, PPPFCH1, SMPCH, PFPCH2, two tunable local oscillators (PG), a local oscillator frequency control unit (BCCH), a control generator (KG), a directional coupler (BUT), two intermediate frequency amplifiers with a logarithmic video output ( UPCHL), analog amount Ohr, bias voltage generator (FPSm), three threshold devices (PU), an analog comparator, (N + 2) -th PFPCh1, (N + 1) -th PFPCh2, two amplitude detectors (HELL), frequency discriminator (BH), two blocks of analog-to-digital converters (ADC), an intermediate frequency computer (IF), a four-input coincidence circuit, an electronic programmable read-only memory (EEPROM), an ADC sampler, a phase difference calculator, a correction unit and a bearing calculator, each of N antennas is connected respectively to the input of the microwave of each of the N receiving channels, the (N + 1) -th antenna is connected via NO to the input of the UHF reference channel, the output of the first PG is connected to the second input of the UHF of each of the N receiving channels, the output of the PPPCH2 of each of the N receiving channels is connected respectively to the N inputs of the first of the ADC unit, the first output of the BCCH is connected to the input of the first SG, the second output of the BCCH through the CH is connected to the second input of the NO, the third output of the BCCH through the second PG is connected to the second input of the microwave UHF of the reference channel, the fourth output of the BCCH is connected to the first input of the EEPROM and to (N + 1) th input of the bearing calculator c, the output of the PPPFCH2 of the Nth receiving phase channel is additionally connected through the first UPCF, (N + 1) -th PPFCH2, the first HELL and the first PU with the first input of the match circuit, the output of the Federal Tax Service through an analog adder, the analog comparator is connected to the second input of the match circuit , the second output of the first controller is connected to the second input of the analog adder, the output of the reference channel PFPC1 through the second controller is connected to the second input of the analog comparator and the input of the second controller, the output of which is connected to the third input of the matching circuit, the second output of the second controller is connected is not connected to the input of the (N + 2) th PPFPC1 and the input of the BH, the output of the (N + 2) th PPFPC1 is connected to the second inputs of the SMPC of each of the N receiving channels and to the input of the second BP, the output of which through the third PU is connected to the fourth input of the four-input coincidence schemes, two BH outputs are connected respectively to two inputs of the second ADC block, two outputs of the second ADC block are connected respectively to the inverter, the output of which is connected to the second input of the EEPROM and the (N + 2) -th input of the bearing calculator, (N + 1) the output of the phase difference calculator is connected to the third input of the EEPROM, the output of the circuit matches is connected to the third input of the second ADC unit and to the (N + 1) -th input of the ADC sampler, N outputs of the first ADC unit, respectively, through the N inputs and N outputs of the ADC sampler, N inputs and N outputs of the phase difference calculator, N inputs and The N outputs of the correction unit are connected respectively to the N inputs of the bearing calculator, the two outputs of which are the outputs of the device.

Figure 1 shows the structural diagram of the direction finder, figure 2 is a diagram explaining its operation.

The phase direction finder contains N + 1 antennas 1 ₁ , 1 ₂ , ..., 1 _N , 10 located in one plane, N of which (1 ₁ , ..., 1 _N ) form a phase array, and antenna 10 is located in the center of the entire antenna system , UHF 2 ₁ , 2 ₂ , ..., 2 _N , 15, PCB 3 ₁ , 3 ₂ , ..., 3 _N , 16, N + 2 PPPCH1 4 ₁ , 4 ₂ , ..., 4 _N , 18, 27, N 5 ₁ , 5 ₂ , ..., 5 _N , N + 1 ППФПЧ2 6 ₁ , 6 ₂ , ..., 6 _N , two tunable local oscillators 7, 14, БУЧГ 8, КГ 9, НО 11, UHF 12, PPFVCh 13, two UPCHL 20, 23, Federal Tax Service, 17, analog adder 21, analog comparator 22, three control units 25, 31, 37, two AD 30, 32, BH 28, two ADC units 19, 33, inverter 38, four-input match circuit 36, EEPROM 35 , formiro ADC sampler 24, phase difference calculator 29, correction block 34, bearing calculator 39.

The output of each of the antennas 1 ₁ , 1 ₂ , ..., 1 _{N is} connected respectively to the first inputs of each UHF 2 ₁ , 2 ₂ , ..., 2 _N. Serially connected, UHF 2 ₁ , PUPCH 3 ₁ , PPFCH ₁ 4 ₁ , SmPCH 5 ₁ , PFPC 2 6 ₁ form the first receiving phase channel. Serially connected, UHF 2 ₂ , PUPCH 3 ₂ , PPFCH 1 4 ₂ , SmPCH 5 ₂ , PFPC ₂ 6 ₂ form the second receiving phase channel. Serially connected UHF 2 _N , PPCF 3 _N , PFPC 1 4 _N , SFC 5 _N , PFPC 2 6 _N form the N-th receiving phase channel. The output of the antenna 10 through NO 11 is connected to the input of the UHF 12. Serially connected UHF 12, PPFVCH 13, UHF 15, PUPCH 16, PPFPCh 18 form a reference receiving channel. The output of the first PG 7 is connected to the second inputs of each of the UHF 2 ₁ , 2 ₂ , ..., 2 _N included in the N phase receiving channels, the output of the second PG 14 is connected to the second input of the UHF 15 of the reference channel. The first, second, third and fourth outputs of the BUCHG 8 are connected respectively to the inputs of the first PG 7, through the KG 9 with the second input of the HO 11, with the input of the PG 14, with the first input of the EEPROM 35 and with the (N + 1) -th input of the bearing calculator 39 The output of each of N PPPCH2 6 ₁ , 6 ₂ , ..., 6 _N, respectively, through the N inputs and N outputs of the first ADC block 19, N inputs and N outputs of the ADC sampler 24, N inputs and N outputs of the phase difference calculator 29, N inputs and N outputs of the correction unit 34 are connected to N inputs of the bearing calculator 39, the outputs of which are the outputs of the direction finder. The output of PPPFCH2 6 _{N of the} Nth phase channel is additionally connected to the input of the first UPCF 20, the first output of which through the (N + 1) -th PPFCH2 26, the first HELL 30, the first PU 31 is connected to the first input of the four-input matching circuit 36. The output of the Federal Tax Service 17 through the analog adder 21, the analog comparator 22 is connected to the second input of the match circuit 36. The first output of the second UCHL 23 is connected to the second input of the comparator 22 and through the second PU 25 is connected to the third input of the match circuit 36. The second output of the second UCH 23 is connected to the input (N +2) -th PPFPCH1 27 and with the input of BH 28. Output (N + 2) -th PPFP Ch1 27 is connected to the second inputs of the SMPCH 5 ₁ , 5 ₂ , ..., 5 _N and through the second HELL 32 and the third PU 37 with the fourth input of the four-input matching circuit 36. Two outputs of BH 28 are connected respectively through the second block of the ADC 33 with two inputs of the inverter 38, the output of which is connected to the second input of the EEPROM 35 and to the (N + 2) -th input of the bearing calculator 39. The output of the coincidence circuit 36 is connected to the (N + 1) -m input of the ADC sampler 24 and to the third input of the second ADC block 33 .

The direction finder’s operation is based on the phase direction finding method, when a plane-incident radio wave forms coherent signals at the antenna outputs, the phase difference ∆φ between them depends on the direction α to the direction-finding radiation source:

$$\Delta \varphi =\left(2\pi d/\lambda \right)Sin\alpha \left(\mathrm{one}\right)$$

where d is the distance between the antennas (base);

λ is the wavelength of electromagnetic radiation.

The antenna of the reference channel is installed in the center, the rest - along the perimeter with an integer ratio of the projections of the bases on the azimuthal and elevation axis of coordinates.

A superheterodyne receiver with two frequency transforms with two local oscillators spaced in frequency by the value of the second intermediate frequency with a ban on reception at the mirror frequency is used as a receiving device in the direction finder.

When adjusting the direction finder, the values of the correcting codes for each base are stored according to the signal of the radiation source installed in the equal-phase direction and according to the signal from the control generator. In normal mode, phase errors are corrected.

Phase direction finder works as follows. An electromagnetic wave is converted by input antennas 1 ₁ -1 _N into harmonic oscillations of the same carrier frequency with phase differences in partial bases defined by expression (1). At the output of the antenna 10, an arbitrary phase signal is generated.

In each of the N phase channels, the signal is converted to UHF 2 _i to the first IF, amplified by IFAP 3 _i , filtered by IFPC 4 _i , converted into SMPC 5 _i by the second IF, and filtered PPF2 6 _i with a narrow passband to the second IF.

From the output of the antenna 10, the signal through HO11 is fed to the input of the reference channel, where UHF 12 is amplified, PPFHF 13 is filtered at high frequency, UHF 15 is converted to the first IF of the reference channel, which differs from the first IF of the phase channel by the value of the second IF. Then the signal in the reference channel is amplified by the PCB 16, filtered by the PFHF 18, amplified by the PCF 23 and additionally filtered by the PFPC 1 27. From the output of the PFPC 1 27, the signal is fed to the inputs of the PCF 2 6 _{i of} each of the N phase channels.

. Величина задержки τ выбирается такой, чтобы однозначно измерить величину ПЧ во всей мгновенной полосе пропускания приемного устройства. С выхода вычислителя ПЧ 38 двоичный код, пропорциональный величине ПЧ, поступает на второй вход ЭППЗУ 35 и на (N+2)-й вход вычислителя пеленгов 39. Таким образом устанавливается соответствие между частотой сигнала, частотой ПГ 14 и измеренной величиной ПЧ, что необходимо для однозначного соответствия каждому сигналу кода коррекции в ЭППЗУ 35 и в блоке коррекции 34. С выхода ППФПЧ1 27 ПЧ сигнал поступает также на вход АД 32 и после детектирования - на вход ПУ 37, а затем на четвертый вход схемы совпадений 36. Таким образом, наличие сигнала на выходе третьего ПУ 37 формирует мгновенную полосу пропускания приемника во всем динамическом диапазоне входных сигналов. С первого выхода второго УПЧЛ 23 видеосигнал поступает на второй вход аналогового компаратора 22 и на вход второго ПУ 25, а с их выходов соответственно на второй и третий входы схемы совпадений 36. С выхода ППФПЧ2 6_N N-го фазового канала ПЧ сигнал поступает дополнительно на вход УПЧЛ 20. С ПЧ выхода УПЧЛ 20 сигнал фильтруется ППФПЧ2 26, затем детектируется АД 30 и сравнивается с порогом в первом ПУ 31. Таким образом формируется наличие сигнала в полосе пропускания после второго преобразования по частоте. С выхода первого ПУ 31 логический сигнал поступает на первый вход схемы совпадений 36. Видеосигнал с второго выхода УПЧЛ 20 поступает на второй вход аналогового сумматора 21, на первый вход которого приходит напряжение с выхода ФНСм 17. С выхода сумматора 21 сумма сигналов поступает на первый вход компаратора 22, а с его выхода - на второй вход схемы совпадений 36. Компаратор 22 разрешает работу приемного устройства на основной частоте приема. На зеркальной частоте напряжение на выходе компаратора 22 будет соответствовать логическому нулю (см. фиг.2) и обнаружения сигнала не произойдет.In BUCHG 8, the necessary frequency of the first GHG 7 and the second GHG 14 is set, shifted relative to each other by the value of the second IF. From the second output, the BUCHG 8 controls the modes and frequency of the KG 9. From its third output, a digital code is received corresponding to the frequency code of the second PG 14 to the (N + 1) -th input of the bearing calculator 39 and to the first input of the EEPROM 35. From the second output of the second 23 The IF signal is also fed to the BH 28 input. In it, the phase difference between the direct and delayed signals is calculated in quadratures and voltages proportional to Sinϖτ and Cosϖτ are formed. In the second block of the ADC 33, these voltages are converted into a digital binary code, and in the inverter 38, ϖτ is calculated by the formula $$\varpi \tau =arctg\frac{Sin\varpi \tau }{Cos\varpi \tau }$$

. The delay value τ is chosen so as to unambiguously measure the IF value in the entire instantaneous passband of the receiving device. From the output of the inverter 38, a binary code proportional to the inverter is supplied to the second input of the EEPROM 35 and to the (N + 2) -th input of the bearing calculator 39. Thus, a correspondence is established between the signal frequency, the frequency of the GD 14 and the measured value of the inverter, which is necessary for unambiguous correspondence to each signal of the correction code in EEPROM 35 and in the correction unit 34. From the output of the PPPFCH1 27, the IF signal also goes to the input of the AD 32 and, after detection, to the input of the PU 37, and then to the fourth input of the coincidence circuit 36. Thus, the presence of third output signal UE 37 generates an instantaneous bandwidth of the receiver during the entire dynamic range of input signals. From the first output of the second UCHL 23, the video signal is fed to the second input of the analog comparator 22 and to the input of the second PU 25, and from their outputs, respectively, to the second and third inputs of the matching circuit 36. From the output of the PFPC2 6 _N N-th phase channel, the IF signal is additionally fed to input CHF 20. From the IF output of CHF 20, the signal is filtered by PPFCH2 26, then the AD 30 is detected and compared with the threshold in the first control unit 31. Thus, the presence of a signal in the passband after the second frequency conversion is formed. From the output of the first PU 31, a logical signal is supplied to the first input of the matching circuit 36. The video signal from the second output of the PCA 20 is fed to the second input of the analog adder 21, the first input of which receives the voltage from the output of the Federal Tax Service 17. From the output of the adder 21, the sum of the signals goes to the first input comparator 22, and from its output to the second input of the coincidence circuit 36. Comparator 22 allows the receiving device to operate at the main reception frequency. At the mirror frequency, the voltage at the output of the comparator 22 will correspond to a logical zero (see figure 2) and the signal will not be detected.

IF signals from the output of each of N PPPFCH2 6i are fed to the N inputs of the first ADC block 19. In the block, the analog IF signals are continuously converted to binary codes with a high clock frequency, which are received, respectively, at the inputs of the ADC sampler 24. By the detection pulse, formed at the output of the four-input coincidence circuit 36, when the outputs of the first, second, third control units 25, 31, 37 and the analog comparator 22 go into the state of the logical unit (when a signal is detected) in the sampler 24 according to the principle of a sliding time window is stored for a processing time a certain number of binary numbers. In the phase difference calculator 29, the phase differences are calculated by partial bases on the principle of the complex fast Fourier transform (FFT) or by quadratures. Further, the correction unit 34 for each of the partial base is carried out a correction of phase error codes from the memory EEPROM 35 in accordance with a set frequency of the second local oscillator 14 and the measured calculator inverter 38 an intermediate frequency (f _c = f _r2 + f _IF, where f _c - signal frequency calculated or set during tuning or in KG 9, signal frequency, f _Г2 - frequency of the second local oscillator, f _IF - measured IF). If the measured or set frequencies do not match, the interpolation method is used or the correction code value is taken, which is closest in frequency.

When adjusting the direction finder according to the radiation source installed in the equiphase direction, through the (N + 1) -th output of the phase difference calculator 29 and the third input of the EEPROM 35 is filled with the EEPROM 35 over the entire frequency range. Then, the KG 9 is turned on and the EEPROM 35 is filled sequentially in the frequency range in the KG mode. In this case, the signal from the output of the KG 9 through the HO 11 and the antenna 10 is distributed in the form of an electromagnetic wave to the phase antennas 1 ₁ ... 1 _N phase channels and, further, to the receiving phase channels with the formation of correction codes in the KG mode.

The detection of signals and the formation of samples of bearings in the operating mode is as follows. Alternately, the installation of GHG 7 and the associated second GHG 14 in frequency occurs. In the event that the frequency of the signal after frequency conversion falls into the passband of the receiver, and if the signal power is sufficient to trigger the first, second, third controllers 31, 25, 37 and if the frequency corresponds to the main (non-mirror) reception frequency, then the four-input match circuit 36 will operate and signal detection will occur. If, at the set frequency values of the first and second PG 7 and PG 14, the signal frequency is close to the mirror frequency of the reference channel (see Fig. 2), then detection will not occur, since at the selected bandwidths of the phase and reference channels the second IF, frequency response of these channels do not intersect. In the dynamic range of input signals, when due to the finite selectivity of the bandpass filters, triggering of the controllers 25, 31, and 37 may occur, the analog comparator 22 will not work, since the amplitude of the video signal from output 2 of the AMPL 20 will be significantly less than the amplitude of the output 1 of the AML 23. This ensures increased noise immunity of the direction finder in the dynamic range of input signals.

The formation of bearings in the direction finder is as follows. Periodically, KG 9 is turned on, the operability of the direction finder (built-in control) is monitored, and the current correction codes are recorded in the EEPROM 35. When a signal is detected in the ADC 24 sampler by the principle of a sliding time window, a certain number of time samples (all samples) are recorded on all N channels of the ADC 19 ), which are calculated in the calculator 29, the value of the phase difference for partial bases. In accordance with the calculated carrier frequency of the signal from the memory of the EEPROM 35, a correction code is generated for each base, generated when the direction finder is set up according to the radiation source in the different-phase direction, and the phase difference samples are corrected. Then, from the EEPROM 35, the values of the correction codes closest in frequency and time for each base are selected as the difference of the current values of the phase differences and recorded in the CG mode when setting the direction finder. Thus, the direction finder provides improved direction finding accuracy in the conditions of its operation and its full check in the built-in control mode.

Claims (1)

A phase direction finder containing three high-frequency mixers (UHF), three intermediate-frequency amplifiers (PUPCH), three first-pass bandpass filters (PFPCH1), a high-frequency amplifier (UHF), a high-pass filter (PFVCH), two intermediate-frequency mixers ( SMPCH), two bandpass filters of the second intermediate frequency (PPFCH2), with the first coupled SMHF, PUPCH, PPPCH1, SmPCH, PPPCH2 serially connected to form the first phase receiving channel, the second SMHF, PPCh connected in series, PFCH1, SMPCH, PFPCH2 form the second phase receiving channel, connected in series by UHF, PFVCH, third SMHF, PUPCH, PFPCH1 form the reference receiving channel, characterized in that N + 1 antennas, N-2 phase receiving channels are additionally introduced in the form of series-connected UHF , PUPCH, PPPFCH1, SMPC, PFPCH2, two tunable local oscillators (PG), a local oscillator frequency control unit (BCCH), a control oscillator (KG), a directional coupler (BUT), two intermediate frequency amplifiers with a logarithmic video output (UPCHL), an analog adder, of forms bias voltage calibrator (FSM), three threshold devices (PU), an analog comparator, (N + 2) -th PFPCh1, (N + 1) -th PFPCh2, two amplitude detectors (HELL), frequency discriminator (BH), two blocks analog-to-digital converters (ADCs), an intermediate frequency computer (IF), a four-input match circuit, an electronic programmable read-only memory (EEPROM), an ADC sampler, a phase difference calculator, a correction unit and a bearing calculator, with each of the N antennas being connected respectively, with the input of each microwave of the N receiving channels, the (N + 1) -th antenna is connected via NO to the input of the UHF reference channel, the output of the first PG is connected to the second input of the UHF of each of the N receiving channels, the output of the PFPC2 of each of the N receiving channels is connected respectively to the N inputs of the first block ADC, the first output of the BUCHG is connected to the input of the first SG, the second output of the BUCH through the CHG is connected to the second input of the NO, the third output of the BUCH through the second SG is connected to the second input of the microwave UHF of the reference channel, the fourth output of the BUCHG is connected to the first input of the EEPROM and to (N + 1 ) -th input of the bearing calculator, output PFCH2 of the N-th receiving channel is additionally connected through the first UPCL, (N + 1) -th PFPCh2, the first HELL and the first PU with the first input of the match circuit, the output of the Federal Tax Service through an analog adder, the analog comparator is connected to the second input of the match circuit, the second output of the first The UCHF is connected to the second input of the analog adder, the output of the reference channel PPPFCH1 through the second UCHF is connected to the second input of the analog comparator and the input of the second PU, the output of which is connected to the third input of the matching circuit, the second output of the second UPCL is connected to the input of the (N + 2) -th PP IF1 and BH input, the output of the (N + 2) -th PPFCH1 is connected to the second inputs of the SMPC of each of the N phase receiving channels and to the input of the second HELL, the output of which through the third PU is connected to the fourth input of the four-input matching circuit, two BH outputs are connected respectively to two inputs of the second ADC block, two outputs of the second ADC block are connected respectively to the inverter, the output of which is connected to the second input of the EEPROM and the (N + 2) -th input of the bearing calculator, the (N + 1) -th output of the phase difference calculator is connected to the third EEPROM input, output of the coincidence circuit with it is single with the third input of the second ADC block and with the (N + 1) -th input of the ADC sampler, N outputs of the first ADC block through N inputs and N outputs of the ADC sampler, through N inputs and N outputs of the phase difference calculator, through N inputs and N outputs of the correction unit are connected respectively to N inputs of the bearing calculator, the two outputs of which are the outputs of the device.

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