RU2525111C1 - Device to form transfer in summator - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: device comprises logical transistors of n-type, precharge transistors of p-type, inverting elements, each of which comprises a clock transistor of p-type, a logical transistor of p-type and a clock transistor of n-type, a power supply bus, an earth bus, logical outputs, logical inputs, straight and inverse outputs.

EFFECT: reliability improvement.

1 dwg

Description

The invention relates to the field of computer technology and can be used in CMDP integrated circuits for the implementation of arithmetic devices.

A device for the formation of transfer in the composition of the adder (RF Patent No. 2239227, G06F 7/50 from 10/27/2004). This device contains two p-type transistors and 12 n-type logic transistors in the discharge. The disadvantages of the device are the limited performance if it is necessary to recharge the output capacitance through a circuit of 4 series-connected transistors and limited functionality, since adjacent (even) discharges of the adder must be performed on complementary p-type transistors, which also reduces the speed of the device.

The closest technical solution to the proposed one is a transfer forming device based on differential circuitry of the domino type (US Pat. No. 7,428,568, FIG. 1, G06F 7/50, NKI 708/702 of September 23, 2008). The device contains two p-type precharge transistors, two p-type feedback transistors, an n-type clock transistor and ten n-type logic transistors. The disadvantage of the device is the lack of reliability of operation, since in the initial state and when the variables are not equal until the arrival of the paraphase transfer signals, the logic 1 signals are stored on both differential outputs of the device, which leads to the uncertainty of the device functioning for successively connected stages (adder discharges).

The technical result of the invention is to increase reliability.

The technical result is achieved by the fact that the transfer forming device in the adder contains ten n-type logic transistors, first and second p-type transistors, which are connected between the power bus and, accordingly, the first and second logic conclusions, are paired in series and connected between the first logic output and with a common conclusion, the first and second, third and fourth, fifth and fourth logical transistors of n-type, as well as connected in pairs in series and connected between the second logical output m and the common output of the sixth and seventh, eighth and ninth, tenth and ninth logical transistors of n-type, the gates of logical transistors of n-type are connected to the corresponding logical inputs of the device, and the gates of the first and third, second and fifth, sixth and eighth are combined in pairs, the seventh and tenth logical transistors of n-type, and also contains the first and second inverting elements, each of which contains a clock and logical transistors of p-type and a clock transistor of n-type, which are connected in series between the bus th power supply and ground bus, the first and second logic leads are connected to the gates of the p-type logic transistors of the first and second inverting elements, respectively, the connection point of the p-type logic transistor and the n-type clock transistor of the first inverting element is connected to the direct output of the device and to the gate first p-type precharge transistor. and the connection point of the p-type logic transistor and the n-type clock transistor of the second inverting element is connected to the inverse output of the device and to the gate of the second p-type pre-charge transistor, the gates of the n-type clock transistors and the gates of the r-type clock transistors of the first and second inverting elements , as well as the common output connected to the clock bus.

Significant distinguishing features in this set of features is the presence of inverting elements containing p-type clock and logic transistors and an n-type clock transistor in series with new connections and known features of the device, connected in series between the power bus and the ground bus.

The presence in the proposed device of the above significant distinguishing features provides a solution to the technical problem - improving reliability.

In the prototype device, the well-known logical transfer functions during clocking and with variable inequality until the arrival of paraphase transfer signals are realized when there are high level signals on the differential outputs of the device, which leads to the uncertainty of the device functioning for sequentially connected stages (adder discharges). In the claimed device, the same logical functions are realized when there are zero signals at the transfer outputs, which, when directly connected to devices of this type, eliminates the uncertainty of the logical state and temporary “bounce” of the signals. P-type precharge transistors, controlled by gates from paraphase outputs, provide not only the presence of zero signals at the transfer outputs in the initial state, but also due to feedback, the safety of the zero signal at one of the transfer outputs during switching to the para-phase state is reliable.

The drawing shows a schematic diagram of the inventive device for forming a transfer in the adder.

The device contains ten logical transistors 1-10 n-type, the first 11 and second 12 pre-charge transistors of p-type, the first 13 and second 14 inverting elements, each of which contains a clock 15 and a logical 16 transistors of p-type and a clock transistor 17 n- types that are connected in series between the power bus 18 and the ground bus 19.

The first 11 and second 12 p-type pre-charge transistors are connected between the power bus 18 and, respectively, the first 20 and second 21 logic outputs. In pairs are connected in series and connected between the first logical output 20 and the common output 22, the first 1 and second 2, the third 3 and fourth 4, the fifth 5 and fourth 4 logical transistors of n-type, and are also paired in series and connected between the second logical output 21 and general output 22 sixth 6 and seventh 7, eighth 8 and ninth 9, tenth 10 and ninth 9 are n-type logic transistors.

The first 20 and second 21 logic outputs are connected to the gates of the p-type logic transistor 16, respectively, of the first 13 and second 14 of the inverting element. The connection point of the p-type logical transistor 16 and the n-type clock transistor 17 of the first inverting element 13 is connected to the direct output of the device 23 and to the gate of the first p-type trans-charge transistor 11. The connection point of the p-type logic transistor 16 and the n-type clock transistor 17 of the second inverting element 14 is connected to the inverse output 24 of the device and to the gate of the second p-type trans-charge transistor 12. The gates of the clock transistors 17 are n-type, the gates of the clock transistors 15 are p-type of the first 13 and the second 14 inverting elements, as well as the common terminal 22 are connected to the clock bus 25. The gates of the logic transistors 1-10 of the n-type are connected to the logical inputs 26-31 devices, and the gates of the first 1 and third 3, second 2 and fifth 5, sixth 6 and eighth 8, seventh 7 and tenth 10 logic transistors of n-type are combined in pairs.

The device operates as follows. In the initial state, on the first half-cycle, with a single signal on the clock bus 25, the p-type 15 transistors are closed, and the n-type clock transistors 17 are open in the first 13 and second 14 inverting elements. The outputs 23 and 24 of the device are in the zero state, the pre-charge transistors 11 and 12 of the p-type are open and the node capacitances of the logic outputs 20 and 21 are charged to the voltage of the power bus.

, а на логический вход 31 - сигнал переменной $$\overline{C}$$

.The signal of variable A is sent to logic input 26, and the signal of variable B is sent to logic input 27, the signal of variable (transfer) C is sent to logical input 28, the signal of variable Ā is sent to logic input 29, and the signal of variable 30 is $$\overline{B}$$

, and to the logic input 31 - signal variable $$\overline{C}$$

.

.The working half-cycle begins with the supply of a zero signal to the clock bus 25, while the clock transistors 15 of the p-type inverting elements 13,14 open, and the clock transistors 17 of the n-type are closed. If the variables are equal, A = B = 1, the circuit of the first 1 and second 2 logical n-type transistors is conductive. When C = 1, an additional circuit is carried out consisting of logical transistors 3-4 and 4-5 n-type. The voltage at the node capacitance of the first logic output 20 drops, the p-type clock transistor 15 of the first inverting element 13 opens, the voltage at the device’s direct output 23 rises, and the first p-type transistor 11 closes. With the inequality of variables A and B and with the transfer of C = 1, the circuit of the transistor 4 and one of the 3 or 5 logical n-type transistors connected in series with it is conductive. At the same time, at the direct output 23 of the device, forming a logical 1 signal, which corresponds to a transfer result of 1. Circuits containing logic transistors 6-10 are turned off and a zero signal is stored at the inverse output 24 of the device, i.e. $$\overline{C}=0$$

.

The circuits of n-type logic transistors 6-10 function similarly with the corresponding inverse values of the variables A and B and with the transfer C = 0. In this case, a logical 1 signal is generated at the inverted output 24 of the device, and a logical 0 signal at the direct output 23 of the device.

Claims (1)

A transfer forming device in an adder containing ten n-type logic transistors, first and second p-type transistor transistors that are connected between the power bus and, respectively, the first and second logic terminals, are paired in series and connected between the first logical terminal and the common terminal first and the second, third and fourth, fifth and fourth logical transistors of n-type, are also connected in pairs in series and are connected between the second logical output and the common output of the sixth and seventh, eighth the ninth and ninth, tenth and ninth logical transistors of n-type, the gates of logical transistors of n-type are connected to the corresponding logical inputs of the device, and the gates of the first and third, second and fifth, sixth and eighth, seventh and tenth logical transistors of n-type are combined in pairs characterized in that the device comprises first and second inverting elements, each of which contains p-type clock and logic transistors and an n-type clock transistor, which are connected in series between the power bus and the bus th ground, the first and second logical conclusions are connected to the gates of the p-type logical transistors of the first and second inverting elements, respectively, the connection point of the p-type logical transistor and the n-type clock transistor of the first inverting element is connected to the direct output of the device and to the gate of the first pre-charge transistor p-type, and the connection point of the p-type logic transistor and the n-type clock transistor of the second inverting element is connected to the inverse output of the device and to the gate of the second charge p-type transistor, the gates of clock n-type transistors and the gates of transistors clock p-type first and second inverting element, and the total output connected to the clock bus.