RU2518997C1 - Ultra-high-speed parallel analogue-to-digital converter with differential input - Google Patents

Abstract

FIELD: radio engineering, communication.SUBSTANCE: disclosed is an ultra-high-speed parallel analogue-to-digital converter with a differential input, having N sections of identical architecture. Each of the sections includes a voltage comparator, the first input of which is connected to a first input voltage source through a first reference resistor, and the second input of the voltage comparator is connected to a second input anti-phase voltage source through a second reference resistor, wherein the first input of the voltage comparator is connected to a first reference current source and a first parasitic capacitor, the second input of the voltage comparator is connected to a second reference current source and a second parasitic capacitor. The first reference current source is connected in form of a first current mirror which is matched with a first power supply bus, and a first auxiliary reference current source connected to the input of the first current mirror, wherein the output of the first current mirror is the output of the first reference current source, and the second input anti-phase voltage source is connected to the input of the first current mirror through a first balancing capacitor.EFFECT: multifold expansion of the frequency range of processed analogue-to-digital converter signals by reducing the transmission error of input differential voltages from input voltage sources to voltage comparator inputs.3 cl, 7 dwg

Description

The present invention relates to the field of measuring and computing, radio engineering, communications and can be used in the structure of various devices for processing analog information, measuring instruments, telecommunication systems, etc.

In modern technology, widespread use are parallel analog-to-digital converters (ADCs), which provide the highest conversion speed of analog signals (u _in ) to digital signals [1-27]. With an increase in the frequency of the input voltage u _I in such microelectronic ADCs, significant conversion errors arise due to the influence of stray capacitors formed by capacitors on the substrate of active and passive components [28-29]. A further increase in the performance of parallel ADCs is one of the problems of modern information-measuring equipment, the solution of which will allow the practical implementation of new communication systems and telecommunications with higher quality indicators.

Closest to the technical nature of the claimed device is a parallel ADC of FIG. 1 described in US Pat. No. 7,394,420, fig. 3, fig. 4. An analysis of its limiting frequency range (f _in.max ), as well as attempts to increase f _in.max by optimizing the absolute values of the resistances of the reference resistors, are discussed in [28–29], including a co-author of this application [29].

The ADC prototype contains N sections identical in architecture (FIG. 1). Each section contains a voltage comparator 1, the first 2 input of which is connected to the first 3 source of input voltage through the first 4 reference resistor, and the second 5 input of the voltage comparator 1 is connected to the second 6 source of input antiphase voltage through the second 7 reference resistor, the first 2 input a voltage comparator 1 is connected to a first 8 reference current source and a first 9 spurious capacitor, a second 5 input of a voltage comparator 1 is connected to a second 10 reference current source and a second 11 spurious capacitor.

A significant drawback of the ADC prototype (FIG. 1), a circuit of one of the sections of which is shown in FIG. 2, consists in the fact that its limiting frequency range for converting input analog signals to digital (even when implementing SGB25H1, IHP, Germany [28, 29] technology at microwave transistors with f ^max = 200 GHz) is limited due to a decrease at high frequencies the transmission coefficient of the signal from the inputs of the ADC to the inputs of the voltage comparators.

The main objective of the invention is to expand several times the frequency range of the processed ADC signals by reducing the error of transmission of input differential voltages from sources of input voltages 3 and 6 to the inputs of voltage comparators 1.

The problem is achieved in that in a parallel analog-to-digital Converter with a differential input (figure 1), each of the N-sections of which (figure 2) contains a voltage comparator 1, the first 2 input of which is connected to the first 3 source of input voltage through the first 4 reference resistor, and the second 5 input of voltage comparator 1 is connected to the second 6 source of input antiphase voltage through the second 7 reference resistor, and the first 2 input of voltage comparator 1 is connected to the first 8 reference current source and the first 9 pair by a total capacitor, the second 5 input of the voltage comparator 1 is connected to the second 10 reference current source and the second 11 stray capacitor, new elements and connections are provided - the first 8 reference current source is made in the form of a first 12 current mirror, matched with the first 13 bus of the power source, and the first 14 auxiliary reference current source connected to the input of the first 12 current mirror, and the output of the first 12 current mirror is the output of the first 8 reference current source, and the second 6 input source is out of phase second power connected to the input of the first current mirror 12 through a first adjustment capacitor 15.

Figure 1 shows the circuit of the ADC prototype, which contains N-parallel connected sections with the same architecture (figure 2), but with different absolute values of the resistances of the reference resistors 4 (7) and currents I ₈ (I ₁₀ ) of the sources of the reference currents 8 ( 10).

In FIG. 2 is an equivalent circuit diagram of one of the ADC sections of FIG. 1, corresponding to the ADC prototype.

In FIG. 3 shows a diagram of one of the sections of the proposed ADC, corresponding to paragraphs. 1, 2 claims.

In FIG. Figure 4 shows the equivalent circuit of the claimed ADC in the Cadence environment on SiGe transistor models (npn 200-n; SG25H1, IHP process technology, Ik max = 4 mA. A high-performance 0.25 µm technology with npn-HBTs up to f _T / f _max = 180/220 GHz.), Which takes into account parasitic capacitance of real current mirrors, capacitance on the substrate of passive components and input capacitance of voltage comparators 1 based on real differential stages.

In FIG. 5 shows the logarithmic amplitude-frequency characteristic of the transmission coefficient from input voltage sources 3 and 6 to the differential input of comparator No. 2 (channels: 32, 48) of the ADC circuit of FIG. four.

In FIG. 6 shows the logarithmic amplitude-frequency characteristic of the transmission coefficient from sources of input voltages 3 and 6 to the differential input of comparator No. 2 (channels: 32, 48) of the ADC circuit of FIG. 4. Moreover, in this scheme:

- takes into account the capacitance on the substrate of the reference resistors 4 and 7;

- sequentially with each correction capacitor 15 and 18 C _to , additional resistors R = 50 Ohms are included;

- parasitic output capacitance of current mirrors 12 and 16 has a relatively small value With _n = 70 fF;

- the circuit uses real voltage comparators 1 (differential stages) with parasitic capacitances of their transistors.

In FIG. 7 shows the logarithmic amplitude-frequency characteristic of the transmission coefficient from voltage sources 3 and 6 to the differential input of comparator No. 2 (channels: 32, 48) of the ADC circuit of FIG. 4. Moreover, in the circuit of FIG. four:

- takes into account the capacitance on the substrate of the reference resistors 4 and 7;

- sequentially with the capacitance of each correction capacitors 15 and 18 (C _k ), additional resistors R = 50 Ohms are included;

- parasitic output capacitance of current mirrors 12 and 16 has an increased value With _n = 300 fF;

- used real voltage comparators 1 (differential stages) with parasitic capacitances of its transistors.

An ultra-fast parallel analog-to-digital converter with differential input contains N identical architecture sections of FIG. 3. Each of the sections includes a voltage comparator 1, the first 2 input of which is connected to the first 3 source of input voltage through the first 4 reference resistor, and the second 5 input of the voltage comparator 1 is connected to the second 6 source of input antiphase voltage through the second 7 reference resistor, the first 2 input of voltage comparator 1 is connected to the first 8 reference current source and the first 9 spurious capacitor, second 5 input of voltage comparator 1 is connected to the second 10 reference current source and the second 11 parasitic capacitor m The first 8 reference current source is made in the form of a first 12 current mirror, matched with the first 13 bus power source, and the first 14 auxiliary reference current source connected to the input of the first 12 current mirror, and the output of the first 12 current mirror is the output of the first 8 reference current source and the second 6 source of input antiphase voltage is connected to the input of the first 12 current mirrors through the first 15 correction capacitor. The status of the outputs of the voltage comparators is judged on the digital equivalent of the input signal.

In Fig. 3, in accordance with claim 2, the second 10 reference current source is made in the form of a second 16 current mirror, matched with the first 13 bus of the power source, and the second 17 auxiliary reference current source connected to the input of the second 16 current mirror moreover, the output of the second 16 current mirror is the output of the second 10 source of reference current, and the first 3 source of input voltage is connected to the input of the second 16 current mirror through the second 18 correction capacitor.

In figure 4, in accordance with claim 3 of the claims, additional resistors are connected in series with each correction capacitor 15 and 18.

Consider the operation of the analog sections of the ADC of FIG. 1, FIG. 2 and FIG. 3, including reference resistors 4, 7, reference current sources 8, 10, voltage comparator 1.

In the ADC prototype of FIG. 1, the speed of the analog section of FIG. 2 (its maximum frequency range is f in _max ) is determined by parasitic capacitors 9 and 11. The practically upper cut-off frequency (level - 1 dB) of the ADC prototype when implemented using SiGe technology does not exceed 2-7 GHz (Fig. 5, Fig. 6), while the speed of the comparator 1, implemented on microwave SiGe transistors [28, 29] with f _T = 200 GHz, allows you to work in a wider frequency range (20 ÷ 50 GHz).

In the inventive device of FIG. 3 due to the introduction of new connections, the limiting range of operating frequencies of the analog section of the ADC is expanded 2-6 times (Fig.5-Fig.7). This allows for analog-to-digital conversion of higher frequency signals.

The introduction of corrective resistors in series with the correction capacitors 18 and 15 (Fig. 4) makes it possible to optimize the unevenness of the amplitude-frequency characteristics of the analog part of the ADC section, which creates the conditions for further expansion of the frequency range (Fig. 6, Fig. 7).

Thus, the claimed device is characterized by significant advantages in comparison with the prototype in the frequency range of the processed signals.

BIBLIOGRAPHIC LIST

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Claims (3)

1. An ultra-fast parallel analog-to-digital converter with a differential input, each of the N sections of which contains a voltage comparator (1), the first (2) input of which is connected to the first (3) input voltage source through the first (4) reference resistor, and the second ( 5) the input of the voltage comparator (1) is connected to the second (6) source of input antiphase voltage through a second (7) reference resistor, and the first (2) input of the voltage comparator (1) is connected to the first (8) reference current source and the first (9 a) parasitic condensation orom, the second (5) input of the voltage comparator (1) is connected to the second (10) reference current source and the second (11) spurious capacitor, characterized in that the first (8) reference current source is made in the form of the first (12) current mirror, coordinated with the first (13) bus power supply, and the first (14) auxiliary reference current source connected to the input of the first (12) current mirror, and the output of the first (12) current mirror is the output of the first (8) reference current source, and the second (6) source of input antiphase coupling voltage n from the first input (12) via a first current mirror (15) correcting capacitor. 2. The ultra-fast parallel analog-to-digital converter with a differential input according to claim 1, characterized in that the second (10) reference current source is made in the form of a second (16) current mirror, matched with the first (13) bus of the power source, and the second ( 17) an auxiliary reference current source connected to the input of the second (16) current mirror, and the output of the second (16) current mirror is the output of the second (10) reference current source, and the first (3) input voltage source is connected to the input of the second (16) current mirror la through the second (18) correction capacitor. 3. An ultra-fast parallel analog-to-digital converter with a differential input according to claim 2, characterized in that additional resistors are connected in series with each correction capacitor (15) and (18).

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