RU2523960C1 - Ultra-high-speed parallel analogue-to-digital converter with differential input - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: ultra-high-speed parallel analogue-to-digital converter with a differential input has N sections of identical architecture. Each of the sections includes a voltage comparator (1), the first (2) input of which is connected to a first (3) input voltage source through a first (4) reference resistor, and the second (5) input of the voltage comparator (1) is connected to a second (6) input anti-phase voltage source through a second (7) reference resistor. The first (2) input of the voltage comparator (1) is connected to a first (8) reference current source and a first (9) parasitic capacitor, the second (5) input of the voltage comparator (1) is connected to a second (10) reference current source and a second (11) parasitic capacitor. The first (3) input voltage source is connected to the base of a first (12) additional transistor, the collector of which is connected to the bus of a first (13) power supply, and the emitter is connected to the bus of a second (14) power supply through a first (15) current-stabilising two-terminal device and through a first (16) balancing capacitor to the first (2) input of the voltage comparator (1).

EFFECT: multifold expansion of the frequency range of processed signals of an analogue-to-digital converter by reducing the transmission error of input differential voltages to voltage comparator inputs.

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Description

The present invention relates to the field of measuring and computing, radio engineering, communications and can be used in the structure of various devices for processing analog information, measuring instruments, telecommunication systems, etc.

In modern technology, widespread use are parallel analog-to-digital converters (ADCs), which provide the highest conversion speed of analog signals (u _in ) to digital signals [1-27]. With an increase in the frequency of the input voltage u _I in such microelectronic ADCs, significant conversion errors arise due to the influence of stray capacitors formed by capacitors on the substrate of active and passive components [28-29]. A further increase in the performance of parallel ADCs is one of the problems of modern information-measuring equipment, the solution of which will allow the practical implementation of new communication systems and telecommunications with higher quality indicators.

The closest in technical essence to the claimed device is a parallel ADC, described in patent US 7.394.420, fig.3, fig.4. An analysis of its limiting frequency range (f _in.max ), as well as attempts to increase f _in.max by optimizing the absolute values of R reference resistors, are discussed in [28–29], including a co-author of this application [29].

The ADC prototype, figure 1 contains N identical in architecture sections (figure 2, figure 3). Each section includes a voltage comparator 1, the first 2 input of which is connected to the first 3 source of input voltage through the first 4 reference resistor, and the second 5 input of the voltage comparator 1 is connected to the second 6 source of input antiphase voltage through the second 7 reference resistor, the first 2 input a voltage comparator 1 is connected to a first 8 reference current source and a first 9 spurious capacitor, a second 5 input of a voltage comparator 1 is connected to a second 10 reference current source and a second 11 spurious capacitor.

A significant drawback of the ADC prototype (Fig. 1), one of the analog sections of which is also shown in the drawings of Fig. 2 and Fig. 3, is that its limiting frequency range is the conversion of input analog signals to digital (even when implemented on microwave transistors with f _max = 200 GHz, the technical process SGB25H1, IHP, Germany [28, 29]) is limited due to the reduction at high frequencies of the transmission coefficient from input voltage sources 3 and 6 to the inputs of voltage comparators 1.

The main objective of the invention is to expand several times the limit frequency range of the processed ADC signals by reducing the error of transmission of input differential voltages (sources 3, 6) to the inputs of voltage comparators 1.

The problem is achieved in that in a parallel analog-to-digital Converter with a differential input (figure 1, figure 2, figure 3), each of the N-sections of which (figure 3) contains a voltage comparator 1, the first 2 input of which is connected with the first 3 source of input voltage through the first 4 reference resistor, and the second 5 input of the voltage comparator 1 is connected to the second 6 source of input antiphase voltage through the second 7 reference resistor, and the first 2 input of the voltage comparator 1 is connected to the first 8 source of reference current and the first 9 parasitic capacitor, the second 5 input of the voltage comparator 1 is connected to the second 10 reference current source and the second 11 parasitic capacitor, new elements and connections are provided - the first 3 input voltage source is connected to the base of the first 12 additional transistor, the collector of which is connected to the bus of the first 13 power supply, and the emitter is connected to the bus of the second 14 power supply through the first 15 current-stabilizing two-terminal and through the first 16 correction capacitor is connected to the first 2 input of the comparator voltage Adjustment 1.

The drawing of figure 1 shows the circuit of the ADC prototype, which contains N-parallel connected sections with the same architecture, but with different absolute values of the resistances of the reference resistors 4 (7) and currents I ₈ (I ₁₀ ) of the sources of the reference currents 8 (10).

The drawing of FIG. 2 is a diagram of FIG. 1, in which, in each of the N architecture-identical sections, the output transistors of the reference current sources 8 and 10 are shown having a capacitance on a substrate (C _p ) and a collector-base capacitance (C _k ). Thus, the stray capacitance 9 and 11 in the circuits of figure 2 and figure 3 are determined by the output capacitance of the transistors of the reference current sources 8 and 10 and the input capacitance of the voltage comparator 1.

The drawing of figure 3 shows the equivalent circuit of one of the analog sections of the ADC prototype of figure 2.

The drawing of figure 4 shows a diagram of the analog section of the proposed ADC, corresponding to claims 1, 2 of the claims.

The drawing of figure 5 presents the diagram of the inventive ADC in the Cadence environment on models of integrated transistors (transistors SiGe: npn 200-p; process technology SG25H1, IHP, Iк.max = 4 mA, A high-performance 0.25 μm technology with npn-HBTs up to f _T / f _max = 180/220 GHz). Moreover, in the diagram of figure 5 are taken into account:

- the capacitance on the substrate of the reference resistors 4 and 7, as well as the stray capacitance of the transistors 12, 17;

- spurious input capacitance of voltage comparators 1 (real differential stages, taking into account spurious capacitances of their transistors).

Spurious capacitances of the current-stabilizing two-terminal 15, 8, 10, 18 in this experiment with the circuit of figure 5 are not taken into account.

The drawing of Fig.6 shows a logarithmic amplitude-frequency characteristic of the voltage transfer coefficient from voltage sources 3 and 6 of the ADC of Fig.5 to the differential input of comparator No. 2 (channels: 32, 48) for different capacitances of the first 16 (C 16) and second 19 (C 19) correction capacitors (C16 = C19 = C _to = 0 ÷ 100 fF). From these graphs it follows that the limit frequency (at a level of -1 dB) of the proposed analog section of the ADC is increased from 13.8 GHz to 84.8 GHz.

The drawing of Fig.7 shows a diagram of the inventive ADC in the Cadence environment on models of integrated transistors (Transistors SiGe: npn 200-n; process technology SG25H1, IHP, Iк.max = 4 mA (A high-performance 0.25 µm technology with npn-HBTs up to f _T / f _max = 180/220 GHz.). In this case, in this experiment with the circuit of Fig. 7, the following are taken into account:

- capacitance on the substrate of the reference resistors 4 and 7, as well as stray capacitance of the transistors 12, 17;

- spurious input capacitance of comparators 1 (real differential stages, taking into account spurious capacitances of their transistors).

In addition, the current-stabilizing two-terminal networks 15, 18 in the circuit of Fig. 7 are implemented on the basis of resistors providing a current of 1 mA, taking into account spurious capacitances on the substrate. The real parasitic capacitances of the current-stabilizing two-terminal circuits 8 and 10 in the circuit of Fig. 7 were modeled by connecting in parallel with this ideal two-terminal network special closed n-p-n transistors, taking into account their stray collector-base capacitances and capacitances on the substrate.

The drawing of Fig. 8 shows the logarithmic amplitude-frequency characteristic of the voltage transfer coefficient from the inputs of the ADC 3 and 6 (Fig. 4, Fig. 7) to the differential input of the comparator No. 2 (channels: 32, 48) for different capacitances of the first 16 ( C 16) and second 19 (C 19) correction capacitors C16 = C19 = CK = 0 ÷ 300 fF. From these graphs it follows that the limit frequency of the analog section of the proposed ADC is increased from 10.4 GHz to 51.7 GHz.

An ultra-fast parallel analog-to-digital converter with a differential input contains N sections identical in architecture (Fig. 4). Each section includes a voltage comparator 1, the first 2 input of which is connected to the first 3 source of input voltage through the first 4 reference resistor, and the second 5 input of the voltage comparator 1 is connected to the second 6 source of input antiphase voltage through the second 7 reference resistor, the first 2 input a voltage comparator 1 is connected to a first 8 reference current source and a first 9 spurious capacitor, a second 5 input of a voltage comparator 1 is connected to a second 10 reference current source and a second 11 spurious capacitor. The first 3 input voltage source is connected to the base of the first 12 additional transistor, the collector of which is connected to the bus of the first 13 power supply, and the emitter is connected to the bus of the second 14 power supply through the first 15 current-stabilizing two-terminal device and connected through the first 16 correction capacitor to the first 2 input of the voltage comparator one.

In the drawing of FIG. 4, in accordance with claim 2, a second 6 input antiphase voltage source is connected to the base of the second 17 additional transistor, the collector of which is connected to the bus of the first 13 power source, and the emitter is connected to the bus of the second 14 power source through the second 18 is a current-stabilizing two-terminal device and through the second 19 correction capacitor is connected to the second 5 input of voltage comparator 1.

Consider the operation of one of the analog sections of the inventive ADC (figure 4), including reference resistors 4, 7 and reference current sources 8, 10.

In the ADC prototype of FIG. 1, FIG. 3, the speed of the analog part (its maximum frequency range f _in.max ) is determined by the capacitance of parasitic capacitors 9 and 11. The practically maximum upper cut-off frequency (level -1 dB) of the analog section of the ADC prototype is not exceeds 13-14 GHz (Fig.6, C16 = C19 = C _k = 0), while the speed of the comparator 1, implemented on microwave SiGe transistors [28, 29] with f _t = 200 GHz, allows you to work in a wider frequency range (20 ÷ 50 GHz).

In the inventive device due to the introduction of correction capacitors 16 and 19, the range of operating frequencies of the analog section of the ADC is expanded 5-6 times (Fig.7, Fig.8). This allows for analog-to-digital conversion of higher frequency signals.

The introduction of corrective resistors in series with the correction capacitors 16 and 19 (FIG. 5, FIG. 7) makes it possible to optimize the non-uniformity of the amplitude-frequency characteristics of the analog section of the inventive ADC, which creates the conditions for further expansion of the limiting frequency range.

Thus, the claimed device is characterized by significant advantages in comparison with the prototype in the limiting frequency range of the processed signals.

BIBLIOGRAPHIC LIST

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Claims (2)

1. An ultra-fast parallel analog-to-digital converter with a differential input, each of the N sections of which contains a voltage comparator (1), the first (2) input of which is connected to the first (3) input voltage source through the first (4) reference resistor, and the second ( 5) the input of the voltage comparator (1) is connected to the second (6) source of input antiphase voltage through a second (7) reference resistor, and the first (2) input of the voltage comparator (1) is connected to the first (8) reference current source and the first (9 a) parasitic condensation orom, the second (5) input of the voltage comparator (1) is connected to the second (10) reference current source and the second (11) stray capacitor, characterized in that the first (3) input voltage source is connected to the base of the first (12) additional transistor, whose collector is connected to the bus of the first (13) power source, and the emitter is connected to the bus of the second (14) power source through the first (15) current-stabilizing two-terminal device and through the first (16) correction capacitor is connected to the first (2) input of voltage comparator 1. 2. The ultra-fast parallel analog-to-digital converter with a differential input according to claim 1, characterized in that the second (6) source of input antiphase voltage is connected to the base of the second (17) additional transistor, the collector of which is connected to the bus of the first (13) power source, and the emitter is connected to the bus of the second (14) power source through the second (18) current-stabilizing two-terminal device and through the second (19) correction capacitor is connected to the second (5) input of the voltage comparator (1).

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