RU2517423C1 - Digital modular for control over synchronous motor - Google Patents

Abstract

FIELD: engines and pumps.

SUBSTANCE: modulator comprises rectangular pulse generator, counters, OR elements, triggers, inverter, limiting circuit, decoders, pulse shapers, AND elements, reset circuit, adders, registers, AND-NO elements, binary-sextic counter, input signal bus, sign bus, bus of the signal describing engine design version, rotor position transducer signal bus and output buses.

EFFECT: control over rpm in DC brushless motor mode in response to rotor position transducer signals.

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Description

The invention relates to the field of pulsed technology and can be used in power converters of control systems of synchronous motors equipped with rotor position sensors.

The closest in technical essence is a digital modulator for a frequency converter of an induction motor (see RF patent No. 2216850, publ. November 20, 2003, Bull. No. 32), containing a square-wave pulse generator, four counters, three triggers, four OR elements, an inverter, two AND elements, six NAND elements, three decoders, two pulse shapers, two adders, two registers, a binary-hex counter, a limit circuit and a reset circuit.

The disadvantage of the closest digital modulator is that it can control a synchronous motor only by changing the frequency of the supply voltage supplied to the stator windings. At the same time, the device taken as a prototype cannot regulate the speed of a synchronous machine in the mode of a brushless DC motor using the signals from the rotor position sensor.

The essence of the invention lies in the fact that in a digital modulator for controlling a synchronous electric motor, comprising a first square-wave generator, first, second, third and fourth counters, first, second and third elements OR, first, second and third trigger, inverter, limiting circuit, first , the second and third decoders, the first and second pulse shapers, the first and second elements And, the reset circuit, the first and second adders, the first and second registers, the first, second, third, fourth, fifth and sixth elements AND NOT an ochical-sixth counter, the output of the first rectangular pulse generator being connected to the first input of the first counter and the first inputs of the first and second OR elements, the second inputs of the first and second OR elements connected, respectively, to the direct and inverse outputs of the first trigger, the first input of which is connected to the sign bus and the second input is with the inverter output, the outputs of the first and second OR elements are connected respectively to the first and second inputs of the second counter, the third input of which is connected to the output of the limiting circuit, the first and second inputs of the limiting circuit are connected respectively to the input signal bus and the sign bus, the output of the second counter is connected to the first input of the second trigger, the output of which is connected to the first inputs of the first, second and third decoders, the output of the first pulse shaper is connected to the second inputs of the second and third of decoders, the output of the first counter is connected to the first input of the first element And, the second input of which is connected to the output of the reset circuit, the output of the restriction circuit is connected to the first input of the first adder a, whose output is connected to the first input of the first register, the output of the first rectangular pulse generator is connected to the first input of the third counter, the output of which is connected to the first input of the third trigger, the output of the first register is connected to the second inputs of the first adder and the third counter, the output of the first element And is connected with the inverter input, the second inputs of the second and third triggers and the first counter, the third input of the third counter and the fourth input of the second counter, the direct output of the second register is connected to the first the ode of the second adder, the output of which is connected to the first input of the second register, the first, second, third, fourth, fifth and sixth outputs of the first decoder are connected respectively to the first inputs of the fifth, first, sixth, second, fourth and third elements NAND, the outputs of which connected to the output buses, the first, second, third, fourth, fifth and sixth outputs of the second decoder are connected respectively to the second inputs of the first, sixth, second, fourth, third and fifth I-HE elements, the first, second, third, fourth, the fourth and sixth outputs of the third decoder are connected respectively to the third inputs of the third, fifth, first, sixth, second and fourth NAND elements, the direct and inverse outputs of the second trigger are connected respectively to the third inputs of the second and third decoders, an additional square-wave generator is additionally introduced, the fourth trigger, the third, fourth, fifth and sixth pulse shapers, the third element And, the third adder and the third register, and the second input of the second adder is connected to the signal bus, operating the motor design, the inverse output of the second register is connected to the first input of the third adder, the second input of which is connected to the bus of the position sensor of the rotor of the synchronous motor, the highest discharge of the output of the third adder is connected to the first input of the fourth trigger, the output of which is connected to the first input of the third OR element, the output of the second rectangular pulse generator is connected to the second input of the third OR element, the output of which is connected to the input of the second pulse shaper, you One of the second pulse shaper is connected to the input of the third pulse shaper, the first input of the fourth counter and the second inputs of the first and second registers, the output of the third pulse shaper is connected to the second input of the fourth trigger, the output of the fourth counter is connected to the first inputs of the binary-hex counter and the second element And, the output of which is connected to the third input of the first register, the second input of the binary-hex counter is connected to the sign bus of the input signal, the output of the binary-hex counter connected to the first input of the third register, the first, second and third outputs of which are connected respectively to the second, third and fourth inputs of the first decoder and the fourth, fifth and sixth inputs of the second and third decoders, the output of the first element And is connected to the inputs of the first and fourth pulse shapers, the output of the first pulse shaper is connected to the fifth input of the first decoder, the direct output of the fourth pulse shaper is connected to the second input of the third register, the inverse output of the fourth shaper the pulse generator is connected to the input of the fifth pulse shaper, the output of which is connected to the first input of the third element And, the output of the reset circuit is connected to the third input of the third register and the second input of the third element And, the output of which is connected to the input of the sixth pulse shaper, the second input of the fourth counter and the third the input of the binary-hex counter, the output of the sixth pulse shaper is connected to the second input of the second element And and the third inputs of the second register and fourth trigger.

Significant differences are expressed in a new set of connections between the elements of the device. The specified set of connections allows using the proposed digital modulator to control the speed of a synchronous machine in the mode of a brushless DC motor according to the signals of the rotor position sensor.

Figure 1 presents a functional diagram of a digital modulator for controlling a synchronous electric motor, figure 2 is a functional diagram of a limiting circuit, Fig. 3 is a functional diagram of a binary-hex counter, Fig. 4 is a timing diagram of a digital modulator, and Fig. 5 is a diagram of a digital modulator connected to a power converter.

A digital modulator for controlling a synchronous electric motor (Fig. 1) contains rectangular pulse generators 1 and 2, counters 3, 4, 5 and 6, OR elements 7, 8 and 9, triggers 10, 11, 12 and 13, inverter 14, circuit 15 restrictions, decoders 16, 17 and 18, drivers 19, 20, 21, 22, 23 and 24 pulses, elements 25, 26 and 27 I, reset circuit 28, adders 29, 30 and 31, registers 32, 33 and 34, elements 35, 36, 37, 38, 39 and 40 AND-NOT, binary-hex counter 41, input signal bus 42, sign bus 43, signal bus 44 characterizing the engine design, bus 45 of the rotor position sensor signal, output buses 46, 47, 48, 49, 50, and 51.

The output of the rectangular pulse generator 1 is connected to the first input of the counter 3 and the first inputs of the elements 7 and 8 OR. The second inputs of the elements 7 and 8 OR are connected respectively to the direct and inverse outputs of the trigger 10, the first input (D-input) of which is connected to the bus 43 signs, and the second input (gating input) is connected to the output of the inverter 14. The outputs of the elements 7 and 8 OR connected respectively to the first (reverse counting) and second (direct counting) inputs of the counter 4, the third input (preset input) of which is connected to the output of the limiting circuit 15. The first and second inputs of the limiting circuit 15 are connected respectively to the input signal line 42 and the sign line 43. The output of the counter 4 (transfer output) is connected to the first input (installation input) of the trigger 11, the output of which is connected to the first inputs (resolution inputs) of the decoders 16, 17 and 18. The output of the pulse shaper 19 is connected to the second inputs (resolution inputs) of the decoders 17 and 18. The output of the counter 3 (transfer output) is connected to the first input of the AND element 25, the second input of which is connected to the output of the reset circuit 28. The output of the limiting circuit 15 is connected to the first input of the adder 29, the output of which is connected to the first input of the register 32. The output of the square-wave generator 1 is connected to the first input (countdown input) of the counter 5, the output of which (transfer output) is connected to the first input (installation input) ) trigger 12. The output of the register 32 is connected to the second inputs of the adder 29 and counter 5 (the counter uses the preset input). The output of the 25 And element is connected to the input of the inverter 14, the second inputs of the triggers 11 and 12 and the counter 3, the third input of the counter 5 and the fourth input of the counter 4 (the triggers use the reset inputs, and the counters use the gating inputs). The direct output of the register 33 is connected to the first input of the adder 30, the output of which is connected to the first input of the register 33. The first, second, third, fourth, fifth and sixth outputs of the decoder 16 are connected respectively to the first inputs of the elements 39, 35, 40, 36, 38 and 37 AND NOT, the outputs of which are connected respectively to the output buses 50, 46, 51, 47, 49 and 48. The first, second, third, fourth, fifth and sixth outputs of the decoder 17 are connected respectively to the second inputs of the elements 35, 40, 36, 38, 37 and 39 AND NOT. The first, second, third, fourth, fifth and sixth outputs of the decoder 18 are connected respectively to the third inputs of the elements 37, 39, 35, 40, 36 and 38 AND-NOT. The direct and inverse outputs of the trigger 12 are connected respectively to the third inputs (resolution inputs) of the second and third decoders 17 and 18. The second input of the adder 30 is connected to a signal bus 44 characterizing the design of the engine. The inverse output of the register 33 is connected to the first input of the adder 31, the second input of which is connected to the bus 45 of the signal of the position sensor of the rotor of the synchronous motor. The senior bit of the output of the third adder 31 is connected to the first input (D-input) of the trigger 13, the output of which is connected to the first input of the third element 9 OR. The output of the rectangular pulse generator 2 is connected to the second input of the OR element 9, the output of which is connected to the input of the pulse shaper 20. The output of the pulse shaper 20 is connected to the input of the pulse shaper 21, the first input (direct count input) of the counter 6 and the second inputs (gating inputs) of the registers 32 and 33. The output of the pulse shaper 21 is connected to the second input (gating input) of the trigger 13. Counter output 6 (transfer output) is connected to the first inputs of the binary-hex counter 41 (the counter uses a direct count input) and an AND element 26, the output of which is connected to the third input (reset input) of register 32. The second input (the first and second digits of the input installation) binary-hex counter 41 is connected to the bus 43 of the sign of the input signal. The output (first, second and third bits) of the binary-hex counter 41 is connected to the first input of the register 34, the first, second and third outputs (binary bits) of which are connected respectively to the second, third and fourth inputs (information inputs) of the decoder 16 and fourth, fifth and sixth inputs (information inputs) of the decoders 17 and 18. The output of the element 25 And is connected to the inputs of the drivers 19 and 22 of the pulses. The output of the pulse shaper 19 is connected to the fifth input (resolution input) of the decoder 16. The direct output of the pulse shaper 22 is connected to the second input (gating input) of the register 34. The inverse output of the fourth pulse shaper 22 is connected to the input of the pulse shaper 23, the output of which is connected to the first input of the third element 27 I. The output of the reset circuit 28 is connected to the third input (reset input) of the register 34 and the second input of the And element 27, the output of which is connected to the input of the pulse shaper 24, the second input of the counter 6 (input gating m) and third input (input sampling) Senary binary counter 41. The output pulse generator 24 is connected to the second input of the AND element 26 and the third input (reset) flip-flop 33 and register 13.

Generators 1 and 2 of rectangular pulses can be performed, for example, on a 155LAZ chip with quartz stabilization or with a timing capacitor. Counters 3, 4, 5 and 6, for example, are made on K555IE7 microcircuits. Elements 7, 8 and 9 OR, for example, are made on the chip K555LL1. Triggers 10, 11, 12 and 13 can be performed, for example, on K555TM2 microcircuits, and inverter 14 - on a K555LN1 microcircuit. Decoders 16, 17 and 18 can be performed, for example, on K555ID7 microcircuits, pulse shapers 19, 20, 21, 22, 23 and 24 pulses on K555AGZ microcircuits, elements 25, 26 and 27 And on a K555LI microcircuit. Adders 29, 30 and 31 can be performed, for example, on K555IM6 chips, registers 32, 33 and 34 on K555TM8 chips, and elements 35, 36, 37, 38, 39, 40 AND-NOT on K155LA4 chips.

The limitation circuit 15 (FIG. 2) contains, for example, an OR element group 52, an AND element group 53, an AND-NOT element 54, an OR element 55 and 56, an OR-NOT element 57, and an inverter 58.

Depending on the value by which the input signal should be limited, the n-bit inputs of bus 42 are divided into two groups: from 1 to (n-m) and from (n-m + 1) to n, with m <n. The first group of bits - from 1 to (n-m), is connected to the first inputs of the group of 52 OR elements, the outputs of which are connected to the first inputs of the group of 53 AND elements, the outputs of which are (n-m) the least significant bits of the output of the limiting circuit 15. The second group of bit inputs of the bus 42 - from (n-m + 1) to n - are the corresponding bits of the output of the limiting circuit 15. They are connected to the m inputs of an AND-AND element 54 and an OR element 55. The output of the element 54 AND-NOT connected to the first input of the element 56 OR, the output of which is connected to the second inputs of the group 53 of the elements I. The output of the element 55 OR is connected to the first input of the element 57 OR, the second input of which is connected to the output of the inverter 58, and the output - with the second inputs of the group of 52 elements OR. The second input of the OR element 56 and the input of the inverter 58 are connected to the sign bus 43.

The reset circuit 28, for example, can be made in the form of a series-connected resistor and capacitor, the second terminal of the resistor being connected to the power bus, and the second terminal of the capacitor to the common bus. The resistance terminal connected to the capacitor is the output of the reset circuit 28.

The binary-hex counter 41 (FIG. 3), for example, comprises a binary counter 59, an AND element 60, and a pulse shaper 61. The first, second and third output bits of the counter 59 are the output of the binary-hex counter 41. The second and third output bits of the counter 59 are connected respectively to the first and second inputs of the And element 60, the output of which is connected to the input of the pulse shaper 61. The output of the pulse shaper 61 is connected to the reset input of the counter 59. The direct counter input of the counter 59 is the first input of the binary-hex counter 41. The counter counter input 59 is connected to a logical unit. The first and second bits of the preset input of the counter 59 are combined and are the second input of the binary-hex counter 41. The third and fourth bits of the preset input of the counter 59 are connected to a common bus. The gate input of the counter 59 is the third input of the binary-hex counter 41.

A digital modulator for controlling a synchronous motor operates as follows.

After turning on the supply voltage, the reset circuit 28 generates a signal that registers 34. The same signal through element 25 And sets the triggers 11 and 12 to the initial state, gates the counters 3, 4, and 5, and then triggers the trigger 10 through the inverter 14. The signal from the output of the reset circuit 28 through the element 27 AND gates the counter 6 and the binary-hex counter 41 and then through the pulse shaper 24 sets register 33 and the trigger 13 to the initial state and then through the element 26 And the register 32. When the gate 4 is gated it records the input signal passing through the limiting circuit 15. The sign code of this signal is recorded in trigger 10. Depending on the sign of the input signal, the pulses of generator 1 with a frequency f ₀ pass either through element 7 OR (positive sign) or element 8 OR (negative sign) and are received respectively at the input of the countdown, or to the input of the direct counting of the counter 4. Depending on the module, the magnitude N of the input signal at the outputs of the transfer of the counter 4 after a period of time

, $$t_{\mathrm{one}}=\frac{|\; |\; |N|\; |\; |}{f_0}$$

,

where n is the number of bits of the binary counter 4,

after the initial installation (gating), a negative pulse will appear (Fig. 4a). This negative pulse is fed to the input of the installation of the trigger 11, the output of which at the same time a high level signal appears (fig.4b). Rectangular pulses from the generator 1 also arrive at the counting input of the counter 3. Therefore, at the output of the transfer of the counter 5 after a period of time

$$t_2=\frac{2^n}{f_0}$$

.after the initial installation, a negative impulse appears (Fig. 4 c), which, passing through the element 25 And, is fed to the reset input of trigger 11 and returns to its original state. The negative pulse from the output of 25 And gates the counters 3, 4 and 5 and through the inverter 14 - trigger 10 signs, after which the process of generating the output signals of the counters 3 and 4 and trigger 10 is repeated. As a result, a trigger signal is generated at the output of trigger 11 (Fig. 4b) $${\gamma }_{\mathrm{one}}=\frac{|\; |\; |N|\; |\; |}{2^n}$$

.

Simultaneously with the operation of the above-mentioned elements, the input signal, passing through the limiting circuit 15, is fed to the input of the adder 29 and is added to the output signal of the register 32, and the signal characterizing the design of the engine is fed to the input of the adder 30 and added to the output signal of the register 33. The value the signal characterizing the design of the electric motor can be determined by the formula:

, $$\Delta N_{\mathrm{about}PR}=\frac{2^{-k}{N}_{\partial PR}^{\max }}{6Z_n}$$

,

- количество дискрет (импульсов) датчика положения ротора на оборот вала электродвигателя; Z_n - число пар полюсов синхронного электродвигателя.where k is the number of bits of the binary counter 6; $$N_{\partial PR}^{\max }$$

- the number of discrete (pulses) of the rotor position sensor per revolution of the motor shaft; Z _n - the number of pairs of poles of the synchronous motor.

At the same time, the signal of the rotor position sensor from the bus 45 is fed to the input of the adder 31 and compared with the signal from the output of the register 33. At the initial time, the output of the registers 32 and 33 and the trigger 13 contains a zero signal. Therefore, the pulses from the generator 2 through the element 9 OR are fed to the input of the shaper 20 pulses. The pulses from the output of the shaper 20 go to the input of the direct count of the counter 6 and the gating inputs of the registers 32 and 33 and through the shaper 21 of the pulses to the gating input of the trigger 13. As a result, the signals at the output of the adders 29 and 30 and the registers 32 and 33 increase, and through 2 ^k pulse occurs the output register 32 reset to zero by the signal from the counter 6 via the output member 26 I. Because the output signal of register 33 increases, at a certain cycle of the generator 2 output pryamoug lnyh pulses older (landmark) output of adder 31 appears discharge the high-level signal, which is written in the flip-flop 13 and block the passage of oscillator pulses through the element 2 OR 9. By this time, a specific digital code will be generated at the output of register 32. Since the output signal from the output of counter 6 also enters the input of the binary-hex counter 41, a certain digital code will also be generated at its output, depending on the value of the signal from the rotor position sensor. It should be noted that the reference point of the rotor position sensor can be carried out, for example, from the negative direction of the axis of the phase A winding of the synchronous electric motor (in relation to a two-pole machine).

According to the signal from the output of element 25 AND, the digital code from the output of register 32 with a shift by k bits to the right is recorded in binary counter 5, at the transfer output of which a negative pulse appears after a time interval t ₃ after gating. This negative pulse is fed to the input of the trigger 12, the output of which appears a high level signal. Upon arrival at the reset input of the trigger 12 of a negative pulse from the output of the element 25 And at the output of the trigger 12 a low level signal is set. And then the process repeats. As a result, a signal with a duty cycle is generated at the direct output of trigger 12 (Fig. 4d)

. $${\gamma }_P=\frac{t_3}{t_2}$$

.

It should be noted that the value of t ₃ depends on the digital code at the output of the register 32, which in turn is determined by the value of N and the digital code of the position sensor of the rotor of the electric motor. A signal with a duty cycle is generated at the inverse output of trigger 12

γ _И = 1 - γ _П.

The signal from the output of the element 25 And also triggers the pulse shaper 22, which gates the register 34. At the same time, the signal from the output of the binary-hex counter 41, which controls the decoders 16, 17 and 18, passes to the output of the register 34.

The process of generating the output signals of the register 32, the binary-hex counter 41 and the register 34 is carried out with the frequency of occurrence of the low level signal at the output of the element 25 And, that is, with the frequency of the pulse width modulation.

Depending on the code combination of the signals of the outputs of the register 34 and the signals from the outputs of the triggers 11 and 12, the decoders 16, 17 and 18 through the elements 35, 36, 37, 38, 39 and 40 AND-NOT provide a width-modulated signal to the output buses 46, 47 , 48, 49, 50, and 51 of a digital modulator. If signals from buses 46, 47, 48, 49, 50, and 51 are fed through amplifiers to a power three-phase transistor bridge with a synchronous electric motor connected to it, as shown, for example, in Fig. 5, then the generated voltage system will cause the motor rotor to rotate. For certain values of N of the input signal at the input of the digital modulator and the steady rotation speed of the synchronous electric motor, the waveforms at the outputs of the register 34 will correspond to the drawings shown in Figs. 4e, e, g. At the same time, output signals 46, 47, 48, 49, 50, and 51 will generate signals corresponding to the graphs presented in Fig.4z, and, k, l, m, n.

The signal from the output of the pulse shaper 19 is used to block the decoders 16, 17 and 18, which allows you to organize the sliding front when changing the sign of the input signal. The pulse generator 23 is necessary for synchronizing the operation of the register 34 and the binary-hex counter 41. The signal from the sign bus 43 is fed to the input of the preliminary setting of the binary-hex counter 41 with the aim of automatically organizing the braking modes and reversing when the sign of the input signal is changed. The limiting circuit 15 is intended to limit at a certain level of the input signal in order to exclude the possibility of overturning pulse-width modulation.

Thus, the proposed digital modulator allows you to adjust the speed of the synchronous machine in the mode of a brushless DC motor according to the signals of the rotor position sensor.

Claims (1)

A digital modulator for controlling a synchronous electric motor, comprising a first square-wave pulse generator, first, second, third and fourth counters, first, second and third OR elements, first, second and third flip-flops, an inverter, a limiting circuit, first, second and third decoders, the first and second pulse shapers, first and second AND elements, a reset circuit, first and second adders, first and second registers, first, second, third, fourth, fifth, and sixth elements AND NOT and a binary-hex counter, and the output is first The first rectangular pulse generator is connected to the first input of the first counter and the first inputs of the first and second OR elements, the second inputs of the first and second OR elements are connected respectively to the direct and inverse outputs of the first trigger, the first input of which is connected to the sign bus, and the second input is connected to the output inverters, the outputs of the first and second elements OR are connected respectively to the first and second inputs of the second counter, the third input of which is connected to the output of the limiting circuit, the first and second inputs of the limiting circuit they are connected respectively with the input signal bus and the sign bus, the output of the second counter is connected to the first input of the second trigger, the output of which is connected to the first inputs of the first, second and third decoders, the output of the first pulse shaper is connected to the second inputs of the second and third decoders, the output of the first counter is connected with the first input of the first element And, the second input of which is connected to the output of the reset circuit, the output of the restriction circuit is connected to the first input of the first adder, the output of which is connected to the first input of of the first register, the output of the first rectangular pulse generator is connected to the first input of the third counter, the output of which is connected to the first input of the third trigger, the output of the first register is connected to the second inputs of the first adder and the third counter, the output of the first element And is connected to the inverter input, the second inputs of the second and the third flip-flops and the first counter, the third input of the third counter and the fourth input of the second counter, the direct output of the second register is connected to the first input of the second adder, the output of which is connected with the first input of the second register, the first, second, third, fourth, fifth and sixth outputs of the first decoder are connected respectively to the first inputs of the fifth, first, sixth, second, fourth and third elements AND NOT, the outputs of which are connected to the output buses, the first , the second, third, fourth, fifth and sixth outputs of the second decoder are connected respectively to the second inputs of the first, sixth, second, fourth, third and fifth elements NAND, the first, second, third, fourth, fifth and sixth outputs of the third decoder with are connected respectively with the third inputs of the third, fifth, first, sixth, second and fourth NAND elements, the direct and inverse outputs of the second trigger are connected respectively to the third inputs of the second and third decoders, characterized in that a second square-wave generator is additionally introduced into it, the fourth trigger, the third, fourth, fifth and sixth pulse shapers, the third element And, the third adder and the third register, and the second input of the second adder is connected to the signal bus characterizing to engine design, the inverse output of the second register is connected to the first input of the third adder, the second input of which is connected to the bus of the position sensor of the rotor of the synchronous motor, the senior discharge of the output of the third adder is connected to the first input of the fourth trigger, the output of which is connected to the first input of the third OR element, the output the second rectangular pulse generator is connected to the second input of the third OR element, the output of which is connected to the input of the second pulse former, the output of the second the pulse generator is connected to the input of the third pulse generator, the first input of the fourth counter and the second inputs of the first and second registers, the output of the third pulse generator is connected to the second input of the fourth trigger, the output of the fourth counter is connected to the first inputs of the binary-hex counter and the second element And, the output of which connected to the third input of the first register, the second input of the binary-hex counter connected to the sign bus of the input signal, the output of the binary-hex counter connected to the third input of the third register, the first, second and third outputs of which are connected respectively to the second, third and fourth inputs of the first decoder and the fourth, fifth and sixth inputs of the second and third decoders, the output of the first element And is connected to the inputs of the first and fourth pulse shapers, the output of the first the pulse shaper is connected to the fifth input of the first decoder, the direct output of the fourth pulse shaper is connected to the second input of the third register, the inverse output of the fourth pulse shaper owl is connected to the input of the fifth pulse shaper, the output of which is connected to the first input of the third element And, the output of the reset circuit is connected to the third input of the third register and the second input of the third element And, the output of which is connected to the input of the sixth pulse shaper, the second input of the fourth counter and the third input binary-hex counter, the output of the sixth pulse shaper is connected to the second input of the second element And and the third inputs of the second register and fourth trigger.

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