RU2475828C1 - Apparatus for generating control action to provide stable operation of complex engineering systems - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: apparatus has a correlator, a random process stabiliser, a computing unit, an exponentiation unit, a matrix transposition unit, OR elements, a multiplier unit, a control unit, AND elements, a matrix forming unit, a memory unit, a matrix inversion unit, adders, a comparator unit, a recorder, groups of input registers, an input register, a switch, a group of subtractor units, groups of square-wave generators, groups of multiplier units, a group of OR elements, accumulative adders, square-root extractors, delay elements, a divider unit, groups of registers, a group of switches, groups of display units, a minimum estimating unit, a group of comparator units, a group of delay elements, a clock pulse generator and a pulse distributor.

EFFECT: high accuracy of estimating an unknown distribution function of parameters which characterise complex engineering systems.

4 dwg

Description

The invention relates to computer technology and can be used to obtain information for decision-making during the operation of complex technical systems (STS) in order to ensure the specified requirements for their reliability.

A device for predicting reliability, comprising a correlator, a random process analyzer, a computing unit, an exponentiation unit, a memory unit, a differentiation unit, an adder, a recording unit, a matrix transpose unit and an additional computing unit (ed. Certificate of the USSR No. 746349, class. G01R 31/28, 1980).

The disadvantage of this device is the big errors in determining the synthesized properties of STS. The problem of synthesizing the requirements for the reliability of the STS is incorrect, and solving it using the square root method or the Gauss method results in a result that has large errors.

The closest analogue, prototype, is a device for determining the requirements for the parameters of technological devices, containing a correlator, a random process analyzer, a computing unit, an exponentiation block, a matrix transpose block, a first OR element, a product block, a control unit, a first And element, a block matrix generation, memory unit, matrix inversion, second and first adders, comparison unit, recorder, second OR element, second and third AND elements (ed. certificate of the USSR No. 798641, G01R 31/02, 1981).

The device hardware implements the expression

- функция надежности или вероятность того, что за время t=n×Δτ ни разу внешнее по отношению к эксплуатируемому устройству воздействие не превышает допустимого;Where

- the reliability function or the likelihood that during the time t = n × Δτ the exposure external to the operating device has never exceeded the permissible;

- функция распределения сопротивляемости, обоснования и исчерпывающая характеристика допустимого предела величин внешнего воздействия, приводящего устройство к отказу;

- the distribution function of resistance, justification and an exhaustive description of the permissible limit of the magnitude of the external impact, leading the device to failure;

- наибольшее случайное воздействие на интервале времени, равном периоду корреляции;

- the greatest random impact on a time interval equal to the correlation period;

- функция распределения наибольших значений внешнего воздействия;

- distribution function of the highest values of external influence;

n is the number of periods of correlation of the external action n = t / Δτ;

Δτ is the correlation period of the investigated signal;

- условная функция распределения внешнего воздействия относительно гипотезы о том, что предельное (допустимое) значение воздействия принадлежит элементарному отрезку

- conditional distribution function of the external action relative to the hypothesis that the limit (permissible) value of the effect belongs to the elementary segment

,

,

- вероятность элементарной гипотезы.

- the probability of an elementary hypothesis.

функции распределения сопротивляемости.When synthesizing the properties of STS, the device determines discrete values from expression (1)

distribution function of resistance.

и функции

распределения наибольших значений внешнего воздействия

.The initial information in this case for the operation of the device are the set values of the reliability function

and functions

distribution of the highest values of external influence

.

In this case, the device implements the algorithm resulting from the following transformations.

In the equation

характеризует требования к синтезируемой СТС. Эффективным методом решения системы линейных алгебраических уравнений вида (2) является метод Зейделя.representing the compact matrix form of the equation (1), vector

characterizes the requirements for synthesized STS. An effective method for solving a system of linear algebraic equations of the form (2) is the Seidel method.

To ensure positive definiteness of the matrix of the problem, we multiply the left and right sides of equation (2) by the matrix B ^T. As a result, instead of equation (2), the equation is solved

;where B ^T is the transportation matrix

;

- вектор правой части уравнения (2) - функция надежности.

is the vector of the right side of equation (2) is the reliability function.

We introduce the notation

We rewrite equations (3) taking into account the notation introduced

In vector-matrix form, the algorithm for solving system (6) by the Seidel method at the (n + 1) -th step of the iteration has the following form:

where φ ^{n + 1} is the desired approximation vector at the current (n + 1) -th step of the iteration;

φ ⁿ is the same in the previous iteration step.

which are obtained from the original matrix F.

The disadvantage of this device is the absence in the process of calculating the coefficient of stability, ensuring the stability of the solution obtained in the form of a distribution function of resistance. In addition, the conditions for obtaining the optimal solution are not specified.

The technical result of the claimed invention is to ensure the stability (stability) of the calculations and the implementation of the conditions for obtaining the optimal solution. All this, ultimately, leads to an increase in the accuracy of estimating the desired distribution function of various parameters of the STS and their stable operation due to the possibility of adjusting these parameters.

Ensure the stability of the solution as follows. In the first term of the right-hand side of formula (7), as a factor, it is necessary to introduce the values of the stability coefficient α _κ :

where k is the number of values of the coefficient α _k successively substituted into the formula (10);

α _k is the coefficient of regularization (stability) (its values are set on the basis of theoretical studies).

, которое является функцией распределения проектного значения сопротивляемости. Величина этого отклонения ε_k определяется по следующей формуле:The optimality of the obtained solution can be estimated by the criterion of the minimum of the Euclidean norm of deviation of the area under the curve φ _kl from the reference value

, which is a function of the distribution of the design resistance value. The magnitude of this deviation ε _k is determined by the following formula:

l = 1, ..., P; k = 1, ..., m;

where φ _kl are the values of the curve of the distribution function of the resistance obtained as a result of solution (10);

Δx is the length of the partition interval of the argument x of this function;

P is the number of intervals of this partition.

, характеризующие эталонные значения функции распределения сопротивляемости, информационный вход входного регистра является входом задания исходной информации, на который поступает значение Δх, характеризующее значение длины интервала разбиения аргумента х функции распределения сопротивляемости, выходы с первого по m-й элементов первой группы входных регистров соединены с первого по m-й входами третьего элемента ИЛИ, выход которого подключен к первому входу блока умножения, выход которого соединен с седьмым входом блока памяти, а второй вход через первый элемент И - с выходами блока произведения, выход каждого элемента второй группы входных регистров подключен к входам уменьшаемого соответствующих элементов группы блоков вычитания и к входам соответствующих элементов первой группы квадраторов, выход каждого из которых соединен с первым входом соответствующего элемента первой группы блоков умножения, второй вход которого подключен к первому выходу коммутатора, а выход - к входам с первого по Р-й первого накопительного сумматора, выход которого через первый блок извлечения квадратного корня соединен с входом делимого блока деления, вход делителя которого подключен через последовательно соединенные ЭЗ и второй блок извлечения квадратного корня к выходу второго накопительного сумматора, с первого по Р-й входы которого соединены с выходами с первого по Р-й элементов второй группы блоков умножения, первые входы каждого из которых подключены ко второму выходу коммутатора, а вторые входы - к выходам соответствующих элементов второй группы квадраторов, вход каждого из которых соединен с выходом соответствующего элемента группы блоков вычитания, вход вычитаемого каждого из которых подключен к выходу соответствующего элемента группы элементов ИЛИ, с первого по m-й входы каждого из которых соединены со вторыми выходами каждого элемента соответствующей строки группы коммутаторов, вторые выходы каждого из элемента которой подключены к входам соответствующих элементов первой группы блоков индикации, а информационные входы элементов группы коммутаторов - к выходам соответствующих элементов первой группы регистров, информационный вход каждого из которых соединен с множественным выходом второго сумматора, выход блока деления подключен к информационному входу каждого элемента второй группы регистров, выходы которых соединены с входами соответствующих элементов группы ЭЗ и с первого по m-й входами блока оценки минимального значения, выход которого подключен к пороговому входу каждого элемента группы блоков сравнения, информационные входы которых соединены с выходами соответствующих элементов группы ЭЗ, а выходы - с входами соответствующих элементов второй группы блоков индикации.The technical result is achieved by the fact that the device for generating control actions to ensure the stable operation of complex technical systems, containing a correlator and a random process analyzer, the first input of which is connected to the input of the device, and the second input to the output of the correlator, the input of which is connected to the input of the device, connected in series a computing unit, the input of which is connected to the output of a random process analyzer, an exponentiation unit and a matrix transportation unit, a control unit, ith adder, memory unit, product unit, matrix inversion unit, recorder, three AND elements, two OR elements, matrix forming unit, second adder and comparison unit, four inputs of the memory unit are connected respectively to the corresponding outputs of the control unit, the fifth input is connected to the input devices, the sixth input - with the first output of the second adder, from the first to third outputs through the first element OR - with the first input of the product block, and the fourth output - with the first input of the second adder, the second input of which is through the second element AND so inen with the output of the product block connected through the third AND element to the first input of the matrix forming unit, the first output of which is connected to the first input of the second OR element, and the second output through the matrix circulation unit with the fourth input of the first OR element, the third input of the second adder is connected to the output of the comparison unit, the outputs of the control unit are connected to the second inputs of the first, second and third elements And and to the second and third inputs of the matrix forming unit, and the input to the output of the comparison unit, the input of which is connected through Without the first adder with the first output of the second adder, the second output of which is connected to the recorder, the input of the matrix transportation unit is connected to the fifth input of the first OR element, and the output to the second input of the second OR element connected by the output to the second input of the product block, additionally contains the first and the second group of input registers, the first of which consists of m elements, and the second of P elements, the input register, the third OR element, commutator, multiplication block, a group of subtraction blocks, the first and second quadra groups Orov, the first and second groups of multiplication blocks, the group of OR elements, each of which consists of P elements, the first and second accumulative adders, the first and second square root blocks, the delay element (EI), the division block, the first group of j registers, the group switches, the first group of indication blocks, each of which consists of m × p elements, the minimum value estimation block, the second group of registers, the group of comparison blocks, the EZ group, the second group of indication blocks, each of which consists of m elements, a clock generator new pulses and a pulse distributor, the clock input of which is connected to the output of the clock generator, the first output is with the recording inputs of each element of the first and second groups of input registers and the input of the input register, the second through mth outputs are with the reading inputs from the first to m-th elements of the first group of input registers, 2 + m-th output - with a record entry of each element of the first column of the first group of registers, 3 + m-th output - with a read input of each element of the second group of input registers, 4 + m-th output - with control input each element of the switch group, 5 + m-th output - with input input of the input register, 6 + m-th output - with control input of the switch, from 7 + m-th to 6 + 2 m-th outputs - with recording inputs from the first to m-th elements of the second group of registers, 2 + 3m-th output - with a read input of each element of the first column of the first group of registers, 4 + 4m-th and 5 + 4-m outputs - respectively, with write and read inputs of each element of the m-th column of the first group of registers, 1 + 5th output - with the read input of each element of the second group of registers and with the control input of the mini evaluation unit of the maximum value, the information inputs of the first group of input registers are inputs of the input information, to which the values α _k characterizing the value of the stability coefficient for the k-th version of the calculations are received, the information inputs of the second group of input registers are inputs of the input of the initial information to which the values are supplied

characterizing the reference values of the resistance distribution function, the information input of the input register is the input of the input of the initial information, to which the value Δx characterizing the value of the length of the partition interval of the argument x of the resistance distribution function is received, the outputs from the first to the mth elements of the first group of input registers are connected to the first by the m-th inputs of the third OR element, the output of which is connected to the first input of the multiplication block, the output of which is connected to the seventh input of the memory block, and the second the input through the first element And - with the outputs of the product block, the output of each element of the second group of input registers is connected to the inputs of the reduced corresponding elements of the group of subtraction blocks and to the inputs of the corresponding elements of the first group of quadrators, the output of each of which is connected to the first input of the corresponding element of the first group of blocks multiplication, the second input of which is connected to the first output of the switch, and the output to the inputs from the first to the Pth first accumulative adder, the output of which through the first block the square root cross section is connected to the input of the divisible division unit, the input of the divider of which is connected through series-connected EHs and the second square root extraction unit to the output of the second accumulative adder, from the first to the Pth inputs of which are connected to the outputs from the first to the Pth elements of the second group multiplication units, the first inputs of each of which are connected to the second output of the switch, and the second inputs to the outputs of the corresponding elements of the second group of quadrators, the input of each of which is connected to the output respectively unit of the group of subtraction blocks, the input of each of which is subtracted is connected to the output of the corresponding element of the group of OR elements, the first through mth inputs of each of which are connected to the second outputs of each element of the corresponding row of the switch group, the second outputs of each of which are connected to the inputs the corresponding elements of the first group of indication blocks, and the information inputs of the elements of the switch group to the outputs of the corresponding elements of the first group of registers, the information input is of which is connected to the multiple output of the second adder, the output of the division unit is connected to the information input of each element of the second group of registers, the outputs of which are connected to the inputs of the corresponding elements of the EZ group and from the first through mth inputs of the minimum value estimator, the output of which is connected to the threshold the input of each element of the group of comparison blocks, the information inputs of which are connected to the outputs of the corresponding elements of the EZ group, and the outputs - with the inputs of the corresponding elements of the second group of blocks Superimpose.

Figure 1, 2 and 3 presents a functional diagram of a device for making decisions during the operation of complex technical systems (to avoid cumbersome communications between the RI and the control inputs of the respective blocks are not shown completely, but are indicated by numbering the inputs and outputs).

Figure 4 shows the cyclogram of the operation of the device (the ordinates indicate the numbers of the outputs of the RI, and the abscissa indicates the number of packets), and the duration of various computational operations (extracting the square root is twenty clock cycles, squaring is eight cycles, multiplication is eight cycles , division — sixteen measures, addition of eight terms — seven measures) in the upper part of FIG. 4 (for the possibility of execution of the cyclogram, m = 5, P = 8, although the values can take arbitrary values). Since it is difficult to determine the duration of the computational operations by some blocks of the prototype, “gaps” are made on the abscissa axis.

A control action generating device for ensuring the stable operation of complex technical systems (FIGS. 1, 2 and 3) contains a correlator 1, a random process analyzer 2, a computing unit 3, a power raising unit 4, a matrix transportation unit 5, a first OR element 6, a block 7 products, control unit 8, the first element And 9, the matrix generation unit 10, the memory unit 11, the matrix inversion unit 12, the second 13 and the first 14 adders, the comparison unit 15, the recorder 16, the second element OR 17, the second 18 and the third 19 elements And, the first 20 and second 21 groups input registers, the first of which consists of m elements, and the second of P elements, input register 22, third OR element 23, switch 24, multiplication block 25, a group of 26 subtraction blocks, the first 27 and second 28 groups of quadrants, the first 29 and the second 30 groups of multiplication blocks, a group of 31 OR elements, each of which consists of P elements, the first 32 and second 33 accumulative adders, the first 34 and second 35 square root extraction blocks, the delay element 36, the division block 37, the first group of 38 registers, group of 39 switches, the first group of 40 blocks of indicators stations, each of which consists of m × P elements, a block for estimating the minimum value, a second group of 42 registers, a group of 43 comparison blocks, a group of 44 EZs, a second group of 45 indication blocks, each of which consists of m elements, a clock generator 46 and RI 47.

It should be emphasized that newly introduced blocks and elements are standard.

Information about the blocks and elements of the device is described in the following sources:

1. Charge coupled devices. / Ed. M. Howes and D. Morgan: Trans. from English - M.: Energoizdat, 1981. - 376 p., Ill.

2. User Guide for Signal Microprocessors ADSP-2100. / Per. from English O.V. Luneva. Ed. A.D. Viktorov; St. Petersburg State Electrotechnical University. - St. Petersburg, 1997 .-- 520 p.

3. V. B. Steshenko. FPGA company "ALTERA": Design of signal processing devices. / M .: Dodeka, 2000.

l-го сечения функции распределения сопротивляемости исследуемой СТС. На информационный вход входного регистра 22 засылается длина Δх интервала разбиения аргумента х функции распределения сопротивляемости. При этом управляющий сигнал на входы записи групп 20 и 21 и регистра 22 подается с первого выхода РИ 47, темпы работы которого задаются генератором 46 тактовых импульсов.The device forming control actions to ensure the stable operation of complex technical systems works as follows. The information inputs of each of the elements of the first group of 20 input registers are sent stability coefficients α _k for the Kth version of the calculations. The information inputs of each of the elements of the second group of 21 input registers are fed with the values of the reference value

l-section of the distribution function of the resistance of the studied STS. At the information input of the input register 22, the length Δx of the partition interval of the argument x of the resistance distribution function is sent. In this case, the control signal to the recording inputs of groups 20 and 21 and register 22 is supplied from the first output of RI 47, the pace of which is set by the generator 46 clock pulses.

The next step in evaluating the distribution function of the resistance is carried out mainly using the blocks of the prototype.

которая поступает в блок 4, где возводится в степень n. Информация с выхода блока 4 представляет собой матрицу В уравнения (3), которая в блоке 5 преобразуется в матрицу В^T. С выхода блоков 4 и 5 через элементы 6 и 17 матрицы В и В^T поступают в блок 7. Полученная в результате перемножения матрица Ф по сигналу K1 блока через элемент И 19 засылается в блок 10, где преобразуется в две треугольные матрицы А и D.Information about the loads on the studied DUT, presented in the form of a signal U (t), is fed to the input of the correlator 1 and to the input of the analyzer 2. In the correlator 1, the autocorrelation function of the studied signal is determined, and the correlation period Δτ is calculated from it. The correlation period is set by analyzer 2, in which the signal under investigation is divided into intervals Δτ, and then the largest value is determined in each of the obtained intervals. The selected values of the maximums from the intervals of the partition of the investigated signal by block 3 determines the conditional probability

which goes to block 4, where it is raised to the power of n. The information from the output of block 4 is a matrix B of equation (3), which in block 5 is converted into a matrix B ^T. From the output of blocks 4 and 5, through the elements 6 and 17, the matrices B and B ^T enter block 7. The matrix Ф obtained as a result of multiplication by the signal K1 of the block through the element And 19 is sent to block 10, where it is converted into two triangular matrices A and D.

Blocks 5 and 10 are almost identical and are made according to a single scheme. They consist of two counters (integer adders) for generating the current row numbers i and column j of the matrix, a unit for sending numbers to select numbers from the matrix and writing these numbers to the matrix at the given numbers i and j and the block (s) of memory to store the original and formed matrices. The only difference is that in block 5, one memory block is enough for matrix B, since transposing the matrix reduces to the fact that the transfer block swaps the elements of matrix B symmetrical with respect to the main diagonal, i.e. b _ij ⇆b _ji . In block 10, two memory blocks are required, in one of which the original matrix Φ is stored, converted as a result of the operation of the transfer unit into the lower triangular matrix, and in the other, the upper triangular matrix A formed by the transfer unit

By command K2 of block 8 from block 11, the vector r is sent through block OR 6 to block 7, where it is multiplied with the value B ^T stored there. In this case, the vector C is calculated.

At the next stage of the device operation, by the control signal K3 of block 8, the matrix D is transmitted through block 12 and the OR element 6 to block 7, where the value D ^{-1 is} multiplied with the value C - the result of the previous operation. The result of multiplication is the vector g, which, according to the command K4 of block 8, is sent through block AND 9 to block 11.

In block 7, by command K5 of block 8, matrix A is sent through the OR element 6, where it is multiplied with matrix D ^-1 . The matrix H obtained as a result of multiplication by a command K6 of block 8 through element And 9 is sent to the second input of multiplication block 25, to the first input of which, by the control signal from the second output of RI 47, to the read input of the first element of the first group of 20 input registers from the output of this element, the quantity α ₁ (values of the stability coefficient for the first version of the calculations) is supplied through the third element OR 23. The result of this multiplication is sent from the output of block 25 to the input of block 11 of the memory. On this, the prepared operations for calculating the unknown φ _kl by the Seidel method end.

By the command K7 of block 8 from block 11, the value Н is sent through the OR element 6 to block 7, and by the command K8, the approximate φ ° value of the desired function φ is transmitted through the OR element 6 to block 7. If information on the approximate value is not available, then, as a first approximation, in block 7, the value φ ° = 1 is recorded.

In block 7, the matrix H and the vector φ ° are multiplied, and the product, according to the K9 command, is sent through the And 18 element to the adder 13, where the vector g arrives at the K8 command of the block 8 from block 11. From the output of the adder 13, the desired value of the first iteration step (hereinafter n + 1 steps) is fed to the adder 14, where the difference Δ _n = φ _n -φ _{n + 1} is determined, and to block 11, where it is written instead of φ °. From the adder 14, the value of Δ _n enters the block 15, where the value of Δ _{n is} compared with a given calculation error Δ. Further, in this block, the error of the (n + 1) -th iteration step is compared with Δ. If, as a result of the comparison, it turns out that Δ _n-1 ≤Δ, then the iterative process of determining the function φ by the command of block 15 to block 8 is terminated and the value of the desired function φ of the adder 13 is output to register 16 by the same command, and block 8 is initialized state. Otherwise, the iterative process of computing the function φ continues with the required accuracy, which is achieved by repeated submission of commands K7-K9 from block 8.

From the output of the second adder 13, the values of φ _{1l of the} first embodiment of the calculation of the distribution function of the resistance are sent to the corresponding elements of the first group of 38 registers. However, the recording will be carried out only in the first column of this group, because the signal from the 2 + mth output of RI 47 will be fed to the recording inputs only from the first to the rth elements of the first of m columns.

с выходов элементов этой группы направляются на входы уменьшаемого соответствующих элементов группы 26 блоков вычитания и на входы первой группы 27 квадраторов. По сигналу с 5+m-го выхода РИ 47 на вход считывания входного регистра 22 величина Δх поступает через коммутатор 24 на вторые выходы первой группы 29 блоков умножения и на первые входы второй группы 30 блоков вычитания. По сигналу с 2+3m-го выхода РИ 47 на входы считывания первой группы 38 регистров значения φ_kl с выходов элементов первого столбца этой группы через соответствующие элементы группы 39 коммутаторов и группы 31 элементов ИЛИ подаются на входы вычитаемого соответствующих элементов группы 26 блоков вычитания.According to the signal from the 3 + m-th output of RI 47 to the read inputs of the second group of 21 input value registers

from the outputs of the elements of this group are directed to the inputs of the reduced corresponding elements of the group 26 of the subtraction blocks and to the inputs of the first group of 27 quadrators. According to the signal from the 5 + mth output of RI 47 to the read input of the input register 22, the quantity Δx is supplied through the switch 24 to the second outputs of the first group 29 of multiplication units and to the first inputs of the second group 30 of subtraction units. According to the signal from the 2 + 3mth output of RI 47 to the read inputs of the first group of 38 registers, the values of φ _kl from the outputs of the elements of the first column of this group through the corresponding elements of the group of 39 switches and the group of 31 elements OR are fed to the inputs of the deductible corresponding elements of the group 26 of the subtraction blocks.

Groups of elements 26, 28, 30 and blocks 33, 35 calculate the numerator of formula (11). Groups of elements 27, 29 and blocks 32, 34 evaluate the denominator of formula (11). Due to the presence of EZ 36, the values of the numerator and denominator arrive simultaneously at the inputs of the divisible and divisor of the division unit 37, the output of which the deviation ε ₁ in accordance with formula (11) for the first option is sent to the information inputs of each element of the second group of 42 registers. However, this value will be recorded only in the first element of group 42, since the signal at the recording input from the 7 + mth output of RI 47 will be supplied only to the first element of this group.

In the future, the operation of the device proceeds according to the already indicated scheme, i.e. calculations are made in the second embodiment α ₂ stability coefficient. The operation of the device will end when the calculation is performed with the last m-th version (α _k = α _m ) and the results of all calculations are analyzed. The order of operation of the device shown in the sequence diagram (figure 4).

отклонения направляется на пороговые входы всех элементов группы 43. Каждый элемент этой группы настроен следующим образом: если

, то на выходе элемента будет сигнал. В случае когда

, сигнал на выходе элемента будет отсутствовать. Следовательно, во второй группе 45 блоков индикации будет высвечиваться номер варианта вычислений, соответствующий минимальной ошибке. Поэтому в качестве оптимального нужно выбирать тот вариант функции распределения сопротивляемости анализируемой СТС, который обеспечивает минимальную ошибку.After writing in the elements of the second group of 42 registers of all m deviation values ε _k according to the signal from the 1 + 5m-th output of RI 47 to the readout inputs of all elements of this group from their outputs, the values of ε _{k are} sent through the corresponding elements of group 44 EZ to the information inputs of group 43 comparison blocks. In addition, the values of ε _k are also supplied to the inputs, from the first to the mth, of the minimum value estimation unit 41, from the output of which the minimum value

deviations are sent to the threshold inputs of all elements of group 43. Each element of this group is configured as follows: if

, then there will be a signal at the output of the element. In the case when

, there will be no signal at the output of the element. Therefore, in the second group of 45 display units, the number of the calculation option corresponding to the minimum error will be displayed. Therefore, as an optimal one, one must choose the variant of the resistance distribution function of the analyzed STS that provides the minimum error.

Thus, the technical result of the claimed invention is achieved not due to the mathematical apparatus, but using the technical means (blocks and elements) mentioned in the description of the operation of the device.

The described device allows to ensure the stability of calculations and to implement the conditions for obtaining the optimal solution. This makes it possible to increase the accuracy of estimating the desired distribution function of the parameters characterizing the STS.

The industrial applicability of the invention is justified by the fact that it can be used in various fields (industries) of production upon receipt of information for decision-making during the operation of the STS in order to ensure the specified requirements for their reliability.

Claims (1)

A device for generating control actions to ensure the stable operation of complex technical systems, containing a correlator and a random process analyzer, the first input of which is connected to the input of the device, and the second input - to the output of the correlator, the input of which is connected to the input of the device, the computing unit is connected in series, the input of which is connected to the output of the random process analyzer, the exponentiation unit and the matrix transportation unit, the control unit, the first adder, the memory unit, the product unit , matrix conversion unit, recorder, three AND elements, two OR elements, matrix forming unit, second adder and comparison unit, four inputs of the memory unit are connected respectively to the corresponding outputs of the control unit, the fifth input is with the input of the device, the sixth input is with the first output the second adder, from the first to the third outputs through the first OR element - with the first input of the product block, and the fourth output - with the first input of the second adder, the second input of which is connected through the second AND element to the output of the product block, connected through the third AND element with the first input of the matrix forming unit, the first output of which is connected to the first input of the second OR element, and the second output - through the matrix inversion unit with the fourth input of the first OR element, the third input of the second adder is connected to the output of the comparison unit, block outputs the controls are connected to the second inputs of the first, second and third AND elements and to the second and third inputs of the matrix forming unit, and the input is connected to the output of the comparison unit, the input of which is connected through the first adder to the first output of the second an adder, the second output of which is connected to the recorder, the input of the matrix transporting unit is connected to the fifth input of the first OR element, and the output is to the second input of the second OR element, connected by the output to the second input of the product block, characterized in that it does not have a direct connection between the first element And and a memory unit and it additionally contains the first and second groups of input registers, the first of which consists of m elements, and the second of P elements, input register, third OR element, switch, block multiplications, a group of subtraction blocks, the first and second groups of quadrators, the first and second groups of multiplication blocks, a group of OR elements, each of which consists of P elements, the first and second accumulative adders, the first and second blocks of square root extraction, the delay element (EI) , division block, the first group of j registers, the group of switches, the first group of indication blocks, each of which consists of m × p elements, the minimum value estimation block, the second group of registers, the group of comparison blocks, the EZ group, the second group of blocks indications, each of which consists of m elements, a clock generator and a pulse distributor, the clock input of which is connected to the output of the clock generator, the first output - with the recording inputs of each element of the first and second groups of input registers and the input of the input register entry, from second to 1 + m-th outputs - with read inputs from the first to m-th elements of the first group of input registers, 2 + m-th output - with the write input of each element of the first column of the first group of registers, 3 + m-th output - with the read input each item the second group of input registers, 4 + m-th output - with the control input of each element of the switch group, 5 + m-th output - with the read input of the input register, 6 + m-th output - with the control input of the switch, with 7 + m- go to the 6 + 2m-th outputs - with recording inputs from the first to the m-th elements of the second group of registers, 1 + 3-m-th output - with the read input of each element of the first column of the first group of registers, 4 + 4 m and 5 + 4 m -th outputs - respectively, with write and read inputs of each element of the mth column of the first group of registers, 1 + 5th output - with the read input of each element a second group of registers and a control input unit estimates the minimum value data inputs of the first group of input registers are inputs job source information, which receives values α _k, characterizing value stability coefficient for the k-th embodiment computation data inputs of the second group of input registers are inputs assignment of initial information to which values are supplied

characterizing the reference values of the resistance distribution function, the information input of the input register is the input of the input of the initial information, to which the value Δx characterizing the value of the length of the partition interval of the argument x of the resistance distribution function is received, the outputs from the first to the mth elements of the first group of input registers are connected to the first by the m-th inputs of the third OR element, the output of which is connected to the first input of the multiplication block, the output of which is connected to the seventh input of the memory block, and the second the input through the first element And - with the outputs of the product block, the output of each element of the second group of input registers is connected to the inputs of the reduced corresponding elements of the group of subtraction blocks and to the inputs of the corresponding elements of the first group of quadrators, the output of each of which is connected to the first input of the corresponding element of the first group of blocks multiplication, the second input of which is connected to the first output of the switch, and the output to the inputs from the first to the Pth first accumulative adder, the output of which through the first block the square root cross section is connected to the input of the divisible division unit, the input of the divider of which is connected through series-connected EHs and the second square root extraction unit to the output of the second accumulative adder, from the first to the Pth inputs of which are connected to the outputs from the first to the Pth elements of the second group multiplication units, the first inputs of each of which are connected to the second output of the switch, and the second inputs to the outputs of the corresponding elements of the second group of quadrators, the input of each of which is connected to the output respectively unit of the group of subtraction blocks, the input of each of which is subtracted is connected to the output of the corresponding element of the group of OR elements, the first through mth inputs of each of which are connected to the second outputs of each element of the corresponding row of the switch group, the second outputs of each of which are connected to the inputs the corresponding elements of the first group of indication blocks, and the information inputs of the elements of the switch group to the outputs of the corresponding elements of the first group of registers, the information input is of which is connected to the multiple output of the second adder, the output of the division unit is connected to the information input of each element of the second group of registers, the outputs of which are connected to the inputs of the corresponding elements of the EZ group and from the first through mth inputs of the minimum value estimator, the output of which is connected to the threshold the input of each element of the group of comparison blocks, the information inputs of which are connected to the outputs of the corresponding elements of the EZ group, and the outputs - with the inputs of the corresponding elements of the second group of blocks Superimpose.

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